15 commits

Author	SHA1	Message	Date
Exzap	f11cfa0dc5	PPCRec: Rework RLWIMI	2025-04-26 00:27:15 +02:00
Exzap	05e3cfe5c9	PPCRec: Code cleanup	2025-04-26 00:27:14 +02:00
Exzap	8270308ccc	PPCRec: Refactor read/write access tracking for liveness ranges	2025-04-26 00:24:43 +02:00
Exzap	547cf501d0	PPCRec: Update spill cost calculation	2025-04-26 00:24:43 +02:00
Exzap	f94f99546d	PPCRec: Fixes and optimizations + rework FRES/FRSQRTE	2025-04-26 00:24:43 +02:00
Exzap	972d0ed05d	PPCRec: Clean up code and optimize	2025-04-26 00:24:43 +02:00
Exzap	b55785a0a0	PPCRec: Support for arbitrary function calls in the IR ... Used for MFTBU/MFTBL instruction	2025-04-26 00:22:37 +02:00
Exzap	4517c209d5	PPCRec: Some fixes	2025-04-26 00:22:37 +02:00
Exzap	aa946ae42d	PPCRec: Add RA support for instructions with register constraints ... Also make interval tracking more fine grained and differentiate between input and output edges of each instruction	2025-04-26 00:22:37 +02:00
Exzap	675c802cc1	PPCRec: Simplify RA code and clean it up a bit	2025-04-26 00:22:37 +02:00
Exzap	1cc458c543	PPCRec: Implement MFCR and MTCRF	2025-04-26 00:22:37 +02:00
Exzap	c786ba0ebb	PPCRec: Further work on support for typed registers in RA ... Additionally there is no more range limit for virtual RegIDs, making the entire uint16 space available in theory	2025-04-26 00:22:37 +02:00
Exzap	948e33f9bf	PPCRec: Unify code + misc RA preparation ... Whoopsie	2025-04-26 00:22:36 +02:00
Exzap	0622631868	PPCRec: Move X64 files into subdirectory and rename	2025-04-26 00:22:35 +02:00
Exzap	411a83799c	PPCRec: Move IML register allocator	2025-04-26 00:22:35 +02:00

Renamed from src/Cafe/HW/Espresso/Recompiler/PPCRecompilerImlRanges.cpp (Browse further)