mirror of
https://github.com/cemu-project/Cemu.git
synced 2025-07-06 15:01:18 +12:00
727 lines
No EOL
26 KiB
C++
727 lines
No EOL
26 KiB
C++
#include "../PPCRecompiler.h"
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#include "../PPCRecompilerIml.h"
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#include "IMLRegisterAllocatorRanges.h"
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#include "util/helpers/MemoryPool.h"
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uint32 PPCRecRA_getNextIterationIndex();
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IMLRegID raLivenessRange::GetVirtualRegister() const
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{
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return virtualRegister;
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}
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sint32 raLivenessRange::GetPhysicalRegister() const
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{
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return physicalRegister;
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}
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IMLName raLivenessRange::GetName() const
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{
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return name;
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}
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void raLivenessRange::SetPhysicalRegister(sint32 physicalRegister)
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{
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this->physicalRegister = physicalRegister;
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}
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void raLivenessRange::SetPhysicalRegisterForCluster(sint32 physicalRegister)
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{
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auto clusterRanges = GetAllSubrangesInCluster();
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for(auto& range : clusterRanges)
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range->physicalRegister = physicalRegister;
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}
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boost::container::small_vector<raLivenessRange*, 128> raLivenessRange::GetAllSubrangesInCluster()
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{
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uint32 iterationIndex = PPCRecRA_getNextIterationIndex();
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boost::container::small_vector<raLivenessRange*, 128> subranges;
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subranges.push_back(this);
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this->lastIterationIndex = iterationIndex;
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size_t i = 0;
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while(i<subranges.size())
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{
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raLivenessRange* cur = subranges[i];
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i++;
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// check successors
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if(cur->subrangeBranchTaken && cur->subrangeBranchTaken->lastIterationIndex != iterationIndex)
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{
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cur->subrangeBranchTaken->lastIterationIndex = iterationIndex;
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subranges.push_back(cur->subrangeBranchTaken);
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}
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if(cur->subrangeBranchNotTaken && cur->subrangeBranchNotTaken->lastIterationIndex != iterationIndex)
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{
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cur->subrangeBranchNotTaken->lastIterationIndex = iterationIndex;
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subranges.push_back(cur->subrangeBranchNotTaken);
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}
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// check predecessors
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for(auto& prev : cur->previousRanges)
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{
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if(prev->lastIterationIndex != iterationIndex)
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{
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prev->lastIterationIndex = iterationIndex;
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subranges.push_back(prev);
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}
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}
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}
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return subranges;
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}
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bool raLivenessRange::GetAllowedRegistersEx(IMLPhysRegisterSet& allowedRegisters)
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{
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if(interval2.ExtendsPreviousSegment() || interval2.ExtendsIntoNextSegment())
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{
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auto clusterRanges = GetAllSubrangesInCluster();
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bool hasAnyRequirement = false;
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for(auto& subrange : clusterRanges)
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{
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if(subrange->list_fixedRegRequirements.empty())
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continue;
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allowedRegisters = subrange->list_fixedRegRequirements.front().allowedReg;
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hasAnyRequirement = true;
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break;
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}
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if(!hasAnyRequirement)
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return false;
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for(auto& subrange : clusterRanges)
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{
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for(auto& fixedRegLoc : subrange->list_fixedRegRequirements)
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allowedRegisters &= fixedRegLoc.allowedReg;
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}
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}
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else
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{
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// local check only, slightly faster
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if(list_fixedRegRequirements.empty())
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return false;
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allowedRegisters = list_fixedRegRequirements.front().allowedReg;
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for(auto& fixedRegLoc : list_fixedRegRequirements)
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allowedRegisters &= fixedRegLoc.allowedReg;
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}
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return true;
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}
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IMLPhysRegisterSet raLivenessRange::GetAllowedRegisters(IMLPhysRegisterSet regPool)
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{
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IMLPhysRegisterSet fixedRegRequirements = regPool;
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if(interval2.ExtendsPreviousSegment() || interval2.ExtendsIntoNextSegment())
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{
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auto clusterRanges = GetAllSubrangesInCluster();
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for(auto& subrange : clusterRanges)
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{
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for(auto& fixedRegLoc : subrange->list_fixedRegRequirements)
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fixedRegRequirements &= fixedRegLoc.allowedReg;
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}
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return fixedRegRequirements;
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}
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for(auto& fixedRegLoc : list_fixedRegRequirements)
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fixedRegRequirements &= fixedRegLoc.allowedReg;
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return fixedRegRequirements;
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}
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void PPCRecRARange_addLink_perVirtualGPR(std::unordered_map<IMLRegID, raLivenessRange*>& root, raLivenessRange* subrange)
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{
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IMLRegID regId = subrange->GetVirtualRegister();
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auto it = root.find(regId);
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if (it == root.end())
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{
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// new single element
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root.try_emplace(regId, subrange);
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subrange->link_sameVirtualRegister.prev = nullptr;
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subrange->link_sameVirtualRegister.next = nullptr;
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}
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else
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{
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// insert in first position
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raLivenessRange* priorFirst = it->second;
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subrange->link_sameVirtualRegister.next = priorFirst;
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it->second = subrange;
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subrange->link_sameVirtualRegister.prev = nullptr;
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priorFirst->link_sameVirtualRegister.prev = subrange;
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}
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}
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void PPCRecRARange_addLink_allSegmentRanges(raLivenessRange** root, raLivenessRange* subrange)
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{
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subrange->link_allSegmentRanges.next = *root;
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if (*root)
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(*root)->link_allSegmentRanges.prev = subrange;
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subrange->link_allSegmentRanges.prev = nullptr;
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*root = subrange;
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}
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void PPCRecRARange_removeLink_perVirtualGPR(std::unordered_map<IMLRegID, raLivenessRange*>& root, raLivenessRange* subrange)
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{
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#ifdef CEMU_DEBUG_ASSERT
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raLivenessRange* cur = root.find(subrange->GetVirtualRegister())->second;
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bool hasRangeFound = false;
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while(cur)
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{
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if(cur == subrange)
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{
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hasRangeFound = true;
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break;
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}
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cur = cur->link_sameVirtualRegister.next;
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}
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cemu_assert_debug(hasRangeFound);
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#endif
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IMLRegID regId = subrange->GetVirtualRegister();
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raLivenessRange* nextRange = subrange->link_sameVirtualRegister.next;
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raLivenessRange* prevRange = subrange->link_sameVirtualRegister.prev;
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raLivenessRange* newBase = prevRange ? prevRange : nextRange;
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if (prevRange)
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prevRange->link_sameVirtualRegister.next = subrange->link_sameVirtualRegister.next;
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if (nextRange)
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nextRange->link_sameVirtualRegister.prev = subrange->link_sameVirtualRegister.prev;
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if (!prevRange)
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{
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if (nextRange)
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{
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root.find(regId)->second = nextRange;
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}
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else
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{
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cemu_assert_debug(root.find(regId)->second == subrange);
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root.erase(regId);
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}
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}
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#ifdef CEMU_DEBUG_ASSERT
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subrange->link_sameVirtualRegister.prev = (raLivenessRange*)1;
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subrange->link_sameVirtualRegister.next = (raLivenessRange*)1;
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#endif
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}
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void PPCRecRARange_removeLink_allSegmentRanges(raLivenessRange** root, raLivenessRange* subrange)
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{
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raLivenessRange* tempPrev = subrange->link_allSegmentRanges.prev;
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if (subrange->link_allSegmentRanges.prev)
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subrange->link_allSegmentRanges.prev->link_allSegmentRanges.next = subrange->link_allSegmentRanges.next;
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else
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(*root) = subrange->link_allSegmentRanges.next;
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if (subrange->link_allSegmentRanges.next)
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subrange->link_allSegmentRanges.next->link_allSegmentRanges.prev = tempPrev;
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#ifdef CEMU_DEBUG_ASSERT
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subrange->link_allSegmentRanges.prev = (raLivenessRange*)1;
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subrange->link_allSegmentRanges.next = (raLivenessRange*)1;
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#endif
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}
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MemoryPoolPermanentObjects<raLivenessRange> memPool_livenessSubrange(4096);
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// startPosition and endPosition are inclusive
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raLivenessRange* PPCRecRA_createSubrange2(ppcImlGenContext_t* ppcImlGenContext, IMLSegment* imlSegment, IMLRegID virtualRegister, IMLName name, raInstructionEdge startPosition, raInstructionEdge endPosition)
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{
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raLivenessRange* range = memPool_livenessSubrange.acquireObj();
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range->previousRanges.clear();
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range->list_locations.clear();
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range->list_fixedRegRequirements.clear();
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range->imlSegment = imlSegment;
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cemu_assert_debug(startPosition <= endPosition);
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range->interval2.start = startPosition;
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range->interval2.end = endPosition;
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// register mapping
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range->virtualRegister = virtualRegister;
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range->name = name;
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range->physicalRegister = -1;
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// default values
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range->hasStore = false;
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range->hasStoreDelayed = false;
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range->lastIterationIndex = 0;
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range->subrangeBranchNotTaken = nullptr;
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range->subrangeBranchTaken = nullptr;
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cemu_assert_debug(range->previousRanges.empty());
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range->_noLoad = false;
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// add to segment linked lists
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PPCRecRARange_addLink_perVirtualGPR(imlSegment->raInfo.linkedList_perVirtualRegister, range);
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PPCRecRARange_addLink_allSegmentRanges(&imlSegment->raInfo.linkedList_allSubranges, range);
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return range;
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}
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void _unlinkSubrange(raLivenessRange* subrange)
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{
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IMLSegment* imlSegment = subrange->imlSegment;
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PPCRecRARange_removeLink_perVirtualGPR(imlSegment->raInfo.linkedList_perVirtualRegister, subrange);
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PPCRecRARange_removeLink_allSegmentRanges(&imlSegment->raInfo.linkedList_allSubranges, subrange);
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// unlink reverse references
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if(subrange->subrangeBranchTaken)
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subrange->subrangeBranchTaken->previousRanges.erase(std::find(subrange->subrangeBranchTaken->previousRanges.begin(), subrange->subrangeBranchTaken->previousRanges.end(), subrange));
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if(subrange->subrangeBranchNotTaken)
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subrange->subrangeBranchNotTaken->previousRanges.erase(std::find(subrange->subrangeBranchNotTaken->previousRanges.begin(), subrange->subrangeBranchNotTaken->previousRanges.end(), subrange));
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subrange->subrangeBranchTaken = (raLivenessRange*)(uintptr_t)-1;
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subrange->subrangeBranchNotTaken = (raLivenessRange*)(uintptr_t)-1;
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// remove forward references
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for(auto& prev : subrange->previousRanges)
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{
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if(prev->subrangeBranchTaken == subrange)
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prev->subrangeBranchTaken = nullptr;
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if(prev->subrangeBranchNotTaken == subrange)
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prev->subrangeBranchNotTaken = nullptr;
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}
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subrange->previousRanges.clear();
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}
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void PPCRecRA_deleteSubrange(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange* subrange)
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{
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_unlinkSubrange(subrange);
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//subrange->range->list_subranges.erase(std::find(subrange->range->list_subranges.begin(), subrange->range->list_subranges.end(), subrange));
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subrange->list_locations.clear();
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//PPCRecompilerIml_removeSegmentPoint(&subrange->interval.start);
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//PPCRecompilerIml_removeSegmentPoint(&subrange->interval.end);
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memPool_livenessSubrange.releaseObj(subrange);
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}
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// leaves range and linked ranges in invalid state. Only use at final clean up when no range is going to be accessed anymore
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void _PPCRecRA_deleteSubrangeNoUnlink(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange* subrange)
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{
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_unlinkSubrange(subrange);
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//PPCRecompilerIml_removeSegmentPoint(&subrange->interval.start);
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//PPCRecompilerIml_removeSegmentPoint(&subrange->interval.end);
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memPool_livenessSubrange.releaseObj(subrange);
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// #ifdef CEMU_DEBUG_ASSERT
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// // DEBUG BEGIN
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// subrange->lastIterationIndex = 0xFFFFFFFE;
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// subrange->subrangeBranchTaken = (raLivenessRange*)(uintptr_t)-1;
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// subrange->subrangeBranchNotTaken = (raLivenessRange*)(uintptr_t)-1;
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//
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// // DEBUG END
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// #endif
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}
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void PPCRecRA_deleteSubrangeCluster(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange* subrange)
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{
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auto clusterRanges = subrange->GetAllSubrangesInCluster();
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for (auto& subrange : clusterRanges)
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{
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_PPCRecRA_deleteSubrangeNoUnlink(ppcImlGenContext, subrange);
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}
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}
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void IMLRA_DeleteAllRanges(ppcImlGenContext_t* ppcImlGenContext)
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{
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for(auto& seg : ppcImlGenContext->segmentList2)
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{
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raLivenessRange* cur;
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while(cur = seg->raInfo.linkedList_allSubranges)
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{
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_PPCRecRA_deleteSubrangeNoUnlink(ppcImlGenContext, cur);
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}
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seg->raInfo.linkedList_allSubranges = nullptr;
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seg->raInfo.linkedList_perVirtualRegister.clear();
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}
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}
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void PPCRecRA_mergeSubranges(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange* subrange, raLivenessRange* absorbedSubrange)
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{
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#ifdef CEMU_DEBUG_ASSERT
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PPCRecRA_debugValidateSubrange(subrange);
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PPCRecRA_debugValidateSubrange(absorbedSubrange);
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if (subrange->imlSegment != absorbedSubrange->imlSegment)
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assert_dbg();
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cemu_assert_debug(subrange->interval2.end == absorbedSubrange->interval2.start);
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if (subrange->subrangeBranchTaken || subrange->subrangeBranchNotTaken)
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assert_dbg();
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if (subrange == absorbedSubrange)
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assert_dbg();
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#endif
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// update references
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subrange->subrangeBranchTaken = absorbedSubrange->subrangeBranchTaken;
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subrange->subrangeBranchNotTaken = absorbedSubrange->subrangeBranchNotTaken;
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absorbedSubrange->subrangeBranchTaken = nullptr;
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absorbedSubrange->subrangeBranchNotTaken = nullptr;
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if(subrange->subrangeBranchTaken)
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*std::find(subrange->subrangeBranchTaken->previousRanges.begin(), subrange->subrangeBranchTaken->previousRanges.end(), absorbedSubrange) = subrange;
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if(subrange->subrangeBranchNotTaken)
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*std::find(subrange->subrangeBranchNotTaken->previousRanges.begin(), subrange->subrangeBranchNotTaken->previousRanges.end(), absorbedSubrange) = subrange;
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// merge usage locations
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// at the merge point both ranges might track the same instruction, we handle this by first merging this duplicate location
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if(subrange && absorbedSubrange && !subrange->list_locations.empty() && !absorbedSubrange->list_locations.empty())
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{
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if(subrange->list_locations.back().index == absorbedSubrange->list_locations.front().index)
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{
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subrange->list_locations.back().isRead |= absorbedSubrange->list_locations.front().isRead;
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subrange->list_locations.back().isWrite |= absorbedSubrange->list_locations.front().isWrite;
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absorbedSubrange->list_locations.erase(absorbedSubrange->list_locations.begin()); // inefficient
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}
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}
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for (auto& location : absorbedSubrange->list_locations)
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{
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cemu_assert_debug(subrange->list_locations.empty() || (subrange->list_locations.back().index < location.index)); // todo - sometimes a subrange can contain the same instruction at the merge point if they are covering half of the instruction edge
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subrange->list_locations.push_back(location);
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}
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absorbedSubrange->list_locations.clear();
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// merge fixed reg locations
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#ifdef CEMU_DEBUG_ASSERT
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if(!subrange->list_fixedRegRequirements.empty() && !absorbedSubrange->list_fixedRegRequirements.empty())
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{
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cemu_assert_debug(subrange->list_fixedRegRequirements.back().pos < absorbedSubrange->list_fixedRegRequirements.front().pos);
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}
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#endif
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for (auto& fixedReg : absorbedSubrange->list_fixedRegRequirements)
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{
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subrange->list_fixedRegRequirements.push_back(fixedReg);
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}
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subrange->interval2.end = absorbedSubrange->interval2.end;
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PPCRecRA_debugValidateSubrange(subrange);
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PPCRecRA_deleteSubrange(ppcImlGenContext, absorbedSubrange);
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}
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// remove all inter-segment connections from the range cluster and split it into local ranges (also removes empty ranges)
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void PPCRecRA_explodeRange(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange* originRange)
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{
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cemu_assert_debug(originRange->interval2.ExtendsPreviousSegment() || originRange->interval2.ExtendsIntoNextSegment()); // only call this on ranges that span multiple segments
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auto clusterRanges = originRange->GetAllSubrangesInCluster();
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for (auto& subrange : clusterRanges)
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{
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if (subrange->list_locations.empty())
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continue;
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raInterval interval;
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interval.SetInterval(subrange->list_locations.front().index, true, subrange->list_locations.back().index, true);
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raLivenessRange* newSubrange = PPCRecRA_createSubrange2(ppcImlGenContext, subrange->imlSegment, subrange->GetVirtualRegister(), subrange->GetName(), interval.start, interval.end);
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// copy locations and fixed reg indices
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newSubrange->list_locations = subrange->list_locations;
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newSubrange->list_fixedRegRequirements = subrange->list_fixedRegRequirements;
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if(originRange->HasPhysicalRegister())
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{
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cemu_assert_debug(subrange->list_fixedRegRequirements.empty()); // avoid unassigning a register from a range with a fixed register requirement
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}
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}
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// remove subranges
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PPCRecRA_deleteSubrangeCluster(ppcImlGenContext, originRange);
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}
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#ifdef CEMU_DEBUG_ASSERT
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void PPCRecRA_debugValidateSubrange(raLivenessRange* range)
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{
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// validate subrange
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if (range->subrangeBranchTaken && range->subrangeBranchTaken->imlSegment != range->imlSegment->nextSegmentBranchTaken)
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assert_dbg();
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if (range->subrangeBranchNotTaken && range->subrangeBranchNotTaken->imlSegment != range->imlSegment->nextSegmentBranchNotTaken)
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assert_dbg();
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if(range->subrangeBranchTaken || range->subrangeBranchNotTaken)
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{
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cemu_assert_debug(range->interval2.end.ConnectsToNextSegment());
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}
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if(!range->previousRanges.empty())
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{
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cemu_assert_debug(range->interval2.start.ConnectsToPreviousSegment());
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}
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// validate locations
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if (!range->list_locations.empty())
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{
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cemu_assert_debug(range->list_locations.front().index >= range->interval2.start.GetInstructionIndexEx());
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cemu_assert_debug(range->list_locations.back().index <= range->interval2.end.GetInstructionIndexEx());
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}
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}
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#else
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void PPCRecRA_debugValidateSubrange(raLivenessRange* range) {}
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#endif
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// since locations are per-instruction, but intervals are per-edge, it's possible that locations track reads/writes outside of the range
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// this function will remove any outside read/write locations
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void IMLRA_FixLocations(raLivenessRange* range)
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{
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if(range->list_locations.empty())
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return;
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if(range->interval2.start.IsInstructionIndex() && range->interval2.start.GetInstructionIndex() == range->list_locations.front().index)
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{
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auto& location = range->list_locations.front();
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if(range->interval2.start.IsOnOutputEdge())
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{
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location.isRead = false;
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|
if(!location.isRead && !location.isWrite)
|
|
range->list_locations.erase(range->list_locations.begin());
|
|
}
|
|
}
|
|
if(range->list_locations.empty())
|
|
return;
|
|
if(range->interval2.end.IsInstructionIndex() && range->interval2.end.GetInstructionIndex() == range->list_locations.back().index)
|
|
{
|
|
auto& location = range->list_locations.back();
|
|
if(range->interval2.end.IsOnInputEdge())
|
|
{
|
|
location.isWrite = false;
|
|
if(!location.isRead && !location.isWrite)
|
|
range->list_locations.pop_back();
|
|
}
|
|
}
|
|
}
|
|
|
|
// trim start and end of range to match first and last read/write locations
|
|
// does not trim start/endpoints which extend into the next/previous segment
|
|
void IMLRA_TrimRangeToUse(raLivenessRange* range)
|
|
{
|
|
if(range->list_locations.empty())
|
|
{
|
|
// special case where we trim ranges extending from other segments to a single instruction edge
|
|
cemu_assert_debug(!range->interval2.start.IsInstructionIndex() || !range->interval2.end.IsInstructionIndex());
|
|
if(range->interval2.start.IsInstructionIndex())
|
|
range->interval2.start = range->interval2.end;
|
|
if(range->interval2.end.IsInstructionIndex())
|
|
range->interval2.end = range->interval2.start;
|
|
return;
|
|
}
|
|
raInterval prevInterval = range->interval2;
|
|
// trim start
|
|
if(range->interval2.start.IsInstructionIndex())
|
|
{
|
|
bool isInputEdge = range->list_locations.front().isRead;
|
|
range->interval2.start.Set(range->list_locations.front().index, isInputEdge);
|
|
}
|
|
// trim end
|
|
if(range->interval2.end.IsInstructionIndex())
|
|
{
|
|
bool isOutputEdge = range->list_locations.back().isWrite;
|
|
range->interval2.end.Set(range->list_locations.back().index, !isOutputEdge);
|
|
}
|
|
// extra checks
|
|
#ifdef CEMU_DEBUG_ASSERT
|
|
cemu_assert_debug(range->interval2.start <= range->interval2.end);
|
|
for(auto& loc : range->list_locations)
|
|
{
|
|
cemu_assert_debug(range->interval2.ContainsInstructionIndex(loc.index));
|
|
}
|
|
cemu_assert_debug(prevInterval.ContainsWholeInterval(range->interval2));
|
|
#endif
|
|
}
|
|
|
|
// split range at the given position
|
|
// After the split there will be two ranges:
|
|
// head -> subrange is shortened to end at splitIndex (exclusive)
|
|
// tail -> a new subrange that ranges from splitIndex (inclusive) to the end of the original subrange
|
|
// if head has a physical register assigned it will not carry over to tail
|
|
// The return value is the tail range
|
|
// If trimToHole is true, the end of the head subrange and the start of the tail subrange will be shrunk to fit the read/write locations within them
|
|
// the range after the split point does not inherit the physical register
|
|
// if trimToHole is true and any of the halfes is empty, it will be deleted
|
|
raLivenessRange* PPCRecRA_splitLocalSubrange2(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange*& subrange, raInstructionEdge splitPosition, bool trimToHole)
|
|
{
|
|
cemu_assert_debug(splitPosition.IsInstructionIndex());
|
|
cemu_assert_debug(!subrange->interval2.IsNextSegmentOnly() && !subrange->interval2.IsPreviousSegmentOnly());
|
|
cemu_assert_debug(subrange->interval2.ContainsEdge(splitPosition));
|
|
// determine new intervals
|
|
raInterval headInterval, tailInterval;
|
|
headInterval.SetInterval(subrange->interval2.start, splitPosition-1);
|
|
tailInterval.SetInterval(splitPosition, subrange->interval2.end);
|
|
cemu_assert_debug(headInterval.start <= headInterval.end);
|
|
cemu_assert_debug(tailInterval.start <= tailInterval.end);
|
|
// create tail
|
|
raLivenessRange* tailSubrange = PPCRecRA_createSubrange2(ppcImlGenContext, subrange->imlSegment, subrange->GetVirtualRegister(), subrange->GetName(), tailInterval.start, tailInterval.end);
|
|
tailSubrange->SetPhysicalRegister(subrange->GetPhysicalRegister());
|
|
// carry over branch targets and update reverse references
|
|
tailSubrange->subrangeBranchTaken = subrange->subrangeBranchTaken;
|
|
tailSubrange->subrangeBranchNotTaken = subrange->subrangeBranchNotTaken;
|
|
subrange->subrangeBranchTaken = nullptr;
|
|
subrange->subrangeBranchNotTaken = nullptr;
|
|
if(tailSubrange->subrangeBranchTaken)
|
|
*std::find(tailSubrange->subrangeBranchTaken->previousRanges.begin(), tailSubrange->subrangeBranchTaken->previousRanges.end(), subrange) = tailSubrange;
|
|
if(tailSubrange->subrangeBranchNotTaken)
|
|
*std::find(tailSubrange->subrangeBranchNotTaken->previousRanges.begin(), tailSubrange->subrangeBranchNotTaken->previousRanges.end(), subrange) = tailSubrange;
|
|
// we assume that list_locations is ordered by instruction index and contains no duplicate indices, so lets check that here just in case
|
|
#ifdef CEMU_DEBUG_ASSERT
|
|
if(!subrange->list_locations.empty())
|
|
{
|
|
sint32 curIdx = -1;
|
|
for(auto& location : subrange->list_locations)
|
|
{
|
|
cemu_assert_debug(curIdx < location.index);
|
|
curIdx = location.index;
|
|
}
|
|
}
|
|
#endif
|
|
// split locations
|
|
// since there are 2 edges per instruction and locations track both via a single index, locations on the split point might need to be copied into both ranges
|
|
for (auto& location : subrange->list_locations)
|
|
{
|
|
if(tailInterval.ContainsInstructionIndex(location.index))
|
|
tailSubrange->list_locations.push_back(location);
|
|
}
|
|
// remove tail locations from head
|
|
for (sint32 i = 0; i < subrange->list_locations.size(); i++)
|
|
{
|
|
raLivenessLocation_t* location = subrange->list_locations.data() + i;
|
|
if (!headInterval.ContainsInstructionIndex(location->index))
|
|
{
|
|
subrange->list_locations.resize(i);
|
|
break;
|
|
}
|
|
}
|
|
// split fixed reg requirements
|
|
for (sint32 i = 0; i < subrange->list_fixedRegRequirements.size(); i++)
|
|
{
|
|
raFixedRegRequirement* fixedReg = subrange->list_fixedRegRequirements.data() + i;
|
|
if (tailInterval.ContainsInstructionIndex(fixedReg->pos.GetInstructionIndex()))
|
|
{
|
|
tailSubrange->list_fixedRegRequirements.push_back(*fixedReg);
|
|
}
|
|
}
|
|
// remove tail fixed reg requirements from head
|
|
for (sint32 i = 0; i < subrange->list_fixedRegRequirements.size(); i++)
|
|
{
|
|
raFixedRegRequirement* fixedReg = subrange->list_fixedRegRequirements.data() + i;
|
|
if (!headInterval.ContainsInstructionIndex(fixedReg->pos.GetInstructionIndex()))
|
|
{
|
|
subrange->list_fixedRegRequirements.resize(i);
|
|
break;
|
|
}
|
|
}
|
|
// adjust intervals
|
|
subrange->interval2 = headInterval;
|
|
tailSubrange->interval2 = tailInterval;
|
|
// fix locations to only include read/write edges within the range
|
|
if(subrange)
|
|
IMLRA_FixLocations(subrange);
|
|
if(tailSubrange)
|
|
IMLRA_FixLocations(tailSubrange);
|
|
// trim to hole
|
|
if(trimToHole)
|
|
{
|
|
if(subrange->list_locations.empty() && (subrange->interval2.start.IsInstructionIndex() && subrange->interval2.end.IsInstructionIndex()))
|
|
{
|
|
PPCRecRA_deleteSubrange(ppcImlGenContext, subrange);
|
|
subrange = nullptr;
|
|
}
|
|
else
|
|
{
|
|
IMLRA_TrimRangeToUse(subrange);
|
|
}
|
|
if(tailSubrange->list_locations.empty() && (tailSubrange->interval2.start.IsInstructionIndex() && tailSubrange->interval2.end.IsInstructionIndex()))
|
|
{
|
|
PPCRecRA_deleteSubrange(ppcImlGenContext, tailSubrange);
|
|
tailSubrange = nullptr;
|
|
}
|
|
else
|
|
{
|
|
IMLRA_TrimRangeToUse(tailSubrange);
|
|
}
|
|
}
|
|
// validation
|
|
cemu_assert_debug(!subrange || subrange->interval2.start <= subrange->interval2.end);
|
|
cemu_assert_debug(!tailSubrange || tailSubrange->interval2.start <= tailSubrange->interval2.end);
|
|
cemu_assert_debug(!tailSubrange || tailSubrange->interval2.start >= splitPosition);
|
|
if (!trimToHole)
|
|
cemu_assert_debug(!tailSubrange || tailSubrange->interval2.start == splitPosition);
|
|
|
|
if(subrange)
|
|
PPCRecRA_debugValidateSubrange(subrange);
|
|
if(tailSubrange)
|
|
PPCRecRA_debugValidateSubrange(tailSubrange);
|
|
return tailSubrange;
|
|
}
|
|
|
|
void PPCRecRA_updateOrAddSubrangeLocation(raLivenessRange* subrange, sint32 index, bool isRead, bool isWrite)
|
|
{
|
|
if (subrange->list_locations.empty())
|
|
{
|
|
subrange->list_locations.emplace_back(index, isRead, isWrite);
|
|
return;
|
|
}
|
|
raLivenessLocation_t* lastLocation = subrange->list_locations.data() + (subrange->list_locations.size() - 1);
|
|
cemu_assert_debug(lastLocation->index <= index);
|
|
if (lastLocation->index == index)
|
|
{
|
|
// update
|
|
lastLocation->isRead = lastLocation->isRead || isRead;
|
|
lastLocation->isWrite = lastLocation->isWrite || isWrite;
|
|
return;
|
|
}
|
|
// add new
|
|
subrange->list_locations.emplace_back(index, isRead, isWrite);
|
|
}
|
|
|
|
sint32 PPCRecRARange_getReadWriteCost(IMLSegment* imlSegment)
|
|
{
|
|
sint32 v = imlSegment->loopDepth + 1;
|
|
v *= 5;
|
|
return v*v; // 25, 100, 225, 400
|
|
}
|
|
|
|
// calculate cost of entire range cluster
|
|
sint32 PPCRecRARange_estimateTotalCost(std::span<raLivenessRange*> ranges)
|
|
{
|
|
sint32 cost = 0;
|
|
|
|
// todo - this algorithm isn't accurate. If we have 10 parallel branches with a load each then the actual cost is still only that of one branch (plus minimal extra cost for generating more code).
|
|
|
|
// currently we calculate the cost based on the most expensive entry/exit point
|
|
|
|
sint32 mostExpensiveRead = 0;
|
|
sint32 mostExpensiveWrite = 0;
|
|
sint32 readCount = 0;
|
|
sint32 writeCount = 0;
|
|
|
|
for (auto& subrange : ranges)
|
|
{
|
|
if (!subrange->interval2.ExtendsPreviousSegment())
|
|
{
|
|
//cost += PPCRecRARange_getReadWriteCost(subrange->imlSegment);
|
|
mostExpensiveRead = std::max(mostExpensiveRead, PPCRecRARange_getReadWriteCost(subrange->imlSegment));
|
|
readCount++;
|
|
}
|
|
if (!subrange->interval2.ExtendsIntoNextSegment())
|
|
{
|
|
//cost += PPCRecRARange_getReadWriteCost(subrange->imlSegment);
|
|
mostExpensiveWrite = std::max(mostExpensiveWrite, PPCRecRARange_getReadWriteCost(subrange->imlSegment));
|
|
writeCount++;
|
|
}
|
|
}
|
|
cost = mostExpensiveRead + mostExpensiveWrite;
|
|
cost = cost + (readCount + writeCount) / 10;
|
|
return cost;
|
|
}
|
|
|
|
// calculate cost of range that it would have after calling PPCRecRA_explodeRange() on it
|
|
sint32 PPCRecRARange_estimateCostAfterRangeExplode(raLivenessRange* subrange)
|
|
{
|
|
auto ranges = subrange->GetAllSubrangesInCluster();
|
|
sint32 cost = -PPCRecRARange_estimateTotalCost(ranges);
|
|
for (auto& subrange : ranges)
|
|
{
|
|
if (subrange->list_locations.empty())
|
|
continue;
|
|
cost += PPCRecRARange_getReadWriteCost(subrange->imlSegment) * 2; // we assume a read and a store
|
|
}
|
|
return cost;
|
|
}
|
|
|
|
sint32 PPCRecRARange_estimateAdditionalCostAfterSplit(raLivenessRange* subrange, raInstructionEdge splitPosition)
|
|
{
|
|
// validation
|
|
#ifdef CEMU_DEBUG_ASSERT
|
|
if (subrange->interval2.ExtendsIntoNextSegment())
|
|
assert_dbg();
|
|
#endif
|
|
cemu_assert_debug(splitPosition.IsInstructionIndex());
|
|
|
|
sint32 cost = 0;
|
|
// find split position in location list
|
|
if (subrange->list_locations.empty())
|
|
{
|
|
assert_dbg(); // should not happen?
|
|
return 0;
|
|
}
|
|
sint32 splitInstructionIndex = splitPosition.GetInstructionIndex();
|
|
if (splitInstructionIndex <= subrange->list_locations.front().index)
|
|
return 0;
|
|
if (splitInstructionIndex > subrange->list_locations.back().index)
|
|
return 0;
|
|
|
|
// todo - determine exact cost of split subranges
|
|
|
|
cost += PPCRecRARange_getReadWriteCost(subrange->imlSegment) * 2; // currently we assume that the additional region will require a read and a store
|
|
|
|
return cost;
|
|
} |