Commit graph

775 commits

Author SHA1 Message Date
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f11cfa0dc5 PPCRec: Rework RLWIMI 2025-04-26 00:27:15 +02:00
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05e3cfe5c9 PPCRec: Code cleanup 2025-04-26 00:27:14 +02:00
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2fe2799d96 PPCRec: Clean up some outdated code 2025-04-26 00:24:43 +02:00
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8270308ccc PPCRec: Refactor read/write access tracking for liveness ranges 2025-04-26 00:24:43 +02:00
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547cf501d0 PPCRec: Update spill cost calculation 2025-04-26 00:24:43 +02:00
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8e78371005 PPCRec: Use 32bit mov for 32bit operations 2025-04-26 00:24:43 +02:00
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711b56c9f6 PPCRec: Reintroduce optimization for BDNZ loops 2025-04-26 00:24:43 +02:00
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60d3233151 PPCRec: Optimize register allocation 2025-04-26 00:24:43 +02:00
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6833b33c31 Add natvis file for boost::container::small_vector 2025-04-26 00:24:43 +02:00
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f94f99546d PPCRec: Fixes and optimizations + rework FRES/FRSQRTE 2025-04-26 00:24:43 +02:00
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89f8f9bd2a PPCRec: Implement MCRF, rework DCBZ 2025-04-26 00:24:43 +02:00
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972d0ed05d PPCRec: Clean up code and optimize 2025-04-26 00:24:43 +02:00
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25794f70fa PPCRec: Added dump option for recompiled functions + more fixes 2025-04-26 00:24:42 +02:00
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b55785a0a0 PPCRec: Support for arbitrary function calls in the IR
Used for MFTBU/MFTBL instruction
2025-04-26 00:22:37 +02:00
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4517c209d5 PPCRec: Some fixes 2025-04-26 00:22:37 +02:00
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aa946ae42d PPCRec: Add RA support for instructions with register constraints
Also make interval tracking more fine grained and differentiate between input and output edges of each instruction
2025-04-26 00:22:37 +02:00
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675c802cc1 PPCRec: Simplify RA code and clean it up a bit 2025-04-26 00:22:37 +02:00
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f55b842773 PPCRec: Dead code elimination + reintroduce pre-rework optimizations 2025-04-26 00:22:37 +02:00
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c419bfc451 Fix compile errors due to rebase 2025-04-26 00:22:37 +02:00
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1cc458c543 PPCRec: Implement MFCR and MTCRF 2025-04-26 00:22:37 +02:00
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9dd4f9b9a3 PPCRec: FPRs now use the shared register allocator 2025-04-26 00:22:37 +02:00
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c786ba0ebb PPCRec: Further work on support for typed registers in RA
Additionally there is no more range limit for virtual RegIDs, making the entire uint16 space available in theory
2025-04-26 00:22:37 +02:00
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c891abcb74 PPCRec: Partial support for typed registers in RA 2025-04-26 00:22:37 +02:00
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e9c161c508 PPCRec: Initial support for typed registers 2025-04-26 00:22:37 +02:00
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4c948d4a51 PPCRec: Fix capitalization in include 2025-04-26 00:22:37 +02:00
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86b82be8ef PPCRec: Use agnostic breakpoints 2025-04-26 00:22:36 +02:00
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acfc27f9fc PPCRec: Use IMLReg type in FPR RA 2025-04-26 00:22:36 +02:00
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948e33f9bf PPCRec: Unify code + misc RA preparation
Whoopsie
2025-04-26 00:22:36 +02:00
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1f6f74d6ac PPCRec: Simplify PPC and IML logic instructions
Also implement PPC NAND instruction
2025-04-26 00:22:36 +02:00
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429413d88e PPCRec: Use IMLReg in more places, unify and simplify var names 2025-04-26 00:22:36 +02:00
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dd805cb483 PPCRec: Refactor load/store instructions 2025-04-26 00:22:36 +02:00
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81fd7c8d1f PPCRec: Refactoring and clean up 2025-04-26 00:22:36 +02:00
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ce9a48b987 PPCRec: Rework CR bit handling
CR bits are now resident in registers instead of being baked into the instruction definitions. Same for XER SO, and LWARX reservation EA and value.

Reworked LWARX/STWCX, CRxx ops, compare and branch instructions. As well as RC bit handling. Not all CR-related instructions are reimplemented yet.

Introduced atomic_cmp_store operation to allow implementing STWCX in architecture agnostic IML

Removed legacy CR-based compare and jump operations
2025-04-26 00:22:36 +02:00
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db1f9c162f PPCRec: Avoid complex optimizations in backend
It's better to do it in a lowering pass so that the backend code can be kept as simple as possible
2025-04-26 00:22:36 +02:00
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f305a2ba17 PPCRec: Rework carry bit and generalize carry IML instructions
Carry bit is now resident in a register-allocated GPR instead of being backed directly into IML instructions

All the PowerPC carry ADD* and SUB* instructions as well as SRAW/SRAWI have been reworked to use more generalized IML instructions for handling carry

IML instructions now support two named output registers instead of only one (easily extendable to arbitrary count)
2025-04-26 00:22:36 +02:00
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84909d109f PPCRec: Further unify CR code 2025-04-26 00:22:36 +02:00
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c5ef9a5a98 PPCRec: Streamline instructions + unify code for CR updates 2025-04-26 00:22:36 +02:00
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a51a8bb7d5 PPCRec: New compare and cond jump instrs, update RA
Storing the condition result in a register instead of imitating PPC CR lets us simplify the backend a lot. Only implemented as PoC for BDZ/BDNZ so far.
2025-04-26 00:22:36 +02:00
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d0590ef1f5 PPCRec: New x86-64 code emitter 2025-04-26 00:22:36 +02:00
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53436f1c79 PPCRec: Rename register constants to avoid name collision 2025-04-26 00:22:36 +02:00
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d420622da7 PPCRec: Make register pool for RA configurable 2025-04-26 00:22:35 +02:00
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c4fb7b74f8 PPCRec: Make LSWI/STWSI more generic + GPR temporaries storage 2025-04-26 00:22:35 +02:00
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d724dded8e PPCRec: Clean up unused flags 2025-04-26 00:22:35 +02:00
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0f1d7532a1 PPCRec: Remove now unused PPC_ENTER and jumpMarkAddress 2025-04-26 00:22:35 +02:00
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6cdcef880b PPCRec: Fix single segment loop not being detected
Also removed associatedPPCAddress field from IMLInstruction as it's no longer used
2025-04-26 00:22:35 +02:00
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bb6b18d78f PPCRec: Unify BCCTR and BCLR code
Instead of having fixed macros for BCCTR/BCCTRL/BCLR/BCLRL we now have only one single macro instruction that takes the jump destination as a register parameter.
This also allows us to reuse an already loaded LR register (by something like MTLR) instead of loading it again from memory.

As a necessary requirement for this: The register allocator now has support for read operations in suffix instructions
2025-04-26 00:22:35 +02:00
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f2a07ade4c PPCRec: Fix merge conflicts 2025-04-26 00:22:35 +02:00
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e1e710e3f5 PPCRec: Reworked IML builder to work with basic-blocks
Intermediate commit while I'm still fixing things but I didn't want to pile on too many changes in a single commit.
New:
Reworked PPC->IML converter to first create a graph of basic blocks and then turn those into IML segment(s). This was mainly done to decouple IML design from having PPC specific knowledge like branch target addresses. The previous design also didn't allow to preserve cycle counting properly in all cases since it was based on IML instruction counting.
The new solution supports functions with non-continuous body. A pretty common example for this is when functions end with a trailing B instruction to some other place.

Current limitations:
- BL inlining not implemented
- MFTB not implemented
- BCCTR and BCLR are only partially implemented

Undo vcpkg change
2025-04-26 00:22:35 +02:00
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0622631868 PPCRec: Move X64 files into subdirectory and rename 2025-04-26 00:22:35 +02:00
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da08eda506 PPCRec: Emit x86 movd for non-AVX + more restructuring 2025-04-26 00:22:35 +02:00