mirror of
https://github.com/RPCS3/rpcs3.git
synced 2025-07-12 01:38:37 +12:00
8f91917e8c
Remove SPU thread reference from spu_recompiler_base Disable support for far jumps in pathpoints (they were rare and unsafe)
2807 lines
69 KiB
C++
2807 lines
69 KiB
C++
#include "stdafx.h"
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#include "Emu/System.h"
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#include "Emu/IdManager.h"
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#include "Emu/Memory/Memory.h"
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#include "Crypto/sha1.h"
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#include "SPUThread.h"
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#include "SPUAnalyser.h"
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#include "SPUInterpreter.h"
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#include "SPUDisAsm.h"
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#include "SPURecompiler.h"
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#include <algorithm>
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#include <mutex>
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#include <thread>
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extern u64 get_system_time();
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const spu_decoder<spu_itype> s_spu_itype;
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spu_recompiler_base::spu_recompiler_base()
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{
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}
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spu_recompiler_base::~spu_recompiler_base()
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{
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}
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void spu_recompiler_base::dispatch(SPUThread& spu, void*, u8* rip)
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{
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// If code verification failed from a patched patchpoint, clear it with a single NOP
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if (rip)
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{
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#ifdef _MSC_VER
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*(volatile u64*)(rip) = 0x841f0f;
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#else
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__atomic_store_n(reinterpret_cast<u64*>(rip), 0x841f0f, __ATOMIC_RELAXED);
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#endif
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}
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const auto func = spu.jit->get(spu.pc);
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// First attempt (load new trampoline and retry)
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if (func != spu.jit_dispatcher[spu.pc / 4])
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{
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spu.jit_dispatcher[spu.pc / 4] = func;
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return;
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}
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// Second attempt (recover from the recursion after repeated unsuccessful trampoline call)
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if (spu.block_counter != spu.block_recover && func != &dispatch)
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{
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spu.block_recover = spu.block_counter;
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return;
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}
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// Compile
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verify(HERE), spu.jit->compile(block(spu, spu.pc, &spu.jit->m_block_info));
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spu.jit_dispatcher[spu.pc / 4] = spu.jit->get(spu.pc);
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}
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void spu_recompiler_base::branch(SPUThread& spu, void*, u8* rip)
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{
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// Compile
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const auto func = verify(HERE, spu.jit->compile(block(spu, spu.pc, &spu.jit->m_block_info)));
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spu.jit_dispatcher[spu.pc / 4] = spu.jit->get(spu.pc);
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// Overwrite jump to this function with jump to the compiled function
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const s64 rel = reinterpret_cast<u64>(func) - reinterpret_cast<u64>(rip) - 5;
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alignas(8) u8 bytes[8];
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if (rel >= INT32_MIN && rel <= INT32_MAX)
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{
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const s64 rel8 = (rel + 5) - 2;
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if (rel8 >= INT8_MIN && rel8 <= INT8_MAX)
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{
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bytes[0] = 0xeb; // jmp rel8
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bytes[1] = static_cast<s8>(rel8);
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std::memset(bytes + 2, 0x90, 6);
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}
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else
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{
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bytes[0] = 0xe9; // jmp rel32
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std::memcpy(bytes + 1, &rel, 4);
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std::memset(bytes + 5, 0x90, 3);
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}
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}
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else
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{
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// Far jumps: extremely rare and disabled due to implementation complexity
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bytes[0] = 0x0f; // nop (8-byte form)
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bytes[1] = 0x1f;
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bytes[2] = 0x84;
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std::memset(bytes + 3, 0x00, 5);
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}
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#ifdef _MSC_VER
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*(volatile u64*)(rip) = *reinterpret_cast<u64*>(+bytes);
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#else
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__atomic_store_n(reinterpret_cast<u64*>(rip), *reinterpret_cast<u64*>(+bytes), __ATOMIC_RELAXED);
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#endif
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}
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std::vector<u32> spu_recompiler_base::block(SPUThread& spu, u32 lsa, std::bitset<0x10000>* out_info)
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{
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// Block info (local)
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std::bitset<0x10000> block_info{};
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// Select one to use
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std::bitset<0x10000>& blocks = out_info ? *out_info : block_info;
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if (out_info)
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{
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out_info->reset();
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}
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// Result: addr + raw instruction data
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std::vector<u32> result;
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result.reserve(256);
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result.push_back(lsa);
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blocks.set(lsa / 4);
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// Simple block entry workload list
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std::vector<u32> wl;
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wl.push_back(lsa);
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// Value flags (TODO)
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enum class vf : u32
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{
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is_const,
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is_mask,
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__bitset_enum_max
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};
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// Weak constant propagation context (for guessing branch targets)
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std::array<bs_t<vf>, 128> vflags{};
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// Associated constant values for 32-bit preferred slot
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std::array<u32, 128> values;
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if (spu.pc == lsa && g_cfg.core.spu_block_size == spu_block_size_type::giga)
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{
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// TODO: use current register values for speculations
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vflags[0] = +vf::is_const;
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values[0] = spu.gpr[0]._u32[3];
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}
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for (u32 wi = 0; wi < wl.size();)
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{
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const auto next_block = [&]
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{
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// Reset value information
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vflags.fill({});
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wi++;
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};
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const auto add_block = [&](u32 target)
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{
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// Verify validity of the new target (TODO)
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if (target > lsa)
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{
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// Check for redundancy
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if (!blocks[target / 4])
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{
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blocks[target / 4] = true;
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wl.push_back(target);
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return;
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}
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}
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};
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const u32 pos = wl[wi];
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const u32 data = spu._ref<u32>(pos);
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const auto op = spu_opcode_t{data};
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wl[wi] += 4;
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// Analyse instruction
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switch (const auto type = s_spu_itype.decode(data))
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{
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case spu_itype::UNK:
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case spu_itype::DFCEQ:
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case spu_itype::DFCMEQ:
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case spu_itype::DFCGT:
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//case spu_itype::DFCMGT:
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case spu_itype::DFTSV:
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{
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// Stop before invalid instructions (TODO)
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blocks[pos / 4] = true;
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next_block();
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continue;
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}
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case spu_itype::SYNC:
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case spu_itype::DSYNC:
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case spu_itype::STOP:
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case spu_itype::STOPD:
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{
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if (data == 0 || data == 0x80)
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{
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// Stop before null data
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blocks[pos / 4] = true;
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next_block();
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continue;
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}
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if (g_cfg.core.spu_block_size != spu_block_size_type::giga)
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{
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// Stop on special instructions (TODO)
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next_block();
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break;
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}
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break;
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}
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case spu_itype::IRET:
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{
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next_block();
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break;
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}
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case spu_itype::BI:
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case spu_itype::BISL:
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case spu_itype::BIZ:
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case spu_itype::BINZ:
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case spu_itype::BIHZ:
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case spu_itype::BIHNZ:
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{
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const auto af = vflags[op.ra];
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const auto av = values[op.ra];
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if (type == spu_itype::BISL)
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{
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vflags[op.rt] = +vf::is_const;
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values[op.rt] = pos + 4;
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}
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if (test(af, vf::is_const))
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{
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const u32 target = spu_branch_target(av);
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if (target == pos + 4)
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{
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// Nop (unless BISL)
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break;
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}
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if (type != spu_itype::BISL || g_cfg.core.spu_block_size == spu_block_size_type::giga)
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{
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LOG_WARNING(SPU, "[0x%x] At 0x%x: indirect branch to 0x%x", lsa, pos, target);
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add_block(target);
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}
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if (type == spu_itype::BISL && target < lsa)
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{
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next_block();
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break;
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}
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}
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else if (type == spu_itype::BI && !op.d && !op.e)
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{
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// Analyse jump table (TODO)
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std::basic_string<u32> jt_abs;
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std::basic_string<u32> jt_rel;
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const u32 start = pos + 4;
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const u32 limit = 0x40000;
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for (u32 i = start; i < limit; i += 4)
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{
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const u32 target = spu._ref<u32>(i);
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if (target % 4)
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{
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// Address cannot be misaligned: abort
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break;
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}
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if (target >= lsa && target < limit)
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{
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// Possible jump table entry (absolute)
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jt_abs.push_back(target);
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}
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if (target + start >= lsa && target + start < limit)
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{
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// Possible jump table entry (relative)
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jt_rel.push_back(target + start);
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}
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if (std::max(jt_abs.size(), jt_rel.size()) * 4 + start <= i)
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{
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// Neither type of jump table completes
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break;
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}
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}
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// Add detected jump table blocks (TODO: avoid adding both)
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if (jt_abs.size() >= 3 || jt_rel.size() >= 3)
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{
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if (jt_abs.size() >= jt_rel.size())
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{
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for (u32 target : jt_abs)
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{
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add_block(target);
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}
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}
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if (jt_rel.size() >= jt_abs.size())
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{
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for (u32 target : jt_rel)
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{
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add_block(target);
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}
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}
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}
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}
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if (type == spu_itype::BI || type == spu_itype::BISL || g_cfg.core.spu_block_size == spu_block_size_type::safe)
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{
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if (type == spu_itype::BI || g_cfg.core.spu_block_size != spu_block_size_type::giga)
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{
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next_block();
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break;
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}
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}
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break;
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}
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case spu_itype::BRSL:
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case spu_itype::BRASL:
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{
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const u32 target = spu_branch_target(type == spu_itype::BRASL ? 0 : pos, op.i16);
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vflags[op.rt] = +vf::is_const;
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values[op.rt] = pos + 4;
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if (target == pos + 4)
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{
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// Get next instruction address idiom
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break;
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}
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if (target < lsa || g_cfg.core.spu_block_size != spu_block_size_type::giga)
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{
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// Stop on direct calls
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next_block();
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break;
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}
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if (g_cfg.core.spu_block_size == spu_block_size_type::giga)
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{
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add_block(target);
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}
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break;
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}
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case spu_itype::BR:
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case spu_itype::BRA:
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case spu_itype::BRZ:
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case spu_itype::BRNZ:
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case spu_itype::BRHZ:
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case spu_itype::BRHNZ:
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{
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const u32 target = spu_branch_target(type == spu_itype::BRA ? 0 : pos, op.i16);
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if (target == pos + 4)
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{
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// Nop
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break;
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}
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add_block(target);
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if (type == spu_itype::BR || type == spu_itype::BRA)
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{
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// Stop on direct branches
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next_block();
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break;
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}
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break;
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}
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case spu_itype::HEQ:
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case spu_itype::HEQI:
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case spu_itype::HGT:
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case spu_itype::HGTI:
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case spu_itype::HLGT:
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case spu_itype::HLGTI:
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case spu_itype::HBR:
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case spu_itype::HBRA:
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case spu_itype::HBRR:
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case spu_itype::LNOP:
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case spu_itype::NOP:
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case spu_itype::MTSPR:
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case spu_itype::WRCH:
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case spu_itype::FSCRWR:
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case spu_itype::STQA:
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case spu_itype::STQD:
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case spu_itype::STQR:
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case spu_itype::STQX:
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{
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// Do nothing
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break;
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}
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case spu_itype::IL:
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{
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vflags[op.rt] = +vf::is_const;
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values[op.rt] = op.si16;
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break;
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}
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case spu_itype::ILA:
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{
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vflags[op.rt] = +vf::is_const;
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values[op.rt] = op.i18;
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break;
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}
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case spu_itype::ILH:
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{
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vflags[op.rt] = +vf::is_const;
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values[op.rt] = op.i16 << 16 | op.i16;
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break;
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}
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case spu_itype::ILHU:
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{
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vflags[op.rt] = +vf::is_const;
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values[op.rt] = op.i16 << 16;
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break;
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}
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case spu_itype::IOHL:
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{
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values[op.rt] = values[op.rt] | op.i16;
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break;
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}
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case spu_itype::ORI:
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{
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vflags[op.rt] = vflags[op.ra] & vf::is_const;
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values[op.rt] = values[op.ra] | op.si10;
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break;
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}
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case spu_itype::OR:
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{
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vflags[op.rt] = vflags[op.ra] & vflags[op.rb] & vf::is_const;
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values[op.rt] = values[op.ra] | values[op.rb];
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break;
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}
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case spu_itype::AI:
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{
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vflags[op.rt] = vflags[op.ra] & vf::is_const;
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values[op.rt] = values[op.ra] + op.si10;
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break;
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}
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case spu_itype::A:
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{
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vflags[op.rt] = vflags[op.ra] & vflags[op.rb] & vf::is_const;
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values[op.rt] = values[op.ra] + values[op.rb];
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break;
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}
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default:
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{
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// Unconst
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vflags[type & spu_itype::_quadrop ? +op.rt4 : +op.rt] = {};
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break;
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}
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}
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// Insert raw instruction value
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if (result.size() - 1 <= (pos - lsa) / 4)
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{
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if (result.size() - 1 < (pos - lsa) / 4)
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{
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result.resize((pos - lsa) / 4 + 1);
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}
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result.emplace_back(se_storage<u32>::swap(data));
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}
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else if (u32& raw_val = result[(pos - lsa) / 4 + 1])
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{
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verify(HERE), raw_val == se_storage<u32>::swap(data);
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}
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else
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{
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raw_val = se_storage<u32>::swap(data);
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}
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}
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if (g_cfg.core.spu_block_size == spu_block_size_type::safe)
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{
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// Check holes in safe mode (TODO)
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u32 valid_size = 0;
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for (u32 i = 1; i < result.size(); i++)
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{
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if (result[i] == 0)
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{
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const u32 pos = lsa + (i - 1) * 4;
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const u32 data = spu._ref<u32>(pos);
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const auto type = s_spu_itype.decode(data);
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// Allow only NOP or LNOP instructions in holes
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if (type == spu_itype::NOP || type == spu_itype::LNOP)
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{
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if (i + 1 < result.size())
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{
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continue;
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}
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}
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result.resize(valid_size + 1);
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break;
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}
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else
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{
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valid_size = i;
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}
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}
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}
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if (result.size() == 1)
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{
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// Blocks starting from 0x0 or invalid instruction won't be compiled, may need special interpreter fallback
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result.clear();
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}
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return result;
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}
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#include "Emu/CPU/CPUTranslator.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/IR/Verifier.h"
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#include "llvm/Analysis/Lint.h"
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#include "llvm/Transforms/Utils/BasicBlockUtils.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/Transforms/IPO.h"
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#include "llvm/Transforms/Vectorize.h"
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#include "Utilities/JIT.h"
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class spu_llvm_runtime
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{
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shared_mutex m_mutex;
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// All functions
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std::map<std::vector<u32>, spu_function_t> m_map;
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// All dispatchers
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std::array<atomic_t<spu_function_t>, 0x10000> m_dispatcher;
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// JIT instance (TODO: use small code model)
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jit_compiler m_jit{{}, jit_compiler::cpu(g_cfg.core.llvm_cpu), true};
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friend class spu_llvm_recompiler;
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public:
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spu_llvm_runtime()
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{
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LOG_SUCCESS(SPU, "SPU Recompiler Runtime (LLVM) initialized...");
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// Initialize lookup table
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for (auto& v : m_dispatcher)
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{
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v.raw() = &spu_recompiler_base::dispatch;
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}
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// Initialize "empty" block
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m_map[std::vector<u32>()] = &spu_recompiler_base::dispatch;
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}
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};
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class spu_llvm_recompiler : public spu_recompiler_base, public cpu_translator
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{
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std::shared_ptr<spu_llvm_runtime> m_spurt;
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llvm::Function* m_function;
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using m_module = void;
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llvm::Value* m_thread;
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llvm::Value* m_lsptr;
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llvm::BasicBlock* m_stop;
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llvm::GlobalVariable* m_jt;
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std::array<std::pair<llvm::Value*, llvm::Value*>, 128> m_gpr;
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std::array<llvm::Instruction*, 128> m_flush_gpr;
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std::map<u32, llvm::BasicBlock*> m_instr_map;
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template <typename T>
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llvm::Value* _ptr(llvm::Value* base, u32 offset, std::string name = "")
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{
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const auto off = m_ir->CreateAdd(base, m_ir->getInt64(offset));
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const auto ptr = m_ir->CreateIntToPtr(off, get_type<T>()->getPointerTo(), name);
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return ptr;
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}
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template <typename T, typename... Args>
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llvm::Value* spu_ptr(Args... offset_args)
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{
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return _ptr<T>(m_thread, ::offset32(offset_args...));
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}
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template <typename T = u32[4]>
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auto& init_vr(u32 index)
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{
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auto& gpr = m_gpr.at(index);
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if (!gpr.first)
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{
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// Save and restore current insert point if necessary
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const auto block_cur = m_ir->GetInsertBlock();
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// Emit register pointer at the beginning of function
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m_ir->SetInsertPoint(&*m_function->begin()->getFirstInsertionPt());
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gpr.first = _ptr<T>(m_thread, ::offset32(&SPUThread::gpr, index), fmt::format("Reg$%u", index));
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m_ir->SetInsertPoint(block_cur);
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}
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return gpr;
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}
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template <typename T = u32[4]>
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value_t<T> get_vr(u32 index)
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{
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auto& gpr = init_vr<T>(index);
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if (!gpr.second)
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{
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gpr.second = m_ir->CreateLoad(gpr.first, fmt::format("Load$%u", index));
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}
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value_t<T> r;
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r.value = m_ir->CreateBitCast(gpr.second, get_type<T>());
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return r;
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}
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template <typename T>
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void set_vr(u32 index, T expr)
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{
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auto& gpr = init_vr<typename T::type>(index);
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gpr.second = expr.eval(m_ir);
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// Remember last insertion point for flush
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if (m_ir->GetInsertBlock()->empty())
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{
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// Insert dummy instruction if empty
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m_flush_gpr.at(index) = llvm::cast<llvm::Instruction>(m_ir->CreateAdd(m_thread, m_ir->getInt64(8)));
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}
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else
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{
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m_flush_gpr.at(index) = m_ir->GetInsertBlock()->end()->getPrevNode();
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}
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}
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void flush(std::pair<llvm::Value*, llvm::Value*>& reg, llvm::Instruction*& flush_reg)
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{
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if (reg.first && reg.second && flush_reg)
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{
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// Save and restore current insert point if necessary
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const auto block_cur = m_ir->GetInsertBlock();
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// Try to emit store immediately after its last use
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if (const auto next = flush_reg->getNextNode())
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{
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m_ir->SetInsertPoint(next);
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}
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m_ir->CreateStore(m_ir->CreateBitCast(reg.second, reg.first->getType()->getPointerElementType()), reg.first);
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m_ir->SetInsertPoint(block_cur);
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}
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// Unregister store
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flush_reg = nullptr;
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// Invalidate current value (TODO)
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reg.second = nullptr;
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}
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void flush()
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{
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for (u32 i = 0; i < 128; i++)
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{
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flush(m_gpr[i], m_flush_gpr[i]);
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}
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}
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void update_pc()
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{
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m_ir->CreateStore(m_ir->getInt32(m_pos), spu_ptr<u32>(&SPUThread::pc));
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}
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// Perform external call
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template <typename RT, typename... FArgs, typename... Args>
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llvm::CallInst* call(RT(*_func)(FArgs...), Args... args)
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{
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static_assert(sizeof...(FArgs) == sizeof...(Args), "spu_llvm_recompiler::call(): unexpected arg number");
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const auto iptr = reinterpret_cast<std::uintptr_t>(_func);
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const auto type = llvm::FunctionType::get(get_type<RT>(), {args->getType()...}, false)->getPointerTo();
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return m_ir->CreateCall(m_ir->CreateIntToPtr(m_ir->getInt64(iptr), type), {args...});
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}
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// Perform external call and return
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template <typename RT, typename... FArgs, typename... Args>
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void tail(RT(*_func)(FArgs...), Args... args)
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{
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const auto inst = call(_func, args...);
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inst->setTailCall();
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if (inst->getType() == get_type<void>())
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{
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m_ir->CreateRetVoid();
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}
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else
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{
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m_ir->CreateRet(inst);
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}
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}
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void tail(llvm::Value* func_ptr)
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{
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m_ir->CreateCall(func_ptr, {m_thread, m_lsptr, m_ir->getInt32(0)})->setTailCall();
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m_ir->CreateRetVoid();
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}
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template <typename T1, typename T2>
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value_t<u8[16]> pshufb(T1 a, T2 b)
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{
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value_t<u8[16]> result;
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result.value = m_ir->CreateCall(get_intrinsic(llvm::Intrinsic::x86_ssse3_pshuf_b_128), {a.eval(m_ir), b.eval(m_ir)});
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return result;
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}
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public:
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spu_llvm_recompiler()
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: spu_recompiler_base()
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, cpu_translator(nullptr, false)
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{
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if (g_cfg.core.spu_shared_runtime)
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{
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// TODO (local context is unsupported)
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//m_spurt = std::make_shared<spu_llvm_runtime>();
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}
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}
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virtual spu_function_t get(u32 lsa) override
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{
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// Initialize if necessary
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if (!m_spurt)
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{
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m_spurt = fxm::get_always<spu_llvm_runtime>();
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m_context = m_spurt->m_jit.get_context();
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}
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// Simple atomic read
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return m_spurt->m_dispatcher[lsa / 4];
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}
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virtual spu_function_t compile(const std::vector<u32>& func) override
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{
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// Initialize if necessary
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if (!m_spurt)
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{
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m_spurt = fxm::get_always<spu_llvm_runtime>();
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m_context = m_spurt->m_jit.get_context();
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}
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// Don't lock without shared runtime
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std::unique_lock<shared_mutex> lock(m_spurt->m_mutex, std::defer_lock);
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if (g_cfg.core.spu_shared_runtime)
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{
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lock.lock();
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}
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// Try to find existing function, register new
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auto& fn_location = m_spurt->m_map[func];
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if (fn_location)
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{
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return fn_location;
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}
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std::string hash;
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{
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sha1_context ctx;
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u8 output[20];
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sha1_starts(&ctx);
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sha1_update(&ctx, reinterpret_cast<const u8*>(func.data() + 1), func.size() * 4 - 4);
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sha1_finish(&ctx, output);
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fmt::append(hash, "spu-0x%05x-%s", func[0], fmt::base57(output));
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}
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LOG_NOTICE(SPU, "Building function 0x%x... (size %u, %s)", func[0], func.size() - 1, hash);
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using namespace llvm;
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SPUDisAsm dis_asm(CPUDisAsm_InterpreterMode);
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dis_asm.offset = reinterpret_cast<const u8*>(func.data() + 1) - func[0];
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std::string log;
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if (g_cfg.core.spu_debug)
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{
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fmt::append(log, "========== SPU BLOCK 0x%05x (size %u, %s) ==========\n\n", func[0], func.size() - 1, hash);
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}
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// Create LLVM module
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std::unique_ptr<Module> module = std::make_unique<Module>(hash, m_context);
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// Initialize target
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module->setTargetTriple(Triple::normalize(sys::getProcessTriple()));
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// Initialize pass manager
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legacy::FunctionPassManager pm(module.get());
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// Basic optimizations
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pm.add(createEarlyCSEPass());
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pm.add(createDeadStoreEliminationPass());
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pm.add(createLintPass()); // Check
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// Add function
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const auto main_func = cast<Function>(module->getOrInsertFunction(hash, get_type<void>(), get_type<u64>(), get_type<u64>()));
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m_function = main_func;
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m_thread = &*m_function->arg_begin();
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m_lsptr = &*(m_function->arg_begin() + 1);
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// Initialize IR Builder
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IRBuilder<> irb(BasicBlock::Create(m_context, "", m_function));
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m_ir = &irb;
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// Start compilation
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m_pos = func[0];
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m_size = (func.size() - 1) * 4;
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const u32 start = m_pos;
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const u32 end = m_pos + m_size;
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m_stop = BasicBlock::Create(m_context, "", m_function);
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const auto jtt = ArrayType::get(GetType<u8*>(), m_size / 4);
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std::vector<llvm::Constant*> jt;
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jt.reserve(m_size / 4);
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// Create instruction blocks
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for (u32 i = 1, pos = start; i < func.size(); i++, pos += 4)
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{
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if (func[i] && m_block_info[pos / 4])
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{
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const auto b = BasicBlock::Create(m_context, "", m_function);
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jt.push_back(llvm::BlockAddress::get(b));
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m_instr_map.emplace(pos, b);
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}
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else
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{
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jt.push_back(llvm::BlockAddress::get(m_stop));
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}
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}
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m_jt = new GlobalVariable(*module, jtt, true, GlobalValue::PrivateLinkage, llvm::ConstantArray::get(jtt, jt), "jt");
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update_pc();
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const auto label_test = BasicBlock::Create(m_context, "", m_function);
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const auto label_diff = BasicBlock::Create(m_context, "", m_function);
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const auto label_body = BasicBlock::Create(m_context, "", m_function);
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// Emit state check
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const auto pstate = spu_ptr<u32>(&SPUThread::state);
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m_ir->CreateCondBr(m_ir->CreateICmpNE(m_ir->CreateLoad(pstate), m_ir->getInt32(0)), m_stop, label_test);
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// Emit code check
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m_ir->SetInsertPoint(label_test);
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if (false)
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{
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// Disable check (not available)
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}
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else if (func.size() - 1 == 1)
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{
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const auto cond = m_ir->CreateICmpNE(m_ir->CreateLoad(_ptr<u32>(m_lsptr, m_pos)), m_ir->getInt32(func[1]));
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m_ir->CreateCondBr(cond, label_diff, label_body);
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}
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else if (func.size() - 1 == 2)
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{
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const auto cond = m_ir->CreateICmpNE(m_ir->CreateLoad(_ptr<u64>(m_lsptr, m_pos)), m_ir->getInt64(static_cast<u64>(func[2]) << 32 | func[1]));
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m_ir->CreateCondBr(cond, label_diff, label_body);
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}
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else
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{
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const u32 starta = m_pos & -32;
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const u32 enda = ::align(end, 32);
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const u32 sizea = (enda - starta) / 32;
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verify(HERE), sizea;
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llvm::Value* acc = nullptr;
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for (u32 j = starta; j < enda; j += 32)
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{
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u32 indices[8];
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bool holes = false;
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bool data = false;
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for (u32 i = 0; i < 8; i++)
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{
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const u32 k = j + i * 4;
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if (k < m_pos || k >= end || !func[(k - m_pos) / 4 + 1])
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{
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indices[i] = 8;
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holes = true;
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}
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else
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{
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indices[i] = i;
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data = true;
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}
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}
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if (!data)
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{
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// Skip aligned holes
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continue;
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}
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// Load aligned code block from LS
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llvm::Value* vls = m_ir->CreateLoad(_ptr<u32[8]>(m_lsptr, j));
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// Mask if necessary
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if (holes)
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{
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vls = m_ir->CreateShuffleVector(vls, ConstantVector::getSplat(8, m_ir->getInt32(0)), indices);
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}
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// Perform bitwise comparison and accumulate
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u32 words[8];
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for (u32 i = 0; i < 8; i++)
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{
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const u32 k = j + i * 4;
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words[i] = k >= m_pos && k < end ? func[(k - m_pos) / 4 + 1] : 0;
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}
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vls = m_ir->CreateXor(vls, ConstantDataVector::get(m_context, words));
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acc = acc ? m_ir->CreateOr(acc, vls) : vls;
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}
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// Pattern for PTEST
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acc = m_ir->CreateBitCast(acc, get_type<u64[4]>());
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llvm::Value* elem = m_ir->CreateExtractElement(acc, u64{0});
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elem = m_ir->CreateOr(elem, m_ir->CreateExtractElement(acc, 1));
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elem = m_ir->CreateOr(elem, m_ir->CreateExtractElement(acc, 2));
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elem = m_ir->CreateOr(elem, m_ir->CreateExtractElement(acc, 3));
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// Compare result with zero
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const auto cond = m_ir->CreateICmpNE(elem, m_ir->getInt64(0));
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m_ir->CreateCondBr(cond, label_diff, label_body);
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}
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// Increase block counter
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m_ir->SetInsertPoint(label_body);
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const auto pbcount = spu_ptr<u64>(&SPUThread::block_counter);
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m_ir->CreateStore(m_ir->CreateAdd(m_ir->CreateLoad(pbcount), m_ir->getInt64(1)), pbcount);
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// Emit instructions
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for (u32 i = 1; i < func.size(); i++)
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{
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const u32 pos = start + (i - 1) * 4;
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if (g_cfg.core.spu_debug)
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{
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// Disasm
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dis_asm.dump_pc = pos;
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dis_asm.disasm(pos);
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log += dis_asm.last_opcode;
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log += '\n';
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}
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// Get opcode
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const u32 op = se_storage<u32>::swap(func[i]);
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if (!op)
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{
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// Ignore hole
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if (!m_ir->GetInsertBlock()->getTerminator())
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{
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flush();
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branch_fixed(spu_branch_target(pos));
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LOG_ERROR(SPU, "Unexpected fallthrough to 0x%x", pos);
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}
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continue;
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}
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// Bind instruction label if necessary (TODO)
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const auto found = m_instr_map.find(pos);
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if (found != m_instr_map.end())
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{
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if (!m_ir->GetInsertBlock()->getTerminator())
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{
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flush();
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m_ir->CreateBr(found->second);
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}
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m_ir->SetInsertPoint(found->second);
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}
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if (!m_ir->GetInsertBlock()->getTerminator())
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{
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// Update position
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m_pos = pos;
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// Execute recompiler function (TODO)
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(this->*g_decoder.decode(op))({op});
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}
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}
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// Make fallthrough if necessary
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if (!m_ir->GetInsertBlock()->getTerminator())
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{
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flush();
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branch_fixed(spu_branch_target(end));
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}
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//
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m_ir->SetInsertPoint(m_stop);
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m_ir->CreateRetVoid();
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m_ir->SetInsertPoint(label_diff);
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const auto pbfail = spu_ptr<u64>(&SPUThread::block_failure);
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m_ir->CreateStore(m_ir->CreateAdd(m_ir->CreateLoad(pbfail), m_ir->getInt64(1)), pbfail);
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tail(&spu_recompiler_base::dispatch, m_thread, m_ir->getInt32(0), m_ir->getInt32(0));
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// Clear context
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m_gpr.fill({});
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m_flush_gpr.fill(0);
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m_instr_map.clear();
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// Generate a dispatcher (übertrampoline)
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std::vector<u32> addrv{start};
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const auto beg = m_spurt->m_map.lower_bound(addrv);
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addrv[0] += 4;
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const auto _end = m_spurt->m_map.lower_bound(addrv);
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const u32 size0 = std::distance(beg, _end);
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if (size0 > 1)
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{
|
|
const auto trampoline = cast<Function>(module->getOrInsertFunction(fmt::format("tr_0x%05x_%03u", start, size0), get_type<void>(), get_type<u64>(), get_type<u64>()));
|
|
m_function = trampoline;
|
|
m_thread = &*m_function->arg_begin();
|
|
m_lsptr = &*(m_function->arg_begin() + 1);
|
|
|
|
struct work
|
|
{
|
|
u32 size;
|
|
u32 level;
|
|
BasicBlock* label;
|
|
std::map<std::vector<u32>, spu_function_t>::iterator beg;
|
|
std::map<std::vector<u32>, spu_function_t>::iterator end;
|
|
};
|
|
|
|
std::vector<work> workload;
|
|
workload.reserve(size0);
|
|
workload.emplace_back();
|
|
workload.back().size = size0;
|
|
workload.back().level = 1;
|
|
workload.back().beg = beg;
|
|
workload.back().end = _end;
|
|
workload.back().label = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
|
|
for (std::size_t i = 0; i < workload.size(); i++)
|
|
{
|
|
// Get copy of the workload info
|
|
work w = workload[i];
|
|
|
|
// Switch targets
|
|
std::vector<std::pair<u32, llvm::BasicBlock*>> targets;
|
|
|
|
llvm::BasicBlock* def{};
|
|
|
|
while (true)
|
|
{
|
|
const u32 x1 = w.beg->first.at(w.level);
|
|
auto it = w.beg;
|
|
auto it2 = it;
|
|
u32 x = x1;
|
|
bool split = false;
|
|
|
|
while (it2 != w.end)
|
|
{
|
|
it2++;
|
|
|
|
const u32 x2 = it2 != w.end ? it2->first.at(w.level) : x1;
|
|
|
|
if (x2 != x)
|
|
{
|
|
const u32 dist = std::distance(it, it2);
|
|
|
|
const auto b = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
|
|
if (dist == 1 && x != 0)
|
|
{
|
|
m_ir->SetInsertPoint(b);
|
|
|
|
if (const u64 fval = reinterpret_cast<u64>(it->second))
|
|
{
|
|
const auto ptr = m_ir->CreateIntToPtr(m_ir->getInt64(fval), main_func->getType());
|
|
m_ir->CreateCall(ptr, {m_thread, m_lsptr})->setTailCall();
|
|
}
|
|
else
|
|
{
|
|
verify(HERE, &it->second == &fn_location);
|
|
m_ir->CreateCall(main_func, {m_thread, m_lsptr})->setTailCall();
|
|
}
|
|
|
|
m_ir->CreateRetVoid();
|
|
}
|
|
else
|
|
{
|
|
workload.emplace_back(w);
|
|
workload.back().beg = it;
|
|
workload.back().end = it2;
|
|
workload.back().label = b;
|
|
workload.back().size = dist;
|
|
}
|
|
|
|
if (x == 0)
|
|
{
|
|
def = b;
|
|
}
|
|
else
|
|
{
|
|
targets.emplace_back(std::make_pair(x, b));
|
|
}
|
|
|
|
x = x2;
|
|
it = it2;
|
|
split = true;
|
|
}
|
|
}
|
|
|
|
if (!split)
|
|
{
|
|
// Cannot split: words are identical within the range at this level
|
|
w.level++;
|
|
}
|
|
else
|
|
{
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!def)
|
|
{
|
|
def = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
|
|
m_ir->SetInsertPoint(def);
|
|
tail(&spu_recompiler_base::dispatch, m_thread, m_ir->getInt32(0), m_ir->getInt32(0));
|
|
}
|
|
|
|
m_ir->SetInsertPoint(w.label);
|
|
const auto add = m_ir->CreateAdd(m_lsptr, m_ir->getInt64(start + w.level * 4 - 4));
|
|
const auto ptr = m_ir->CreateIntToPtr(add, get_type<u32*>());
|
|
const auto val = m_ir->CreateLoad(ptr);
|
|
const auto sw = m_ir->CreateSwitch(val, def, ::size32(targets));
|
|
|
|
for (auto& pair : targets)
|
|
{
|
|
sw->addCase(m_ir->getInt32(pair.first), pair.second);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Run some optimizations
|
|
//pm.run(*main_func);
|
|
|
|
spu_function_t fn{}, tr{};
|
|
|
|
raw_string_ostream out(log);
|
|
|
|
if (g_cfg.core.spu_debug)
|
|
{
|
|
fmt::append(log, "LLVM IR at 0x%x:\n", start);
|
|
out << *module; // print IR
|
|
out << "\n\n";
|
|
}
|
|
|
|
if (verifyModule(*module, &out))
|
|
{
|
|
out.flush();
|
|
LOG_ERROR(SPU, "LLVM: Verification failed at 0x%x:\n%s", start, log);
|
|
fmt::raw_error("Compilation failed");
|
|
}
|
|
|
|
if (g_cfg.core.spu_debug)
|
|
{
|
|
// Testing only
|
|
m_spurt->m_jit.add(std::move(module), fmt::format("%sSPU/%s.obj", Emu.GetCachePath(), hash));
|
|
}
|
|
else
|
|
{
|
|
m_spurt->m_jit.add(std::move(module));
|
|
}
|
|
|
|
m_spurt->m_jit.fin();
|
|
fn = reinterpret_cast<spu_function_t>(m_spurt->m_jit.get_engine().getPointerToFunction(main_func));
|
|
tr = fn;
|
|
|
|
if (size0 > 1)
|
|
{
|
|
tr = reinterpret_cast<spu_function_t>(m_spurt->m_jit.get_engine().getPointerToFunction(m_function));
|
|
}
|
|
|
|
// Register function pointer
|
|
fn_location = fn;
|
|
|
|
// Trampoline
|
|
m_spurt->m_dispatcher[start / 4] = tr;
|
|
|
|
LOG_NOTICE(SPU, "[0x%x] Compiled: %p", start, fn);
|
|
|
|
if (tr != fn)
|
|
LOG_NOTICE(SPU, "[0x%x] T: %p", start, tr);
|
|
|
|
if (g_cfg.core.spu_debug)
|
|
{
|
|
out.flush();
|
|
fs::file(Emu.GetCachePath() + "SPU.log", fs::write + fs::append).write(log);
|
|
}
|
|
|
|
return fn;
|
|
}
|
|
|
|
template <spu_inter_func_t F>
|
|
static void exec_fall(SPUThread* _spu, spu_opcode_t op)
|
|
{
|
|
if (F(*_spu, op))
|
|
{
|
|
_spu->pc += 4;
|
|
}
|
|
}
|
|
|
|
template <spu_inter_func_t F>
|
|
void fall(spu_opcode_t op)
|
|
{
|
|
flush();
|
|
update_pc();
|
|
call(&exec_fall<F>, m_thread, m_ir->getInt32(op.opcode));
|
|
}
|
|
|
|
static void exec_unk(SPUThread* _spu, u32 op)
|
|
{
|
|
fmt::throw_exception("Unknown/Illegal instruction (0x%08x)" HERE, op);
|
|
}
|
|
|
|
void UNK(spu_opcode_t op_unk)
|
|
{
|
|
flush();
|
|
update_pc();
|
|
tail(&exec_unk, m_thread, m_ir->getInt32(op_unk.opcode));
|
|
}
|
|
|
|
static void exec_stop(SPUThread* _spu, u32 code)
|
|
{
|
|
if (_spu->stop_and_signal(code))
|
|
{
|
|
_spu->pc += 4;
|
|
}
|
|
}
|
|
|
|
void STOP(spu_opcode_t op) //
|
|
{
|
|
flush();
|
|
update_pc();
|
|
tail(&exec_stop, m_thread, m_ir->getInt32(op.opcode));
|
|
}
|
|
|
|
void STOPD(spu_opcode_t op) //
|
|
{
|
|
flush();
|
|
update_pc();
|
|
tail(&exec_stop, m_thread, m_ir->getInt32(0x3fff));
|
|
}
|
|
|
|
static s64 exec_rdch(SPUThread* _spu, u32 ch)
|
|
{
|
|
return _spu->get_ch_value(ch);
|
|
}
|
|
|
|
void RDCH(spu_opcode_t op) //
|
|
{
|
|
flush();
|
|
update_pc();
|
|
value_t<s64> res;
|
|
res.value = call(&exec_rdch, m_thread, m_ir->getInt32(op.ra));
|
|
const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
m_ir->CreateCondBr(m_ir->CreateICmpSLT(res.value, m_ir->getInt64(0)), m_stop, next);
|
|
m_ir->SetInsertPoint(next);
|
|
set_vr(op.rt, insert(splat<u32[4]>(0), 3, trunc<u32>(res)));
|
|
}
|
|
|
|
static u32 exec_rchcnt(SPUThread* _spu, u32 ch)
|
|
{
|
|
return _spu->get_ch_count(ch);
|
|
}
|
|
|
|
void RCHCNT(spu_opcode_t op) //
|
|
{
|
|
value_t<u32> res;
|
|
res.value = call(&exec_rchcnt, m_thread, m_ir->getInt32(op.ra));
|
|
set_vr(op.rt, insert(splat<u32[4]>(0), 3, res));
|
|
}
|
|
|
|
static bool exec_wrch(SPUThread* _spu, u32 ch, u32 value)
|
|
{
|
|
return _spu->set_ch_value(ch, value);
|
|
}
|
|
|
|
void WRCH(spu_opcode_t op) //
|
|
{
|
|
flush();
|
|
update_pc();
|
|
const auto succ = call(&exec_wrch, m_thread, m_ir->getInt32(op.ra), extract(get_vr(op.rt), 3).value);
|
|
const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
m_ir->CreateCondBr(succ, next, m_stop);
|
|
m_ir->SetInsertPoint(next);
|
|
}
|
|
|
|
void LNOP(spu_opcode_t op) //
|
|
{
|
|
update_pc();
|
|
}
|
|
|
|
void NOP(spu_opcode_t op) //
|
|
{
|
|
update_pc();
|
|
}
|
|
|
|
void SYNC(spu_opcode_t op) //
|
|
{
|
|
// This instruction must be used following a store instruction that modifies the instruction stream.
|
|
m_ir->CreateFence(llvm::AtomicOrdering::SequentiallyConsistent);
|
|
}
|
|
|
|
void DSYNC(spu_opcode_t op) //
|
|
{
|
|
// This instruction forces all earlier load, store, and channel instructions to complete before proceeding.
|
|
m_ir->CreateFence(llvm::AtomicOrdering::SequentiallyConsistent);
|
|
}
|
|
|
|
void MFSPR(spu_opcode_t op) //
|
|
{
|
|
// Check SPUInterpreter for notes.
|
|
set_vr(op.rt, splat<u32[4]>(0));
|
|
}
|
|
|
|
void MTSPR(spu_opcode_t op) //
|
|
{
|
|
// Check SPUInterpreter for notes.
|
|
}
|
|
|
|
void SF(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, get_vr(op.rb) - get_vr(op.ra));
|
|
}
|
|
|
|
void OR(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, get_vr(op.ra) | get_vr(op.rb));
|
|
}
|
|
|
|
void BG(spu_opcode_t op)
|
|
{
|
|
const auto a = get_vr(op.ra);
|
|
const auto b = get_vr(op.rb);
|
|
set_vr(op.rt, ~ucarry(a, eval(b - a), b) >> 31);
|
|
}
|
|
|
|
void SFH(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, get_vr<u16[8]>(op.rb) - get_vr<u16[8]>(op.ra));
|
|
}
|
|
|
|
void NOR(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, ~(get_vr(op.ra) | get_vr(op.rb)));
|
|
}
|
|
|
|
void ABSDB(spu_opcode_t op)
|
|
{
|
|
const auto a = get_vr<u8[16]>(op.ra);
|
|
const auto b = get_vr<u8[16]>(op.rb);
|
|
set_vr(op.rt, max(a, b) - min(a, b));
|
|
}
|
|
|
|
void ROT(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, rol(get_vr(op.ra), get_vr(op.rb)));
|
|
}
|
|
|
|
void ROTM(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, trunc<u32[4]>(zext<u64[4]>(get_vr(op.ra)) >> zext<u64[4]>(-get_vr(op.rb) & 0x3f)));
|
|
}
|
|
|
|
void ROTMA(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, trunc<u32[4]>(sext<s64[4]>(get_vr(op.ra)) >> zext<s64[4]>(-get_vr(op.rb) & 0x3f)));
|
|
}
|
|
|
|
void SHL(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, trunc<u32[4]>(zext<u64[4]>(get_vr(op.ra)) << zext<u64[4]>(get_vr(op.rb) & 0x3f)));
|
|
}
|
|
|
|
void ROTH(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, rol(get_vr<u16[8]>(op.ra), get_vr<u16[8]>(op.rb)));
|
|
}
|
|
|
|
void ROTHM(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, trunc<u16[8]>(zext<u32[8]>(get_vr<u16[8]>(op.ra)) >> zext<u32[8]>(-get_vr<u16[8]>(op.rb) & 0x1f)));
|
|
}
|
|
|
|
void ROTMAH(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, trunc<u16[8]>(sext<s32[8]>(get_vr<u16[8]>(op.ra)) >> zext<s32[8]>(-get_vr<u16[8]>(op.rb) & 0x1f)));
|
|
}
|
|
|
|
void SHLH(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, trunc<u16[8]>(zext<u32[8]>(get_vr<u16[8]>(op.ra)) << zext<u32[8]>(get_vr<u16[8]>(op.rb) & 0x1f)));
|
|
}
|
|
|
|
void ROTI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, rol(get_vr(op.ra), op.i7));
|
|
}
|
|
|
|
void ROTMI(spu_opcode_t op)
|
|
{
|
|
if (-op.i7 & 0x20)
|
|
{
|
|
return set_vr(op.rt, splat<u32[4]>(0));
|
|
}
|
|
|
|
set_vr(op.rt, get_vr(op.ra) >> (-op.i7 & 0x1f));
|
|
}
|
|
|
|
void ROTMAI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, get_vr<s32[4]>(op.ra) >> (-op.i7 & 0x20 ? 0x1f : -op.i7 & 0x1f));
|
|
}
|
|
|
|
void SHLI(spu_opcode_t op)
|
|
{
|
|
if (op.i7 & 0x20)
|
|
{
|
|
return set_vr(op.rt, splat<u32[4]>(0));
|
|
}
|
|
|
|
set_vr(op.rt, get_vr(op.ra) << (op.i7 & 0x1f));
|
|
}
|
|
|
|
void ROTHI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, rol(get_vr<u16[8]>(op.ra), op.i7));
|
|
}
|
|
|
|
void ROTHMI(spu_opcode_t op)
|
|
{
|
|
if (-op.i7 & 0x10)
|
|
{
|
|
return set_vr(op.rt, splat<u16[8]>(0));
|
|
}
|
|
|
|
set_vr(op.rt, get_vr<u16[8]>(op.ra) >> (-op.i7 & 0xf));
|
|
}
|
|
|
|
void ROTMAHI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, get_vr<s16[8]>(op.ra) >> (-op.i7 & 0x10 ? 0xf : -op.i7 & 0xf));
|
|
}
|
|
|
|
void SHLHI(spu_opcode_t op)
|
|
{
|
|
if (op.i7 & 0x10)
|
|
{
|
|
return set_vr(op.rt, splat<u16[8]>(0));
|
|
}
|
|
|
|
set_vr(op.rt, get_vr<u16[8]>(op.ra) << (op.i7 & 0xf));
|
|
}
|
|
|
|
void A(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, get_vr(op.ra) + get_vr(op.rb));
|
|
}
|
|
|
|
void AND(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, get_vr(op.ra) & get_vr(op.rb));
|
|
}
|
|
|
|
void CG(spu_opcode_t op)
|
|
{
|
|
const auto a = get_vr(op.ra);
|
|
const auto b = get_vr(op.rb);
|
|
set_vr(op.rt, ucarry(a, b, eval(a + b)) >> 31);
|
|
}
|
|
|
|
void AH(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, get_vr<u16[8]>(op.ra) + get_vr<u16[8]>(op.rb));
|
|
}
|
|
|
|
void NAND(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, ~(get_vr(op.ra) & get_vr(op.rb)));
|
|
}
|
|
|
|
void AVGB(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, avg(get_vr<u8[16]>(op.ra), get_vr<u8[16]>(op.rb)));
|
|
}
|
|
|
|
void GB(spu_opcode_t op)
|
|
{
|
|
// TODO
|
|
value_t<u32> m;
|
|
m.value = eval((get_vr<s32[4]>(op.ra) << 31) < 0).value;
|
|
m.value = m_ir->CreateBitCast(m.value, m_ir->getIntNTy(4));
|
|
m.value = m_ir->CreateZExt(m.value, get_type<u32>());
|
|
set_vr(op.rt, insert(splat<u32[4]>(0), 3, m));
|
|
}
|
|
|
|
void GBH(spu_opcode_t op)
|
|
{
|
|
const auto m = zext<u32>(bitcast<u8>((get_vr<s16[8]>(op.ra) << 15) < 0));
|
|
set_vr(op.rt, insert(splat<u32[4]>(0), 3, m));
|
|
}
|
|
|
|
void GBB(spu_opcode_t op)
|
|
{
|
|
const auto m = zext<u32>(bitcast<u16>((get_vr<s8[16]>(op.ra) << 7) < 0));
|
|
set_vr(op.rt, insert(splat<u32[4]>(0), 3, m));
|
|
}
|
|
|
|
void FSM(spu_opcode_t op)
|
|
{
|
|
// TODO
|
|
value_t<bool[4]> m;
|
|
m.value = extract(get_vr(op.ra), 3).value;
|
|
m.value = m_ir->CreateTrunc(m.value, m_ir->getIntNTy(4));
|
|
m.value = m_ir->CreateBitCast(m.value, get_type<bool[4]>());
|
|
set_vr(op.rt, sext<u32[4]>(m));
|
|
}
|
|
|
|
void FSMH(spu_opcode_t op)
|
|
{
|
|
const auto m = bitcast<bool[8]>(trunc<u8>(extract(get_vr(op.ra), 3)));
|
|
set_vr(op.rt, sext<u16[8]>(m));
|
|
}
|
|
|
|
void FSMB(spu_opcode_t op)
|
|
{
|
|
const auto m = bitcast<bool[16]>(trunc<u16>(extract(get_vr(op.ra), 3)));
|
|
set_vr(op.rt, sext<u8[16]>(m));
|
|
}
|
|
|
|
void ROTQBYBI(spu_opcode_t op)
|
|
{
|
|
value_t<u8[16]> sh;
|
|
u8 initial[16]{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
|
|
sh.value = llvm::ConstantDataVector::get(m_context, initial);
|
|
sh = eval((sh - (zshuffle<u8[16]>(get_vr<u8[16]>(op.rb), 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12) >> 3)) & 0xf);
|
|
set_vr(op.rt, pshufb(get_vr<u8[16]>(op.ra), sh));
|
|
}
|
|
|
|
void ROTQMBYBI(spu_opcode_t op)
|
|
{
|
|
value_t<u8[16]> sh;
|
|
u8 initial[16]{112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127};
|
|
sh.value = llvm::ConstantDataVector::get(m_context, initial);
|
|
sh = eval(sh + (-(zshuffle<u8[16]>(get_vr<u8[16]>(op.rb), 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12) >> 3) & 0x1f));
|
|
set_vr(op.rt, pshufb(get_vr<u8[16]>(op.ra), sh));
|
|
}
|
|
|
|
void SHLQBYBI(spu_opcode_t op)
|
|
{
|
|
value_t<u8[16]> sh;
|
|
u8 initial[16]{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
|
|
sh.value = llvm::ConstantDataVector::get(m_context, initial);
|
|
sh = eval(sh - (zshuffle<u8[16]>(get_vr<u8[16]>(op.rb), 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12) >> 3));
|
|
set_vr(op.rt, pshufb(get_vr<u8[16]>(op.ra), sh));
|
|
}
|
|
|
|
void CBX(spu_opcode_t op)
|
|
{
|
|
const auto i = eval(~(extract(get_vr(op.ra), 3) + extract(get_vr(op.rb), 3)) & 0xf);
|
|
value_t<u8[16]> r;
|
|
u8 initial[16]{0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10};
|
|
r.value = llvm::ConstantDataVector::get(m_context, initial);
|
|
r.value = m_ir->CreateInsertElement(r.value, m_ir->getInt8(0x3), i.value);
|
|
set_vr(op.rt, r);
|
|
}
|
|
|
|
void CHX(spu_opcode_t op)
|
|
{
|
|
const auto i = eval(~(extract(get_vr(op.ra), 3) + extract(get_vr(op.rb), 3)) >> 1 & 0x7);
|
|
value_t<u16[8]> r;
|
|
u16 initial[8]{0x1e1f, 0x1c1d, 0x1a1b, 0x1819, 0x1617, 0x1415, 0x1213, 0x1011};
|
|
r.value = llvm::ConstantDataVector::get(m_context, initial);
|
|
r.value = m_ir->CreateInsertElement(r.value, m_ir->getInt16(0x0203), i.value);
|
|
set_vr(op.rt, r);
|
|
}
|
|
|
|
void CWX(spu_opcode_t op)
|
|
{
|
|
const auto i = eval(~(extract(get_vr(op.ra), 3) + extract(get_vr(op.rb), 3)) >> 2 & 0x3);
|
|
value_t<u32[4]> r;
|
|
u32 initial[4]{0x1c1d1e1f, 0x18191a1b, 0x14151617, 0x10111213};
|
|
r.value = llvm::ConstantDataVector::get(m_context, initial);
|
|
r.value = m_ir->CreateInsertElement(r.value, m_ir->getInt32(0x010203), i.value);
|
|
set_vr(op.rt, r);
|
|
}
|
|
|
|
void CDX(spu_opcode_t op)
|
|
{
|
|
const auto i = eval(~(extract(get_vr(op.ra), 3) + extract(get_vr(op.rb), 3)) >> 3 & 0x1);
|
|
value_t<u64[2]> r;
|
|
u64 initial[2]{0x18191a1b1c1d1e1f, 0x1011121314151617};
|
|
r.value = llvm::ConstantDataVector::get(m_context, initial);
|
|
r.value = m_ir->CreateInsertElement(r.value, m_ir->getInt64(0x01020304050607), i.value);
|
|
set_vr(op.rt, r);
|
|
}
|
|
|
|
void ROTQBI(spu_opcode_t op)
|
|
{
|
|
const auto a = get_vr(op.ra);
|
|
const auto b = zshuffle<u32[4]>(get_vr<u32[4]>(op.rb) & 0x7, 3, 3, 3, 3);
|
|
set_vr(op.rt, a << b | zshuffle<u32[4]>(a, 3, 0, 1, 2) >> (32 - b));
|
|
}
|
|
|
|
void ROTQMBI(spu_opcode_t op)
|
|
{
|
|
const auto a = get_vr(op.ra);
|
|
const auto b = zshuffle<u32[4]>(-get_vr<u32[4]>(op.rb) & 0x7, 3, 3, 3, 3);
|
|
set_vr(op.rt, a >> b | zshuffle<u32[4]>(a, 1, 2, 3, 4) << (32 - b));
|
|
}
|
|
|
|
void SHLQBI(spu_opcode_t op)
|
|
{
|
|
const auto a = get_vr(op.ra);
|
|
const auto b = zshuffle<u32[4]>(get_vr<u32[4]>(op.rb) & 0x7, 3, 3, 3, 3);
|
|
set_vr(op.rt, a << b | zshuffle<u32[4]>(a, 4, 0, 1, 2) >> (32 - b));
|
|
}
|
|
|
|
void ROTQBY(spu_opcode_t op)
|
|
{
|
|
value_t<u8[16]> sh;
|
|
u8 initial[16]{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
|
|
sh.value = llvm::ConstantDataVector::get(m_context, initial);
|
|
sh = eval((sh - zshuffle<u8[16]>(get_vr<u8[16]>(op.rb), 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12)) & 0xf);
|
|
set_vr(op.rt, pshufb(get_vr<u8[16]>(op.ra), sh));
|
|
}
|
|
|
|
void ROTQMBY(spu_opcode_t op)
|
|
{
|
|
value_t<u8[16]> sh;
|
|
u8 initial[16]{112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127};
|
|
sh.value = llvm::ConstantDataVector::get(m_context, initial);
|
|
sh = eval(sh + (-zshuffle<u8[16]>(get_vr<u8[16]>(op.rb), 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12) & 0x1f));
|
|
set_vr(op.rt, pshufb(get_vr<u8[16]>(op.ra), sh));
|
|
}
|
|
|
|
void SHLQBY(spu_opcode_t op)
|
|
{
|
|
value_t<u8[16]> sh;
|
|
u8 initial[16]{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
|
|
sh.value = llvm::ConstantDataVector::get(m_context, initial);
|
|
sh = eval(sh - (zshuffle<u8[16]>(get_vr<u8[16]>(op.rb), 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12) & 0x1f));
|
|
set_vr(op.rt, pshufb(get_vr<u8[16]>(op.ra), sh));
|
|
}
|
|
|
|
void ORX(spu_opcode_t op)
|
|
{
|
|
const auto a = get_vr(op.ra);
|
|
const auto x = zshuffle<u32[4]>(a, 2, 3, 0, 1) | a;
|
|
const auto y = zshuffle<u32[4]>(x, 1, 0, 3, 2) | x;
|
|
set_vr(op.rt, zshuffle<u32[4]>(y, 4, 4, 4, 3));
|
|
}
|
|
|
|
void CBD(spu_opcode_t op)
|
|
{
|
|
const auto i = eval(~(extract(get_vr(op.ra), 3) + op.i7) & 0xf);
|
|
value_t<u8[16]> r;
|
|
u8 initial[16]{0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10};
|
|
r.value = llvm::ConstantDataVector::get(m_context, initial);
|
|
r.value = m_ir->CreateInsertElement(r.value, m_ir->getInt8(0x3), i.value);
|
|
set_vr(op.rt, r);
|
|
}
|
|
|
|
void CHD(spu_opcode_t op)
|
|
{
|
|
const auto i = eval(~(extract(get_vr(op.ra), 3) + op.i7) >> 1 & 0x7);
|
|
value_t<u16[8]> r;
|
|
u16 initial[8]{0x1e1f, 0x1c1d, 0x1a1b, 0x1819, 0x1617, 0x1415, 0x1213, 0x1011};
|
|
r.value = llvm::ConstantDataVector::get(m_context, initial);
|
|
r.value = m_ir->CreateInsertElement(r.value, m_ir->getInt16(0x0203), i.value);
|
|
set_vr(op.rt, r);
|
|
}
|
|
|
|
void CWD(spu_opcode_t op)
|
|
{
|
|
const auto i = eval(~(extract(get_vr(op.ra), 3) + op.i7) >> 2 & 0x3);
|
|
value_t<u32[4]> r;
|
|
u32 initial[4]{0x1c1d1e1f, 0x18191a1b, 0x14151617, 0x10111213};
|
|
r.value = llvm::ConstantDataVector::get(m_context, initial);
|
|
r.value = m_ir->CreateInsertElement(r.value, m_ir->getInt32(0x010203), i.value);
|
|
set_vr(op.rt, r);
|
|
}
|
|
|
|
void CDD(spu_opcode_t op)
|
|
{
|
|
const auto i = eval(~(extract(get_vr(op.ra), 3) + op.i7) >> 3 & 0x1);
|
|
value_t<u64[2]> r;
|
|
u64 initial[2]{0x18191a1b1c1d1e1f, 0x1011121314151617};
|
|
r.value = llvm::ConstantDataVector::get(m_context, initial);
|
|
r.value = m_ir->CreateInsertElement(r.value, m_ir->getInt64(0x01020304050607), i.value);
|
|
set_vr(op.rt, r);
|
|
}
|
|
|
|
void ROTQBII(spu_opcode_t op)
|
|
{
|
|
const auto s = op.i7 & 0x7;
|
|
const auto a = get_vr(op.ra);
|
|
|
|
if (s == 0)
|
|
{
|
|
return set_vr(op.rt, a);
|
|
}
|
|
|
|
set_vr(op.rt, a << s | zshuffle<u32[4]>(a, 3, 0, 1, 2) >> (32 - s));
|
|
}
|
|
|
|
void ROTQMBII(spu_opcode_t op)
|
|
{
|
|
const auto s = -op.i7 & 0x7;
|
|
const auto a = get_vr(op.ra);
|
|
|
|
if (s == 0)
|
|
{
|
|
return set_vr(op.rt, a);
|
|
}
|
|
|
|
set_vr(op.rt, a >> s | zshuffle<u32[4]>(a, 1, 2, 3, 4) << (32 - s));
|
|
}
|
|
|
|
void SHLQBII(spu_opcode_t op)
|
|
{
|
|
const auto s = op.i7 & 0x7;
|
|
const auto a = get_vr(op.ra);
|
|
|
|
if (s == 0)
|
|
{
|
|
return set_vr(op.rt, a);
|
|
}
|
|
|
|
set_vr(op.rt, a << s | zshuffle<u32[4]>(a, 4, 0, 1, 2) >> (32 - s));
|
|
}
|
|
|
|
void ROTQBYI(spu_opcode_t op)
|
|
{
|
|
const u32 s = -op.i7 & 0xf;
|
|
set_vr(op.rt, zshuffle<u8[16]>(get_vr<u8[16]>(op.ra),
|
|
s & 15, (s + 1) & 15, (s + 2) & 15, (s + 3) & 15,
|
|
(s + 4) & 15, (s + 5) & 15, (s + 6) & 15, (s + 7) & 15,
|
|
(s + 8) & 15, (s + 9) & 15, (s + 10) & 15, (s + 11) & 15,
|
|
(s + 12) & 15, (s + 13) & 15, (s + 14) & 15, (s + 15) & 15));
|
|
}
|
|
|
|
void ROTQMBYI(spu_opcode_t op)
|
|
{
|
|
const u32 s = -op.i7 & 0x1f;
|
|
|
|
if (s >= 16)
|
|
{
|
|
return set_vr(op.rt, splat<u32[4]>(0));
|
|
}
|
|
|
|
set_vr(op.rt, zshuffle<u8[16]>(get_vr<u8[16]>(op.ra),
|
|
s, s + 1, s + 2, s + 3,
|
|
s + 4, s + 5, s + 6, s + 7,
|
|
s + 8, s + 9, s + 10, s + 11,
|
|
s + 12, s + 13, s + 14, s + 15));
|
|
}
|
|
|
|
void SHLQBYI(spu_opcode_t op)
|
|
{
|
|
const u32 s = op.i7 & 0x1f;
|
|
|
|
if (s >= 16)
|
|
{
|
|
return set_vr(op.rt, splat<u32[4]>(0));
|
|
}
|
|
|
|
const u32 x = -s;
|
|
|
|
set_vr(op.rt, zshuffle<u8[16]>(get_vr<u8[16]>(op.ra),
|
|
x & 31, (x + 1) & 31, (x + 2) & 31, (x + 3) & 31,
|
|
(x + 4) & 31, (x + 5) & 31, (x + 6) & 31, (x + 7) & 31,
|
|
(x + 8) & 31, (x + 9) & 31, (x + 10) & 31, (x + 11) & 31,
|
|
(x + 12) & 31, (x + 13) & 31, (x + 14) & 31, (x + 15) & 31));
|
|
}
|
|
|
|
void CGT(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, sext<u32[4]>(get_vr<s32[4]>(op.ra) > get_vr<s32[4]>(op.rb)));
|
|
}
|
|
|
|
void XOR(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, get_vr(op.ra) ^ get_vr(op.rb));
|
|
}
|
|
|
|
void CGTH(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, sext<u16[8]>(get_vr<s16[8]>(op.ra) > get_vr<s16[8]>(op.rb)));
|
|
}
|
|
|
|
void EQV(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, ~(get_vr(op.ra) ^ get_vr(op.rb)));
|
|
}
|
|
|
|
void CGTB(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, sext<u8[16]>(get_vr<s8[16]>(op.ra) > get_vr<s8[16]>(op.rb)));
|
|
}
|
|
|
|
void SUMB(spu_opcode_t op)
|
|
{
|
|
const auto a = get_vr<u16[8]>(op.ra);
|
|
const auto b = get_vr<u16[8]>(op.rb);
|
|
const auto ahs = eval((a >> 8) + (a & 0xff));
|
|
const auto bhs = eval((b >> 8) + (b & 0xff));
|
|
const auto lsh = shuffle2<u16[8]>(ahs, bhs, 0, 9, 2, 11, 4, 13, 6, 15);
|
|
const auto hsh = shuffle2<u16[8]>(ahs, bhs, 1, 8, 3, 10, 5, 12, 7, 14);
|
|
set_vr(op.rt, lsh + hsh);
|
|
}
|
|
|
|
void CLZ(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, ctlz(get_vr(op.ra)));
|
|
}
|
|
|
|
void XSWD(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, get_vr<s64[2]>(op.ra) << 32 >> 32);
|
|
}
|
|
|
|
void XSHW(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, get_vr<s32[4]>(op.ra) << 16 >> 16);
|
|
}
|
|
|
|
void CNTB(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, ctpop(get_vr<u8[16]>(op.ra)));
|
|
}
|
|
|
|
void XSBH(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, get_vr<s16[8]>(op.ra) << 8 >> 8);
|
|
}
|
|
|
|
void CLGT(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, sext<u32[4]>(get_vr(op.ra) > get_vr(op.rb)));
|
|
}
|
|
|
|
void ANDC(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, get_vr(op.ra) & ~get_vr(op.rb));
|
|
}
|
|
|
|
void CLGTH(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, sext<u16[8]>(get_vr<u16[8]>(op.ra) > get_vr<u16[8]>(op.rb)));
|
|
}
|
|
|
|
void ORC(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, get_vr(op.ra) | ~get_vr(op.rb));
|
|
}
|
|
|
|
void CLGTB(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, sext<u8[16]>(get_vr<u8[16]>(op.ra) > get_vr<u8[16]>(op.rb)));
|
|
}
|
|
|
|
void CEQ(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, sext<u32[4]>(get_vr(op.ra) == get_vr(op.rb)));
|
|
}
|
|
|
|
void MPYHHU(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, (get_vr(op.ra) >> 16) * (get_vr(op.rb) >> 16));
|
|
}
|
|
|
|
void ADDX(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, get_vr(op.ra) + get_vr(op.rb) + (get_vr(op.rt) & 1));
|
|
}
|
|
|
|
void SFX(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, get_vr(op.rb) - get_vr(op.ra) - (~get_vr(op.rt) & 1));
|
|
}
|
|
|
|
void CGX(spu_opcode_t op)
|
|
{
|
|
const auto a = get_vr(op.ra);
|
|
const auto b = get_vr(op.rb);
|
|
const auto c = eval(get_vr(op.rt) << 31);
|
|
const auto s = eval(a + b);
|
|
set_vr(op.rt, (ucarry(a, b, s) | (sext<u32[4]>(s == 0xffffffffu) & c)) >> 31);
|
|
}
|
|
|
|
void BGX(spu_opcode_t op)
|
|
{
|
|
const auto a = get_vr(op.ra);
|
|
const auto b = get_vr(op.rb);
|
|
const auto c = eval(get_vr(op.rt) << 31);
|
|
const auto d = eval(b - a);
|
|
set_vr(op.rt, (~ucarry(a, d, b) & ~(sext<u32[4]>(d == 0) & ~c)) >> 31);
|
|
}
|
|
|
|
void MPYHHA(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, (get_vr<s32[4]>(op.ra) >> 16) * (get_vr<s32[4]>(op.rb) >> 16) + get_vr<s32[4]>(op.rt));
|
|
}
|
|
|
|
void MPYHHAU(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, (get_vr(op.ra) >> 16) * (get_vr(op.rb) >> 16) + get_vr(op.rt));
|
|
}
|
|
|
|
void MPY(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, (get_vr<s32[4]>(op.ra) << 16 >> 16) * (get_vr<s32[4]>(op.rb) << 16 >> 16));
|
|
}
|
|
|
|
void MPYH(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, (get_vr(op.ra) >> 16) * (get_vr(op.rb) << 16));
|
|
}
|
|
|
|
void MPYHH(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, (get_vr<s32[4]>(op.ra) >> 16) * (get_vr<s32[4]>(op.rb) >> 16));
|
|
}
|
|
|
|
void MPYS(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, (get_vr<s32[4]>(op.ra) << 16 >> 16) * (get_vr<s32[4]>(op.rb) << 16 >> 16) >> 16);
|
|
}
|
|
|
|
void CEQH(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, sext<u16[8]>(get_vr<u16[8]>(op.ra) == get_vr<u16[8]>(op.rb)));
|
|
}
|
|
|
|
void MPYU(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, (get_vr(op.ra) << 16 >> 16) * (get_vr(op.rb) << 16 >> 16));
|
|
}
|
|
|
|
void CEQB(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, sext<u8[16]>(get_vr<u8[16]>(op.ra) == get_vr<u8[16]>(op.rb)));
|
|
}
|
|
|
|
void FSMBI(spu_opcode_t op)
|
|
{
|
|
u8 data[16];
|
|
for (u32 i = 0; i < 16; i++)
|
|
data[i] = op.i16 & (1u << i) ? 0xff : 0;
|
|
value_t<u8[16]> r;
|
|
r.value = llvm::ConstantDataVector::get(m_context, data);
|
|
set_vr(op.rt, r);
|
|
}
|
|
|
|
void IL(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, splat<s32[4]>(op.si16));
|
|
}
|
|
|
|
void ILHU(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, splat<u32[4]>(op.i16 << 16));
|
|
}
|
|
|
|
void ILH(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, splat<u16[8]>(op.i16));
|
|
}
|
|
|
|
void IOHL(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, get_vr(op.rt) | op.i16);
|
|
}
|
|
|
|
void ORI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, get_vr<s32[4]>(op.ra) | op.si10);
|
|
}
|
|
|
|
void ORHI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, get_vr<s16[8]>(op.ra) | op.si10);
|
|
}
|
|
|
|
void ORBI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, get_vr<s8[16]>(op.ra) | op.si10);
|
|
}
|
|
|
|
void SFI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, op.si10 - get_vr<s32[4]>(op.ra));
|
|
}
|
|
|
|
void SFHI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, op.si10 - get_vr<s16[8]>(op.ra));
|
|
}
|
|
|
|
void ANDI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, get_vr<s32[4]>(op.ra) & op.si10);
|
|
}
|
|
|
|
void ANDHI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, get_vr<s16[8]>(op.ra) & op.si10);
|
|
}
|
|
|
|
void ANDBI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, get_vr<s8[16]>(op.ra) & op.si10);
|
|
}
|
|
|
|
void AI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, get_vr<s32[4]>(op.ra) + op.si10);
|
|
}
|
|
|
|
void AHI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, get_vr<s16[8]>(op.ra) + op.si10);
|
|
}
|
|
|
|
void XORI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, get_vr<s32[4]>(op.ra) ^ op.si10);
|
|
}
|
|
|
|
void XORHI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, get_vr<s16[8]>(op.ra) ^ op.si10);
|
|
}
|
|
|
|
void XORBI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, get_vr<s8[16]>(op.ra) ^ op.si10);
|
|
}
|
|
|
|
void CGTI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, sext<u32[4]>(get_vr<s32[4]>(op.ra) > op.si10));
|
|
}
|
|
|
|
void CGTHI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, sext<u16[8]>(get_vr<s16[8]>(op.ra) > op.si10));
|
|
}
|
|
|
|
void CGTBI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, sext<u8[16]>(get_vr<s8[16]>(op.ra) > op.si10));
|
|
}
|
|
|
|
void CLGTI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, sext<u32[4]>(get_vr(op.ra) > op.si10));
|
|
}
|
|
|
|
void CLGTHI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, sext<u16[8]>(get_vr<u16[8]>(op.ra) > op.si10));
|
|
}
|
|
|
|
void CLGTBI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, sext<u8[16]>(get_vr<u8[16]>(op.ra) > op.si10));
|
|
}
|
|
|
|
void MPYI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, (get_vr<s32[4]>(op.ra) << 16 >> 16) * splat<s32[4]>(op.si10));
|
|
}
|
|
|
|
void MPYUI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, (get_vr(op.ra) << 16 >> 16) * splat<u32[4]>(op.si10 & 0xffff));
|
|
}
|
|
|
|
void CEQI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, sext<u32[4]>(get_vr(op.ra) == op.si10));
|
|
}
|
|
|
|
void CEQHI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, sext<u16[8]>(get_vr<u16[8]>(op.ra) == op.si10));
|
|
}
|
|
|
|
void CEQBI(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, sext<u8[16]>(get_vr<u8[16]>(op.ra) == op.si10));
|
|
}
|
|
|
|
void ILA(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt, splat<u32[4]>(op.i18));
|
|
}
|
|
|
|
void SELB(spu_opcode_t op)
|
|
{
|
|
const auto c = get_vr(op.rc);
|
|
set_vr(op.rt4, (get_vr(op.ra) & ~c) | (get_vr(op.rb) & c));
|
|
}
|
|
|
|
void SHUFB(spu_opcode_t op)
|
|
{
|
|
const auto c = get_vr<u8[16]>(op.rc);
|
|
const auto x = avg(sext<u8[16]>((c & 0xc0) == 0xc0), sext<u8[16]>((c & 0xe0) == 0xc0));
|
|
const auto cr = c ^ 0xf;
|
|
const auto a = pshufb(get_vr<u8[16]>(op.ra), cr);
|
|
const auto b = pshufb(get_vr<u8[16]>(op.rb), cr);
|
|
set_vr(op.rt4, merge(sext<u8[16]>((c & 0x10) == 0), a, b) | x);
|
|
}
|
|
|
|
void MPYA(spu_opcode_t op)
|
|
{
|
|
set_vr(op.rt4, (get_vr<s32[4]>(op.ra) << 16 >> 16) * (get_vr<s32[4]>(op.rb) << 16 >> 16) + get_vr<s32[4]>(op.rc));
|
|
}
|
|
|
|
void FSCRRD(spu_opcode_t op) //
|
|
{
|
|
// Hack
|
|
set_vr(op.rt, splat<u32[4]>(0));
|
|
}
|
|
|
|
void FSCRWR(spu_opcode_t op) //
|
|
{
|
|
// Hack
|
|
}
|
|
|
|
void DFCGT(spu_opcode_t op) //
|
|
{
|
|
return UNK(op);
|
|
}
|
|
|
|
void DFCEQ(spu_opcode_t op) //
|
|
{
|
|
return UNK(op);
|
|
}
|
|
|
|
void DFCMGT(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, sext<u64[2]>(fcmp<llvm::FCmpInst::FCMP_OGT>(fabs(get_vr<f64[2]>(op.ra)), fabs(get_vr<f64[2]>(op.rb)))));
|
|
}
|
|
|
|
void DFCMEQ(spu_opcode_t op) //
|
|
{
|
|
return UNK(op);
|
|
}
|
|
|
|
void DFTSV(spu_opcode_t op) //
|
|
{
|
|
return UNK(op);
|
|
}
|
|
|
|
void DFA(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, get_vr<f64[2]>(op.ra) + get_vr<f64[2]>(op.rb));
|
|
}
|
|
|
|
void DFS(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, get_vr<f64[2]>(op.ra) - get_vr<f64[2]>(op.rb));
|
|
}
|
|
|
|
void DFM(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, get_vr<f64[2]>(op.ra) * get_vr<f64[2]>(op.rb));
|
|
}
|
|
|
|
void DFMA(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, get_vr<f64[2]>(op.ra) * get_vr<f64[2]>(op.rb) + get_vr<f64[2]>(op.rt));
|
|
}
|
|
|
|
void DFMS(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, get_vr<f64[2]>(op.ra) * get_vr<f64[2]>(op.rb) - get_vr<f64[2]>(op.rt));
|
|
}
|
|
|
|
void DFNMS(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, get_vr<f64[2]>(op.rt) - get_vr<f64[2]>(op.ra) * get_vr<f64[2]>(op.rb));
|
|
}
|
|
|
|
void DFNMA(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, -get_vr<f64[2]>(op.rt) - get_vr<f64[2]>(op.ra) * get_vr<f64[2]>(op.rb));
|
|
}
|
|
|
|
void FREST(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, fsplat<f32[4]>(1.0) / get_vr<f32[4]>(op.ra));
|
|
}
|
|
|
|
void FRSQEST(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, fsplat<f32[4]>(1.0) / sqrt(fabs(get_vr<f32[4]>(op.ra))));
|
|
}
|
|
|
|
void FCGT(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, sext<u32[4]>(fcmp<llvm::FCmpInst::FCMP_OGT>(get_vr<f32[4]>(op.ra), get_vr<f32[4]>(op.rb))));
|
|
}
|
|
|
|
void FCMGT(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, sext<u32[4]>(fcmp<llvm::FCmpInst::FCMP_OGT>(fabs(get_vr<f32[4]>(op.ra)), fabs(get_vr<f32[4]>(op.rb)))));
|
|
}
|
|
|
|
void FA(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, get_vr<f32[4]>(op.ra) + get_vr<f32[4]>(op.rb));
|
|
}
|
|
|
|
void FS(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, get_vr<f32[4]>(op.ra) - get_vr<f32[4]>(op.rb));
|
|
}
|
|
|
|
void FM(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, get_vr<f32[4]>(op.ra) * get_vr<f32[4]>(op.rb));
|
|
}
|
|
|
|
void FESD(spu_opcode_t op) //
|
|
{
|
|
value_t<f64[2]> r;
|
|
r.value = m_ir->CreateFPExt(shuffle2<f32[2]>(get_vr<f32[4]>(op.ra), fsplat<f32[4]>(0.), 1, 3).value, get_type<f64[2]>());
|
|
set_vr(op.rt, r);
|
|
}
|
|
|
|
void FRDS(spu_opcode_t op) //
|
|
{
|
|
value_t<f32[2]> r;
|
|
r.value = m_ir->CreateFPTrunc(get_vr<f64[2]>(op.ra).value, get_type<f32[2]>());
|
|
set_vr(op.rt, shuffle2<f32[4]>(r, fsplat<f32[2]>(0.), 2, 0, 3, 1));
|
|
}
|
|
|
|
void FCEQ(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, sext<u32[4]>(fcmp<llvm::FCmpInst::FCMP_OEQ>(get_vr<f32[4]>(op.ra), get_vr<f32[4]>(op.rb))));
|
|
}
|
|
|
|
void FCMEQ(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, sext<u32[4]>(fcmp<llvm::FCmpInst::FCMP_OEQ>(fabs(get_vr<f32[4]>(op.ra)), fabs(get_vr<f32[4]>(op.rb)))));
|
|
}
|
|
|
|
void FNMS(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt4, get_vr<f32[4]>(op.rc) - get_vr<f32[4]>(op.ra) * get_vr<f32[4]>(op.rb));
|
|
}
|
|
|
|
void FMA(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt4, get_vr<f32[4]>(op.ra) * get_vr<f32[4]>(op.rb) + get_vr<f32[4]>(op.rc));
|
|
}
|
|
|
|
void FMS(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt4, get_vr<f32[4]>(op.ra) * get_vr<f32[4]>(op.rb) - get_vr<f32[4]>(op.rc));
|
|
}
|
|
|
|
void FI(spu_opcode_t op) //
|
|
{
|
|
set_vr(op.rt, get_vr<f32[4]>(op.rb));
|
|
}
|
|
|
|
void CFLTS(spu_opcode_t op) //
|
|
{
|
|
value_t<f32[4]> a = get_vr<f32[4]>(op.ra);
|
|
if (op.i8 != 173)
|
|
a = eval(a * fsplat<f32[4]>(std::exp2(static_cast<float>(static_cast<s16>(173 - op.i8)))));
|
|
|
|
value_t<s32[4]> r;
|
|
r.value = m_ir->CreateFPToSI(a.value, get_type<s32[4]>());
|
|
set_vr(op.rt, r ^ sext<s32[4]>(fcmp<llvm::FCmpInst::FCMP_OGE>(a, fsplat<f32[4]>(std::exp2(31.f)))));
|
|
}
|
|
|
|
void CFLTU(spu_opcode_t op) //
|
|
{
|
|
value_t<f32[4]> a = get_vr<f32[4]>(op.ra);
|
|
if (op.i8 != 173)
|
|
a = eval(a * fsplat<f32[4]>(std::exp2(static_cast<float>(static_cast<s16>(173 - op.i8)))));
|
|
|
|
value_t<s32[4]> r;
|
|
r.value = m_ir->CreateFPToUI(a.value, get_type<s32[4]>());
|
|
set_vr(op.rt, r & ~(bitcast<s32[4]>(a) >> 31));
|
|
}
|
|
|
|
void CSFLT(spu_opcode_t op) //
|
|
{
|
|
value_t<f32[4]> r;
|
|
r.value = m_ir->CreateSIToFP(get_vr<s32[4]>(op.ra).value, get_type<f32[4]>());
|
|
if (op.i8 != 155)
|
|
r = eval(r * fsplat<f32[4]>(std::exp2(static_cast<float>(static_cast<s16>(op.i8 - 155)))));
|
|
set_vr(op.rt, r);
|
|
}
|
|
|
|
void CUFLT(spu_opcode_t op) //
|
|
{
|
|
value_t<f32[4]> r;
|
|
r.value = m_ir->CreateUIToFP(get_vr<s32[4]>(op.ra).value, get_type<f32[4]>());
|
|
if (op.i8 != 155)
|
|
r = eval(r * fsplat<f32[4]>(std::exp2(static_cast<float>(static_cast<s16>(op.i8 - 155)))));
|
|
set_vr(op.rt, r);
|
|
}
|
|
|
|
void STQX(spu_opcode_t op) //
|
|
{
|
|
value_t<u64> addr = zext<u64>((extract(get_vr(op.ra), 3) + extract(get_vr(op.rb), 3)) & 0x3fff0);
|
|
addr.value = m_ir->CreateAdd(m_lsptr, addr.value);
|
|
value_t<u8[16]> r = get_vr<u8[16]>(op.rt);
|
|
r.value = m_ir->CreateShuffleVector(r.value, r.value, {15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0});
|
|
m_ir->CreateStore(r.value, m_ir->CreateIntToPtr(addr.value, get_type<u8[16]>()->getPointerTo()));
|
|
}
|
|
|
|
void LQX(spu_opcode_t op) //
|
|
{
|
|
value_t<u64> addr = zext<u64>((extract(get_vr(op.ra), 3) + extract(get_vr(op.rb), 3)) & 0x3fff0);
|
|
addr.value = m_ir->CreateAdd(m_lsptr, addr.value);
|
|
value_t<u8[16]> r;
|
|
r.value = m_ir->CreateLoad(m_ir->CreateIntToPtr(addr.value, get_type<u8[16]>()->getPointerTo()));
|
|
r.value = m_ir->CreateShuffleVector(r.value, r.value, {15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0});
|
|
set_vr(op.rt, r);
|
|
}
|
|
|
|
void STQA(spu_opcode_t op) //
|
|
{
|
|
value_t<u64> addr = splat<u64>(spu_ls_target(0, op.i16));
|
|
addr.value = m_ir->CreateAdd(m_lsptr, addr.value);
|
|
value_t<u8[16]> r = get_vr<u8[16]>(op.rt);
|
|
r.value = m_ir->CreateShuffleVector(r.value, r.value, {15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0});
|
|
m_ir->CreateStore(r.value, m_ir->CreateIntToPtr(addr.value, get_type<u8[16]>()->getPointerTo()));
|
|
}
|
|
|
|
void LQA(spu_opcode_t op) //
|
|
{
|
|
value_t<u64> addr = splat<u64>(spu_ls_target(0, op.i16));
|
|
addr.value = m_ir->CreateAdd(m_lsptr, addr.value);
|
|
value_t<u8[16]> r;
|
|
r.value = m_ir->CreateLoad(m_ir->CreateIntToPtr(addr.value, get_type<u8[16]>()->getPointerTo()));
|
|
r.value = m_ir->CreateShuffleVector(r.value, r.value, {15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0});
|
|
set_vr(op.rt, r);
|
|
}
|
|
|
|
void STQR(spu_opcode_t op) //
|
|
{
|
|
value_t<u64> addr = splat<u64>(spu_ls_target(m_pos, op.i16));
|
|
addr.value = m_ir->CreateAdd(m_lsptr, addr.value);
|
|
value_t<u8[16]> r = get_vr<u8[16]>(op.rt);
|
|
r.value = m_ir->CreateShuffleVector(r.value, r.value, {15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0});
|
|
m_ir->CreateStore(r.value, m_ir->CreateIntToPtr(addr.value, get_type<u8[16]>()->getPointerTo()));
|
|
}
|
|
|
|
void LQR(spu_opcode_t op) //
|
|
{
|
|
value_t<u64> addr = splat<u64>(spu_ls_target(m_pos, op.i16));
|
|
addr.value = m_ir->CreateAdd(m_lsptr, addr.value);
|
|
value_t<u8[16]> r;
|
|
r.value = m_ir->CreateLoad(m_ir->CreateIntToPtr(addr.value, get_type<u8[16]>()->getPointerTo()));
|
|
r.value = m_ir->CreateShuffleVector(r.value, r.value, {15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0});
|
|
set_vr(op.rt, r);
|
|
}
|
|
|
|
void STQD(spu_opcode_t op) //
|
|
{
|
|
value_t<u64> addr = zext<u64>((extract(get_vr(op.ra), 3) + (op.si10 << 4)) & 0x3fff0);
|
|
addr.value = m_ir->CreateAdd(m_lsptr, addr.value);
|
|
value_t<u8[16]> r = get_vr<u8[16]>(op.rt);
|
|
r.value = m_ir->CreateShuffleVector(r.value, r.value, {15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0});
|
|
m_ir->CreateStore(r.value, m_ir->CreateIntToPtr(addr.value, get_type<u8[16]>()->getPointerTo()));
|
|
}
|
|
|
|
void LQD(spu_opcode_t op) //
|
|
{
|
|
value_t<u64> addr = zext<u64>((extract(get_vr(op.ra), 3) + (op.si10 << 4)) & 0x3fff0);
|
|
addr.value = m_ir->CreateAdd(m_lsptr, addr.value);
|
|
value_t<u8[16]> r;
|
|
r.value = m_ir->CreateLoad(m_ir->CreateIntToPtr(addr.value, get_type<u8[16]>()->getPointerTo()));
|
|
r.value = m_ir->CreateShuffleVector(r.value, r.value, {15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0});
|
|
set_vr(op.rt, r);
|
|
}
|
|
|
|
void make_halt(llvm::BasicBlock* next)
|
|
{
|
|
const auto pstatus = spu_ptr<u32>(&SPUThread::status);
|
|
const auto chalt = m_ir->getInt32(SPU_STATUS_STOPPED_BY_HALT);
|
|
m_ir->CreateAtomicRMW(llvm::AtomicRMWInst::Or, pstatus, chalt, llvm::AtomicOrdering::Release)->setVolatile(true);
|
|
const auto ptr = m_ir->CreateIntToPtr(m_ir->getInt64(reinterpret_cast<u64>(vm::base(0xffdead00))), get_type<u32*>());
|
|
m_ir->CreateStore(m_ir->getInt32("HALT"_u32), ptr)->setVolatile(true);
|
|
m_ir->CreateBr(next);
|
|
}
|
|
|
|
void HGT(spu_opcode_t op) //
|
|
{
|
|
flush();
|
|
const auto cond = eval(extract(get_vr<s32[4]>(op.ra), 3) > extract(get_vr<s32[4]>(op.rb), 3));
|
|
const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
const auto halt = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
m_ir->CreateCondBr(cond.value, halt, next);
|
|
m_ir->SetInsertPoint(halt);
|
|
make_halt(next);
|
|
m_ir->SetInsertPoint(next);
|
|
}
|
|
|
|
void HEQ(spu_opcode_t op) //
|
|
{
|
|
flush();
|
|
const auto cond = eval(extract(get_vr(op.ra), 3) == extract(get_vr(op.rb), 3));
|
|
const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
const auto halt = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
m_ir->CreateCondBr(cond.value, halt, next);
|
|
m_ir->SetInsertPoint(halt);
|
|
make_halt(next);
|
|
m_ir->SetInsertPoint(next);
|
|
}
|
|
|
|
void HLGT(spu_opcode_t op) //
|
|
{
|
|
flush();
|
|
const auto cond = eval(extract(get_vr(op.ra), 3) > extract(get_vr(op.rb), 3));
|
|
const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
const auto halt = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
m_ir->CreateCondBr(cond.value, halt, next);
|
|
m_ir->SetInsertPoint(halt);
|
|
make_halt(next);
|
|
m_ir->SetInsertPoint(next);
|
|
}
|
|
|
|
void HGTI(spu_opcode_t op) //
|
|
{
|
|
flush();
|
|
const auto cond = eval(extract(get_vr<s32[4]>(op.ra), 3) > op.si10);
|
|
const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
const auto halt = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
m_ir->CreateCondBr(cond.value, halt, next);
|
|
m_ir->SetInsertPoint(halt);
|
|
make_halt(next);
|
|
m_ir->SetInsertPoint(next);
|
|
}
|
|
|
|
void HEQI(spu_opcode_t op) //
|
|
{
|
|
flush();
|
|
const auto cond = eval(extract(get_vr(op.ra), 3) == op.si10);
|
|
const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
const auto halt = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
m_ir->CreateCondBr(cond.value, halt, next);
|
|
m_ir->SetInsertPoint(halt);
|
|
make_halt(next);
|
|
m_ir->SetInsertPoint(next);
|
|
}
|
|
|
|
void HLGTI(spu_opcode_t op) //
|
|
{
|
|
flush();
|
|
const auto cond = eval(extract(get_vr(op.ra), 3) > op.si10);
|
|
const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
const auto halt = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
m_ir->CreateCondBr(cond.value, halt, next);
|
|
m_ir->SetInsertPoint(halt);
|
|
make_halt(next);
|
|
m_ir->SetInsertPoint(next);
|
|
}
|
|
|
|
void HBR(spu_opcode_t op) //
|
|
{
|
|
// TODO: use the hint.
|
|
}
|
|
|
|
void HBRA(spu_opcode_t op) //
|
|
{
|
|
// TODO: use the hint.
|
|
}
|
|
|
|
void HBRR(spu_opcode_t op) //
|
|
{
|
|
// TODO: use the hint.
|
|
}
|
|
|
|
// TODO
|
|
static u32 exec_check_interrupts(SPUThread* _spu, u32 addr)
|
|
{
|
|
_spu->set_interrupt_status(true);
|
|
|
|
if ((_spu->ch_event_mask & _spu->ch_event_stat & SPU_EVENT_INTR_IMPLEMENTED) > 0)
|
|
{
|
|
_spu->interrupts_enabled = false;
|
|
_spu->srr0 = addr;
|
|
return 0;
|
|
}
|
|
|
|
return addr;
|
|
}
|
|
|
|
void branch_indirect(spu_opcode_t op, value_t<u32> addr)
|
|
{
|
|
if (op.d)
|
|
{
|
|
m_ir->CreateStore(m_ir->getFalse(), spu_ptr<bool>(&SPUThread::interrupts_enabled))->setVolatile(true);
|
|
}
|
|
else if (op.e)
|
|
{
|
|
addr.value = call(&exec_check_interrupts, m_thread, addr.value);
|
|
}
|
|
|
|
if (llvm::isa<llvm::ConstantInt>(addr.value))
|
|
{
|
|
return branch_fixed(llvm::cast<llvm::ConstantInt>(addr.value)->getZExtValue());
|
|
}
|
|
|
|
m_ir->CreateStore(addr.value, spu_ptr<u32>(&SPUThread::pc));
|
|
|
|
const u32 start = m_instr_map.begin()->first;
|
|
const auto local = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
const auto exter = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
const auto off = m_ir->CreateSub(addr.value, m_ir->getInt32(start));
|
|
m_ir->CreateCondBr(m_ir->CreateICmpULT(off, m_ir->getInt32(m_size)), local, exter);
|
|
m_ir->SetInsertPoint(local);
|
|
const auto table = m_ir->CreateIndirectBr(m_ir->CreateLoad(m_ir->CreateGEP(m_jt, {(llvm::Value*)m_ir->getInt32(0), m_ir->CreateLShr(off, 2)})), m_instr_map.size() + 1);
|
|
for (const auto& pair : m_instr_map)
|
|
table->addDestination(pair.second);
|
|
table->addDestination(m_stop);
|
|
m_ir->SetInsertPoint(exter);
|
|
const auto disp = m_ir->CreateAdd(m_thread, m_ir->getInt64(::offset32(&SPUThread::jit_dispatcher)));
|
|
const auto type = llvm::FunctionType::get(get_type<void>(), {get_type<u64>(), get_type<u64>(), get_type<u32>()}, false)->getPointerTo()->getPointerTo();
|
|
tail(m_ir->CreateLoad(m_ir->CreateIntToPtr(m_ir->CreateAdd(disp, zext<u64>(addr << 1).value), type)));
|
|
}
|
|
|
|
void branch_fixed(u32 target)
|
|
{
|
|
m_ir->CreateStore(m_ir->getInt32(target), spu_ptr<u32>(&SPUThread::pc));
|
|
|
|
const auto found = m_instr_map.find(target);
|
|
|
|
if (found != m_instr_map.end())
|
|
{
|
|
m_ir->CreateCondBr(m_ir->CreateICmpNE(m_ir->CreateLoad(spu_ptr<u32>(&SPUThread::state)), m_ir->getInt32(0)), m_stop, found->second);
|
|
return;
|
|
}
|
|
|
|
const auto addr = m_ir->CreateAdd(m_thread, m_ir->getInt64(::offset32(&SPUThread::jit_dispatcher) + target * 2));
|
|
const auto type = llvm::FunctionType::get(get_type<void>(), {get_type<u64>(), get_type<u64>(), get_type<u32>()}, false)->getPointerTo()->getPointerTo();
|
|
const auto func = m_ir->CreateLoad(m_ir->CreateIntToPtr(addr, type));
|
|
tail(func);
|
|
}
|
|
|
|
void BIZ(spu_opcode_t op) //
|
|
{
|
|
flush();
|
|
const auto cond = eval(extract(get_vr(op.rt), 3) == 0);
|
|
const auto addr = eval(extract(get_vr(op.ra), 3) & 0x3fffc);
|
|
const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
const auto jump = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
m_ir->CreateCondBr(cond.value, jump, next);
|
|
m_ir->SetInsertPoint(jump);
|
|
branch_indirect(op, addr);
|
|
m_ir->SetInsertPoint(next);
|
|
}
|
|
|
|
void BINZ(spu_opcode_t op) //
|
|
{
|
|
flush();
|
|
const auto cond = eval(extract(get_vr(op.rt), 3) != 0);
|
|
const auto addr = eval(extract(get_vr(op.ra), 3) & 0x3fffc);
|
|
const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
const auto jump = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
m_ir->CreateCondBr(cond.value, jump, next);
|
|
m_ir->SetInsertPoint(jump);
|
|
branch_indirect(op, addr);
|
|
m_ir->SetInsertPoint(next);
|
|
}
|
|
|
|
void BIHZ(spu_opcode_t op) //
|
|
{
|
|
flush();
|
|
const auto cond = eval(extract(get_vr<u16[8]>(op.rt), 6) == 0);
|
|
const auto addr = eval(extract(get_vr(op.ra), 3) & 0x3fffc);
|
|
const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
const auto jump = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
m_ir->CreateCondBr(cond.value, jump, next);
|
|
m_ir->SetInsertPoint(jump);
|
|
branch_indirect(op, addr);
|
|
m_ir->SetInsertPoint(next);
|
|
}
|
|
|
|
void BIHNZ(spu_opcode_t op) //
|
|
{
|
|
flush();
|
|
const auto cond = eval(extract(get_vr<u16[8]>(op.rt), 6) != 0);
|
|
const auto addr = eval(extract(get_vr(op.ra), 3) & 0x3fffc);
|
|
const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
const auto jump = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
m_ir->CreateCondBr(cond.value, jump, next);
|
|
m_ir->SetInsertPoint(jump);
|
|
branch_indirect(op, addr);
|
|
m_ir->SetInsertPoint(next);
|
|
}
|
|
|
|
void BI(spu_opcode_t op) //
|
|
{
|
|
const auto addr = eval(extract(get_vr(op.ra), 3) & 0x3fffc);
|
|
flush();
|
|
branch_indirect(op, addr);
|
|
}
|
|
|
|
void BISL(spu_opcode_t op) //
|
|
{
|
|
const auto addr = eval(extract(get_vr(op.ra), 3) & 0x3fffc);
|
|
u32 values[4]{0, 0, 0, spu_branch_target(m_pos + 4)};
|
|
value_t<u32[4]> r;
|
|
r.value = llvm::ConstantDataVector::get(m_context, values);
|
|
set_vr(op.rt, r);
|
|
flush();
|
|
branch_indirect(op, addr);
|
|
}
|
|
|
|
void IRET(spu_opcode_t op) //
|
|
{
|
|
value_t<u32> srr0;
|
|
srr0.value = m_ir->CreateLoad(spu_ptr<u32>(&SPUThread::srr0));
|
|
flush();
|
|
branch_indirect(op, srr0);
|
|
}
|
|
|
|
void BISLED(spu_opcode_t op) //
|
|
{
|
|
UNK(op);
|
|
}
|
|
|
|
void BRZ(spu_opcode_t op) //
|
|
{
|
|
const u32 target = spu_branch_target(m_pos, op.i16);
|
|
|
|
if (target == m_pos + 4)
|
|
{
|
|
return;
|
|
}
|
|
|
|
flush();
|
|
const auto cond = eval(extract(get_vr(op.rt), 3) == 0);
|
|
const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
const auto jump = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
m_ir->CreateCondBr(cond.value, jump, next);
|
|
m_ir->SetInsertPoint(jump);
|
|
branch_fixed(target);
|
|
m_ir->SetInsertPoint(next);
|
|
}
|
|
|
|
void BRNZ(spu_opcode_t op) //
|
|
{
|
|
const u32 target = spu_branch_target(m_pos, op.i16);
|
|
|
|
if (target == m_pos + 4)
|
|
{
|
|
return;
|
|
}
|
|
|
|
flush();
|
|
const auto cond = eval(extract(get_vr(op.rt), 3) != 0);
|
|
const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
const auto jump = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
m_ir->CreateCondBr(cond.value, jump, next);
|
|
m_ir->SetInsertPoint(jump);
|
|
branch_fixed(target);
|
|
m_ir->SetInsertPoint(next);
|
|
}
|
|
|
|
void BRHZ(spu_opcode_t op) //
|
|
{
|
|
const u32 target = spu_branch_target(m_pos, op.i16);
|
|
|
|
if (target == m_pos + 4)
|
|
{
|
|
return;
|
|
}
|
|
|
|
flush();
|
|
const auto cond = eval(extract(get_vr<u16[8]>(op.rt), 6) == 0);
|
|
const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
const auto jump = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
m_ir->CreateCondBr(cond.value, jump, next);
|
|
m_ir->SetInsertPoint(jump);
|
|
branch_fixed(target);
|
|
m_ir->SetInsertPoint(next);
|
|
}
|
|
|
|
void BRHNZ(spu_opcode_t op) //
|
|
{
|
|
const u32 target = spu_branch_target(m_pos, op.i16);
|
|
|
|
if (target == m_pos + 4)
|
|
{
|
|
return;
|
|
}
|
|
|
|
flush();
|
|
const auto cond = eval(extract(get_vr<u16[8]>(op.rt), 6) != 0);
|
|
const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
const auto jump = llvm::BasicBlock::Create(m_context, "", m_function);
|
|
m_ir->CreateCondBr(cond.value, jump, next);
|
|
m_ir->SetInsertPoint(jump);
|
|
branch_fixed(target);
|
|
m_ir->SetInsertPoint(next);
|
|
}
|
|
|
|
void BRA(spu_opcode_t op) //
|
|
{
|
|
const u32 target = spu_branch_target(0, op.i16);
|
|
|
|
if (target != m_pos + 4)
|
|
{
|
|
flush();
|
|
branch_fixed(target);
|
|
}
|
|
}
|
|
|
|
void BRASL(spu_opcode_t op) //
|
|
{
|
|
u32 values[4]{0, 0, 0, spu_branch_target(m_pos + 4)};
|
|
value_t<u32[4]> r;
|
|
r.value = llvm::ConstantDataVector::get(m_context, values);
|
|
set_vr(op.rt, r);
|
|
BRA(op);
|
|
}
|
|
|
|
void BR(spu_opcode_t op) //
|
|
{
|
|
const u32 target = spu_branch_target(m_pos, op.i16);
|
|
|
|
if (target != m_pos + 4)
|
|
{
|
|
flush();
|
|
branch_fixed(target);
|
|
}
|
|
}
|
|
|
|
void BRSL(spu_opcode_t op) //
|
|
{
|
|
u32 values[4]{0, 0, 0, spu_branch_target(m_pos + 4)};
|
|
value_t<u32[4]> r;
|
|
r.value = llvm::ConstantDataVector::get(m_context, values);
|
|
set_vr(op.rt, r);
|
|
BR(op);
|
|
}
|
|
|
|
static const spu_decoder<spu_llvm_recompiler> g_decoder;
|
|
};
|
|
|
|
std::unique_ptr<spu_recompiler_base> spu_recompiler_base::make_llvm_recompiler()
|
|
{
|
|
return std::make_unique<spu_llvm_recompiler>();
|
|
}
|
|
|
|
DECLARE(spu_llvm_recompiler::g_decoder);
|