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https://github.com/RPCS3/rpcs3.git
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879 lines
31 KiB
C++
879 lines
31 KiB
C++
#pragma once
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namespace PPU_opcodes
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{
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enum PPU_MainOpcodes
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{
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TDI = 0x02, //Trap Doubleword Immediate
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TWI = 0x03, //Trap Word Immediate
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G_04 = 0x04,
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MULLI = 0x07, //Multiply Low Immediate
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SUBFIC = 0x08, //Subtract from Immediate Carrying
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//DOZI = 0x09,
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CMPLI = 0x0a, //Compare Logical Immediate
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CMPI = 0x0b, //Compare Immediate
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ADDIC = 0x0c, //Add Immediate Carrying
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ADDIC_ = 0x0d, //Add Immediate Carrying and Record
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ADDI = 0x0e, //Add Immediate
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ADDIS = 0x0f, //Add Immediate Shifted
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BC = 0x10, //Branch Conditional
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SC = 0x11, //System Call
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B = 0x12, //Branch
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G_13 = 0x13,
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RLWIMI = 0x14, //Rotate Left Word Immediate then Mask Insert
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RLWINM = 0x15, //Rotate Left Word Immediate then AND with Mask
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RLWNM = 0x17, //Rotate Left Word then AND with Mask
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ORI = 0x18, //OR Immediate
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ORIS = 0x19, //OR Immediate Shifted
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XORI = 0x1a, //XOR Immediate
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XORIS = 0x1b, //XOR Immediate Shifted
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ANDI_ = 0x1c, //AND Immediate
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ANDIS_ = 0x1d, //AND Immediate Shifted
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G_1e = 0x1e,
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G_1f = 0x1f,
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LWZ = 0x20, //Load Word and Zero Indexed
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LWZU = 0x21, //Load Word and Zero with Update Indexed
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LBZ = 0x22, //Load Byte and Zero
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LBZU = 0x23, //Load Byte and Zero with Update
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STW = 0x24, //Store Word
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STWU = 0x25, //Store Word with Update
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STB = 0x26, //Store Byte
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STBU = 0x27, //Store Byte with Update
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LHZ = 0x28, //Load Halfword and Zero
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LHZU = 0x29, //Load Halfword and Zero with Update
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LHA = 0x2a, //Load Halfword Algebraic with Update
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LHAU = 0x2b, //Load Halfword Algebraic
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STH = 0x2c, //Store Halfword
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STHU = 0x2d, //Store Halfword with Update
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LMW = 0x2e, //Load Multiple Word
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STMW = 0x2f, //Store Multiple Word
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LFS = 0x30, //Load Floating-Point Single
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LFSU = 0x31, //Load Floating-Point Single with Update
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LFD = 0x32, //Load Floating-Point Double
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LFDU = 0x33, //Load Floating-Point Double with Update
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STFS = 0x34, //Store Floating-Point Single
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STFSU = 0x35, //Store Floating-Point Single with Update
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STFD = 0x36, //Store Floating-Point Double
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STFDU = 0x37, //Store Floating-Point Double with Update
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LFQ = 0x38, //
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LFQU = 0x39, //
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G_3a = 0x3a,
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G_3b = 0x3b,
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G_3e = 0x3e,
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G_3f = 0x3f,
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};
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enum G_04Opcodes
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{
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VADDUBM = 0x0,
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VMAXUB = 0x2,
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VRLB = 0x4,
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VCMPEQUB = 0x6,
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VMULOUB = 0x8,
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VADDFP = 0xa,
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VMRGHB = 0xc,
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VPKUHUM = 0xe,
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VADDUHM = 0x40,
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VMAXUH = 0x42,
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VRLH = 0x44,
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VCMPEQUH = 0x46,
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VMULOUH = 0x48,
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VSUBFP = 0x4a,
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VMRGHH = 0x4c,
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VPKUWUM = 0x4e,
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VADDUWM = 0x80,
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VMAXUW = 0x82,
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VRLW = 0x84,
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VCMPEQUW = 0x86,
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VMRGHW = 0x8c,
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VPKUHUS = 0x8e,
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VCMPEQFP = 0xc6,
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VPKUWUS = 0xce,
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VMAXSB = 0x102,
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VSLB = 0x104,
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VMULOSB = 0x108,
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VREFP = 0x10a,
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VMRGLB = 0x10c,
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VPKSHUS = 0x10e,
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VMAXSH = 0x142,
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VSLH = 0x144,
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VMULOSH = 0x148,
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VRSQRTEFP = 0x14a,
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VMRGLH = 0x14c,
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VPKSWUS = 0x14e,
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VADDCUW = 0x180,
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VMAXSW = 0x182,
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VSLW = 0x184,
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VEXPTEFP = 0x18a,
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VMRGLW = 0x18c,
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VPKSHSS = 0x18e,
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VSL = 0x1c4,
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VCMPGEFP = 0x1c6,
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VLOGEFP = 0x1ca,
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VPKSWSS = 0x1ce,
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VADDUBS = 0x200,
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VMINUB = 0x202,
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VSRB = 0x204,
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VCMPGTUB = 0x206,
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VMULEUB = 0x208,
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VRFIN = 0x20a,
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VSPLTB = 0x20c,
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VUPKHSB = 0x20e,
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VADDUHS = 0x240,
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VMINUH = 0x242,
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VSRH = 0x244,
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VCMPGTUH = 0x246,
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VMULEUH = 0x248,
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VRFIZ = 0x24a,
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VSPLTH = 0x24c,
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VUPKHSH = 0x24e,
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VADDUWS = 0x280,
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VMINUW = 0x282,
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VSRW = 0x284,
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VCMPGTUW = 0x286,
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VRFIP = 0x28a,
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VSPLTW = 0x28c,
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VUPKLSB = 0x28e,
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VSR = 0x2c4,
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VCMPGTFP = 0x2c6,
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VRFIM = 0x2ca,
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VUPKLSH = 0x2ce,
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VADDSBS = 0x300,
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VMINSB = 0x302,
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VSRAB = 0x304,
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VCMPGTSB = 0x306,
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VMULESB = 0x308,
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VCFUX = 0x30a,
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VSPLTISB = 0x30c,
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VPKPX = 0x30e,
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VADDSHS = 0x340,
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VMINSH = 0x342,
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VSRAH = 0x344,
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VCMPGTSH = 0x346,
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VMULESH = 0x348,
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VCFSX = 0x34a,
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VSPLTISH = 0x34c,
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VUPKHPX = 0x34e,
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VADDSWS = 0x380,
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VMINSW = 0x382,
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VSRAW = 0x384,
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VCMPGTSW = 0x386,
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VCTUXS = 0x38a,
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VSPLTISW = 0x38c,
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VCMPBFP = 0x3c6,
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VCTSXS = 0x3ca,
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VUPKLPX = 0x3ce,
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VSUBUBM = 0x400,
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VAVGUB = 0x402,
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VAND = 0x404,
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VCMPEQUB_ = 0x406,
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VMAXFP = 0x40a,
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VSLO = 0x40c,
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VSUBUHM = 0x440,
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VAVGUH = 0x442,
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VANDC = 0x444,
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VCMPEQUH_ = 0x446,
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VMINFP = 0x44a,
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VSRO = 0x44c,
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VSUBUWM = 0x480,
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VAVGUW = 0x482,
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VOR = 0x484,
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VCMPEQUW_ = 0x486,
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VXOR = 0x4c4,
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VCMPEQFP_ = 0x4c6,
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VAVGSB = 0x502,
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VNOR = 0x504,
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VAVGSH = 0x542,
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VSUBCUW = 0x580,
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VAVGSW = 0x582,
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VCMPGEFP_ = 0x5c6,
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VSUBUBS = 0x600,
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MFVSCR = 0x604,
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VCMPGTUB_ = 0x606,
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VSUM4UBS = 0x608,
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VSUBUHS = 0x640,
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MTVSCR = 0x644,
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VCMPGTUH_ = 0x646,
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VSUM4SHS = 0x648,
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VSUBUWS = 0x680,
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VCMPGTUW_ = 0x686,
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VSUM2SWS = 0x688,
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VCMPGTFP_ = 0x6c6,
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VSUBSBS = 0x700,
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VCMPGTSB_ = 0x706,
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VSUM4SBS = 0x708,
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VSUBSHS = 0x740,
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VCMPGTSH_ = 0x746,
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VSUBSWS = 0x780,
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VCMPGTSW_ = 0x786,
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VSUMSWS = 0x788,
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VCMPBFP_ = 0x7c6,
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};
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enum G_04_VA_Opcodes
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{
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VMHADDSHS = 0x20,
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VMHRADDSHS = 0x21,
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VMLADDUHM = 0x22,
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VMSUMUBM = 0x24,
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VMSUMMBM = 0x25,
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VMSUMUHM = 0x26,
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VMSUMUHS = 0x27,
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VMSUMSHM = 0x28,
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VMSUMSHS = 0x29,
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VSEL = 0x2a,
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VPERM = 0x2b,
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VSLDOI = 0x2c,
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VMADDFP = 0x2e,
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VNMSUBFP = 0x2f,
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};
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enum G_13Opcodes //Field 21 - 30
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{
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MCRF = 0x000,
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BCLR = 0x010,
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CRNOR = 0x021,
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CRANDC = 0x081,
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ISYNC = 0x096,
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CRXOR = 0x0c1,
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CRNAND = 0x0e1,
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CRAND = 0x101,
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CREQV = 0x121,
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CRORC = 0x1a1,
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CROR = 0x1c1,
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BCCTR = 0x210,
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};
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enum G_1eOpcodes //Field 27 - 29
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{
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RLDICL = 0x0,
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RLDICR = 0x1,
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RLDIC = 0x2,
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RLDIMI = 0x3,
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RLDC_LR = 0x4,
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};
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enum G_1fOpcodes //Field 21 - 30
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{
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CMP = 0x000,
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TW = 0x004,
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LVSL = 0x006, //Load Vector for Shift Left
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LVEBX = 0x007, //Load Vector Element Byte Indexed
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SUBFC = 0x008, //Subtract from Carrying
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MULHDU = 0x009,
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ADDC = 0x00a,
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MULHWU = 0x00b,
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MFOCRF = 0x013,
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LWARX = 0x014,
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LDX = 0x015,
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LWZX = 0x017,
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SLW = 0x018,
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CNTLZW = 0x01a,
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SLD = 0x01b,
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AND = 0x01c,
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CMPL = 0x020,
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LVSR = 0x026, //Load Vector for Shift Right
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LVEHX = 0x027, //Load Vector Element Halfword Indexed
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SUBF = 0x028,
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LDUX = 0x035, //Load Doubleword with Update Indexed
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DCBST = 0x036, //Data Cache Block Store
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LWZUX = 0x037,
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CNTLZD = 0x03a,
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ANDC = 0x03c,
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TD = 0x044,
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LVEWX = 0x047, //Load Vector Element Word Indexed
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MULHD = 0x049,
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MULHW = 0x04b,
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LDARX = 0x054,
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DCBF = 0x056, //Data Cache Block Flush
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LBZX = 0x057,
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LVX = 0x067, //Load Vector Indexed
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NEG = 0x068,
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LBZUX = 0x077,
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NOR = 0x07c,
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STVEBX = 0x087, //Store Vector Element Byte Indexed
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SUBFE = 0x088, //Subtract from Extended
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ADDE = 0x08a,
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MTOCRF = 0x090,
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STDX = 0x095,
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STWCX_ = 0x096,
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STWX = 0x097,
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STVEHX = 0x0a7, //Store Vector Element Halfword Indexed
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STDUX = 0x0b5,
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STWUX = 0x0b7,
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STVEWX = 0x0c7, //Store Vector Element Word Indexed
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SUBFZE = 0x0c8,
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ADDZE = 0x0ca,
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STDCX_ = 0x0d6,
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STBX = 0x0d7,
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STVX = 0x0e7,
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SUBFME = 0x0e8,
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MULLD = 0x0e9,
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ADDME = 0x0ea,
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MULLW = 0x0eb,
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DCBTST = 0x0f6, //Data Cache Block Touch for Store
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STBUX = 0x0f7,
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DOZ = 0x108,
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ADD = 0x10a,
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DCBT = 0x116, //Data Cache Block Touch
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LHZX = 0x117,
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EQV = 0x11c,
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ECIWX = 0x136,
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LHZUX = 0x137,
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XOR = 0x13c,
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MFSPR = 0x153,
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LWAX = 0x155,
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DST = 0x156, //Data Stream Touch
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LHAX = 0x157,
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LVXL = 0x167, //Load Vector Indexed Last
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MFTB = 0x173,
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LWAUX = 0x175,
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DSTST = 0x176, //Data Stream Touch for Store
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LHAUX = 0x177,
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STHX = 0x197, //Store Halfword Indexed
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ORC = 0x19c, //OR with Complement
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ECOWX = 0x1b6,
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STHUX = 0x1b7,
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OR = 0x1bc,
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DIVDU = 0x1c9,
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DIVWU = 0x1cb,
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MTSPR = 0x1d3,
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DCBI = 0x1d6, //Data Cache Block Invalidate
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NAND = 0x1dc,
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STVXL = 0x1e7, //Store Vector Indexed Last
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DIVD = 0x1e9,
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DIVW = 0x1eb,
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LVLX = 0x207, //Load Vector Left Indexed
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SUBFCO = 0x208,
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ADDCO = 0x20a,
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LDBRX = 0x214,
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LSWX = 0x215,
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LWBRX = 0x216,
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LFSX = 0x217,
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SRW = 0x218,
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SRD = 0x21b,
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LVRX = 0x227, //Load Vector Right Indexed
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SUBFO = 0x228,
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LFSUX = 0x237,
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LSWI = 0x255,
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SYNC = 0x256,
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LFDX = 0x257,
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NEGO = 0x268,
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LFDUX = 0x277,
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STVLX = 0x287, //Store Vector Left Indexed
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SUBFEO = 0x288,
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ADDEO = 0x28a,
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STDBRX = 0x294,
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STSWX = 0x295,
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STWBRX = 0x296,
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STFSX = 0x297,
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STVRX = 0x2a7, //Store Vector Right Indexed
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STFSUX = 0x2b7,
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SUBFZEO= 0x2c8,
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ADDZEO = 0x2ca,
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STSWI = 0x2d5,
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STFDX = 0x2d7, //Store Floating-Point Double Indexed
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SUBFMEO= 0x2e8,
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MULLDO = 0x2e9,
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ADDMEO = 0x2ea,
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MULLWO = 0x2eb,
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STFDUX = 0x2f7,
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LVLXL = 0x307, //Load Vector Left Indexed Last
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ADDO = 0x30a,
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LHBRX = 0x316,
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SRAW = 0x318,
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SRAD = 0x31a,
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LVRXL = 0x327, //Load Vector Right Indexed Last
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DSS = 0x336, //Data Stream Stop
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SRAWI = 0x338,
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SRADI1 = 0x33a, //sh_5 == 0
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SRADI2 = 0x33b, //sh_5 != 0
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EIEIO = 0x356,
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STVLXL = 0x387, //Store Vector Left Indexed Last
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STHBRX = 0x396,
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EXTSH = 0x39a,
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STVRXL = 0x3a7, //Store Vector Right Indexed Last
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EXTSB = 0x3ba,
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DIVDUO = 0x3c9,
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DIVWUO = 0x3cb,
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STFIWX = 0x3d7,
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EXTSW = 0x3da,
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ICBI = 0x3d6, //Instruction Cache Block Invalidate
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DIVDO = 0x3e9,
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DIVWO = 0x3eb,
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DCBZ = 0x3f6, //Data Cache Block Set to Zero
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};
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enum G_3aOpcodes //Field 30 - 31
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{
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LD = 0x0,
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LDU = 0x1,
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LWA = 0x2,
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};
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enum G_3bOpcodes //Field 26 - 30
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{
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FDIVS = 0x12,
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FSUBS = 0x14,
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FADDS = 0x15,
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FSQRTS = 0x16,
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FRES = 0x18,
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FMULS = 0x19,
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FMSUBS = 0x1c,
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FMADDS = 0x1d,
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FNMSUBS = 0x1e,
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FNMADDS = 0x1f,
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};
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enum G_3eOpcodes //Field 30 - 31
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{
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STD = 0x0,
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STDU = 0x1,
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};
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enum G_3fOpcodes //Field 21 - 30
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{
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MTFSB1 = 0x026,
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MCRFS = 0x040,
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MTFSB0 = 0x046,
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MTFSFI = 0x086,
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MFFS = 0x247,
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MTFSF = 0x2c7,
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FCMPU = 0x000,
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FRSP = 0x00c,
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FCTIW = 0x00e,
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FCTIWZ = 0x00f,
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FDIV = 0x012,
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FSUB = 0x014,
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FADD = 0x015,
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FSQRT = 0x016,
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FSEL = 0x017,
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FMUL = 0x019,
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FRSQRTE = 0x01a,
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FMSUB = 0x01c,
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FMADD = 0x01d,
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FNMSUB = 0x01e,
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FNMADD = 0x01f,
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FCMPO = 0x020,
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FNEG = 0x028,
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FMR = 0x048,
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FNABS = 0x088,
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FABS = 0x108,
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FCTID = 0x32e,
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FCTIDZ = 0x32f,
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FCFID = 0x34e,
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};
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}
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class PPUOpcodes
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{
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public:
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virtual ~PPUOpcodes() {}
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|
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static u32 branchTarget(const u32 pc, const u32 imm)
|
|
{
|
|
return pc + (imm & ~0x3ULL);
|
|
}
|
|
|
|
virtual void NULL_OP() = 0;
|
|
virtual void NOP() = 0;
|
|
|
|
virtual void TDI(u32 to, u32 ra, s32 simm16) = 0;
|
|
virtual void TWI(u32 to, u32 ra, s32 simm16) = 0;
|
|
|
|
virtual void MFVSCR(u32 vd) = 0;
|
|
virtual void MTVSCR(u32 vb) = 0;
|
|
virtual void VADDCUW(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VADDFP(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VADDSBS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VADDSHS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VADDSWS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VADDUBM(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VADDUBS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VADDUHM(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VADDUHS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VADDUWM(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VADDUWS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VAND(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VANDC(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VAVGSB(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VAVGSH(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VAVGSW(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VAVGUB(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VAVGUH(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VAVGUW(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCFSX(u32 vd, u32 uimm5, u32 vb) = 0;
|
|
virtual void VCFUX(u32 vd, u32 uimm5, u32 vb) = 0;
|
|
virtual void VCMPBFP(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPBFP_(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPEQFP(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPEQFP_(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPEQUB(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPEQUB_(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPEQUH(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPEQUH_(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPEQUW(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPEQUW_(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPGEFP(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPGEFP_(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPGTFP(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPGTFP_(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPGTSB(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPGTSB_(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPGTSH(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPGTSH_(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPGTSW(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPGTSW_(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPGTUB(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPGTUB_(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPGTUH(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPGTUH_(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPGTUW(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCMPGTUW_(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VCTSXS(u32 vd, u32 uimm5, u32 vb) = 0;
|
|
virtual void VCTUXS(u32 vd, u32 uimm5, u32 vb) = 0;
|
|
virtual void VEXPTEFP(u32 vd, u32 vb) = 0;
|
|
virtual void VLOGEFP(u32 vd, u32 vb) = 0;
|
|
virtual void VMADDFP(u32 vd, u32 va, u32 vc, u32 vb) = 0;
|
|
virtual void VMAXFP(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMAXSB(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMAXSH(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMAXSW(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMAXUB(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMAXUH(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMAXUW(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMHADDSHS(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
|
virtual void VMHRADDSHS(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
|
virtual void VMINFP(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMINSB(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMINSH(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMINSW(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMINUB(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMINUH(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMINUW(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMLADDUHM(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
|
virtual void VMRGHB(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMRGHH(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMRGHW(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMRGLB(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMRGLH(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMRGLW(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMSUMMBM(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
|
virtual void VMSUMSHM(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
|
virtual void VMSUMSHS(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
|
virtual void VMSUMUBM(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
|
virtual void VMSUMUHM(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
|
virtual void VMSUMUHS(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
|
virtual void VMULESB(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMULESH(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMULEUB(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMULEUH(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMULOSB(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMULOSH(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMULOUB(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VMULOUH(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VNMSUBFP(u32 vd, u32 va, u32 vc, u32 vb) = 0;
|
|
virtual void VNOR(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VOR(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VPERM(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
|
virtual void VPKPX(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VPKSHSS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VPKSHUS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VPKSWSS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VPKSWUS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VPKUHUM(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VPKUHUS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VPKUWUM(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VPKUWUS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VREFP(u32 vd, u32 vb) = 0;
|
|
virtual void VRFIM(u32 vd, u32 vb) = 0;
|
|
virtual void VRFIN(u32 vd, u32 vb) = 0;
|
|
virtual void VRFIP(u32 vd, u32 vb) = 0;
|
|
virtual void VRFIZ(u32 vd, u32 vb) = 0;
|
|
virtual void VRLB(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VRLH(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VRLW(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VRSQRTEFP(u32 vd, u32 vb) = 0;
|
|
virtual void VSEL(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
|
virtual void VSL(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSLB(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSLDOI(u32 vd, u32 va, u32 vb, u32 sh) = 0;
|
|
virtual void VSLH(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSLO(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSLW(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSPLTB(u32 vd, u32 uimm5, u32 vb) = 0;
|
|
virtual void VSPLTH(u32 vd, u32 uimm5, u32 vb) = 0;
|
|
virtual void VSPLTISB(u32 vd, s32 simm5) = 0;
|
|
virtual void VSPLTISH(u32 vd, s32 simm5) = 0;
|
|
virtual void VSPLTISW(u32 vd, s32 simm5) = 0;
|
|
virtual void VSPLTW(u32 vd, u32 uimm5, u32 vb) = 0;
|
|
virtual void VSR(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSRAB(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSRAH(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSRAW(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSRB(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSRH(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSRO(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSRW(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSUBCUW(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSUBFP(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSUBSBS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSUBSHS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSUBSWS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSUBUBM(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSUBUBS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSUBUHM(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSUBUHS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSUBUWM(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSUBUWS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSUMSWS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSUM2SWS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSUM4SBS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSUM4SHS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VSUM4UBS(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void VUPKHPX(u32 vd, u32 vb) = 0;
|
|
virtual void VUPKHSB(u32 vd, u32 vb) = 0;
|
|
virtual void VUPKHSH(u32 vd, u32 vb) = 0;
|
|
virtual void VUPKLPX(u32 vd, u32 vb) = 0;
|
|
virtual void VUPKLSB(u32 vd, u32 vb) = 0;
|
|
virtual void VUPKLSH(u32 vd, u32 vb) = 0;
|
|
virtual void VXOR(u32 vd, u32 va, u32 vb) = 0;
|
|
virtual void MULLI(u32 rd, u32 ra, s32 simm16) = 0;
|
|
virtual void SUBFIC(u32 rd, u32 ra, s32 simm16) = 0;
|
|
virtual void CMPLI(u32 bf, u32 l, u32 ra, u32 uimm16) = 0;
|
|
virtual void CMPI(u32 bf, u32 l, u32 ra, s32 simm16) = 0;
|
|
virtual void ADDIC(u32 rd, u32 ra, s32 simm16) = 0;
|
|
virtual void ADDIC_(u32 rd, u32 ra, s32 simm16) = 0;
|
|
virtual void ADDI(u32 rd, u32 ra, s32 simm16) = 0;
|
|
virtual void ADDIS(u32 rd, u32 ra, s32 simm16) = 0;
|
|
virtual void BC(u32 bo, u32 bi, s32 bd, u32 aa, u32 lk) = 0;
|
|
virtual void SC(u32 lev) = 0;
|
|
virtual void B(s32 ll, u32 aa, u32 lk) = 0;
|
|
virtual void MCRF(u32 crfd, u32 crfs) = 0;
|
|
virtual void BCLR(u32 bo, u32 bi, u32 bh, u32 lk) = 0;
|
|
virtual void CRNOR(u32 bt, u32 ba, u32 bb) = 0;
|
|
virtual void CRANDC(u32 bt, u32 ba, u32 bb) = 0;
|
|
virtual void ISYNC() = 0;
|
|
virtual void CRXOR(u32 bt, u32 ba, u32 bb) = 0;
|
|
virtual void CRNAND(u32 bt, u32 ba, u32 bb) = 0;
|
|
virtual void CRAND(u32 bt, u32 ba, u32 bb) = 0;
|
|
virtual void CREQV(u32 bt, u32 ba, u32 bb) = 0;
|
|
virtual void CRORC(u32 bt, u32 ba, u32 bb) = 0;
|
|
virtual void CROR(u32 bt, u32 ba, u32 bb) = 0;
|
|
virtual void BCCTR(u32 bo, u32 bi, u32 bh, u32 lk) = 0;
|
|
virtual void RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) = 0;
|
|
virtual void RLWINM(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) = 0;
|
|
virtual void RLWNM(u32 ra, u32 rs, u32 rb, u32 MB, u32 ME, bool rc) = 0;
|
|
virtual void ORI(u32 rs, u32 ra, u32 uimm16) = 0;
|
|
virtual void ORIS(u32 rs, u32 ra, u32 uimm16) = 0;
|
|
virtual void XORI(u32 ra, u32 rs, u32 uimm16) = 0;
|
|
virtual void XORIS(u32 ra, u32 rs, u32 uimm16) = 0;
|
|
virtual void ANDI_(u32 ra, u32 rs, u32 uimm16) = 0;
|
|
virtual void ANDIS_(u32 ra, u32 rs, u32 uimm16) = 0;
|
|
virtual void RLDICL(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) = 0;
|
|
virtual void RLDICR(u32 ra, u32 rs, u32 sh, u32 me, bool rc) = 0;
|
|
virtual void RLDIC(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) = 0;
|
|
virtual void RLDIMI(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) = 0;
|
|
virtual void RLDC_LR(u32 ra, u32 rs, u32 rb, u32 m_eb, bool is_r, bool rc) = 0;
|
|
virtual void CMP(u32 crfd, u32 l, u32 ra, u32 rb) = 0;
|
|
virtual void TW(u32 to, u32 ra, u32 rb) = 0;
|
|
virtual void LVSL(u32 vd, u32 ra, u32 rb) = 0;
|
|
virtual void LVEBX(u32 vd, u32 ra, u32 rb) = 0;
|
|
virtual void SUBFC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
|
|
virtual void MULHDU(u32 rd, u32 ra, u32 rb, bool rc) = 0;
|
|
virtual void ADDC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
|
|
virtual void MULHWU(u32 rd, u32 ra, u32 rb, bool rc) = 0;
|
|
virtual void MFOCRF(u32 a, u32 rd, u32 crm) = 0;
|
|
virtual void LWARX(u32 rd, u32 ra, u32 rb) = 0;
|
|
virtual void LDX(u32 ra, u32 rs, u32 rb) = 0;
|
|
virtual void LWZX(u32 rd, u32 ra, u32 rb) = 0;
|
|
virtual void SLW(u32 ra, u32 rs, u32 rb, bool rc) = 0;
|
|
virtual void CNTLZW(u32 ra, u32 rs, bool rc) = 0;
|
|
virtual void SLD(u32 ra, u32 rs, u32 rb, bool rc) = 0;
|
|
virtual void AND(u32 ra, u32 rs, u32 rb, bool rc) = 0;
|
|
virtual void CMPL(u32 bf, u32 l, u32 ra, u32 rb) = 0;
|
|
virtual void LVSR(u32 vd, u32 ra, u32 rb) = 0;
|
|
virtual void LVEHX(u32 vd, u32 ra, u32 rb) = 0;
|
|
virtual void SUBF(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
|
|
virtual void LDUX(u32 rd, u32 ra, u32 rb) = 0;
|
|
virtual void DCBST(u32 ra, u32 rb) = 0;
|
|
virtual void LWZUX(u32 rd, u32 ra, u32 rb) = 0;
|
|
virtual void CNTLZD(u32 ra, u32 rs, bool rc) = 0;
|
|
virtual void ANDC(u32 ra, u32 rs, u32 rb, bool rc) = 0;
|
|
virtual void TD(u32 to, u32 ra, u32 rb) = 0;
|
|
virtual void LVEWX(u32 vd, u32 ra, u32 rb) = 0;
|
|
virtual void MULHD(u32 rd, u32 ra, u32 rb, bool rc) = 0;
|
|
virtual void MULHW(u32 rd, u32 ra, u32 rb, bool rc) = 0;
|
|
virtual void LDARX(u32 rd, u32 ra, u32 rb) = 0;
|
|
virtual void DCBF(u32 ra, u32 rb) = 0;
|
|
virtual void LBZX(u32 rd, u32 ra, u32 rb) = 0;
|
|
virtual void LVX(u32 vd, u32 ra, u32 rb) = 0;
|
|
virtual void NEG(u32 rd, u32 ra, u32 oe, bool rc) = 0;
|
|
virtual void LBZUX(u32 rd, u32 ra, u32 rb) = 0;
|
|
virtual void NOR(u32 ra, u32 rs, u32 rb, bool rc) = 0;
|
|
virtual void STVEBX(u32 vs, u32 ra, u32 rb) = 0;
|
|
virtual void SUBFE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
|
|
virtual void ADDE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
|
|
virtual void MTOCRF(u32 l, u32 crm, u32 rs) = 0;
|
|
virtual void STDX(u32 rs, u32 ra, u32 rb) = 0;
|
|
virtual void STWCX_(u32 rs, u32 ra, u32 rb) = 0;
|
|
virtual void STWX(u32 rs, u32 ra, u32 rb) = 0;
|
|
virtual void STVEHX(u32 vs, u32 ra, u32 rb) = 0;
|
|
virtual void STDUX(u32 rs, u32 ra, u32 rb) = 0;
|
|
virtual void STWUX(u32 rs, u32 ra, u32 rb) = 0;
|
|
virtual void STVEWX(u32 vs, u32 ra, u32 rb) = 0;
|
|
virtual void SUBFZE(u32 rd, u32 ra, u32 oe, bool rc) = 0;
|
|
virtual void ADDZE(u32 rd, u32 ra, u32 oe, bool rc) = 0;
|
|
virtual void STDCX_(u32 rs, u32 ra, u32 rb) = 0;
|
|
virtual void STBX(u32 rs, u32 ra, u32 rb) = 0;
|
|
virtual void STVX(u32 vs, u32 ra, u32 rb) = 0;
|
|
virtual void MULLD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
|
|
virtual void SUBFME(u32 rd, u32 ra, u32 oe, bool rc) = 0;
|
|
virtual void ADDME(u32 rd, u32 ra, u32 oe, bool rc) = 0;
|
|
virtual void MULLW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
|
|
virtual void DCBTST(u32 ra, u32 rb, u32 th) = 0;
|
|
virtual void STBUX(u32 rs, u32 ra, u32 rb) = 0;
|
|
virtual void ADD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
|
|
virtual void DCBT(u32 ra, u32 rb, u32 th) = 0;
|
|
virtual void LHZX(u32 rd, u32 ra, u32 rb) = 0;
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virtual void EQV(u32 ra, u32 rs, u32 rb, bool rc) = 0;
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virtual void ECIWX(u32 rd, u32 ra, u32 rb) = 0;
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virtual void LHZUX(u32 rd, u32 ra, u32 rb) = 0;
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virtual void XOR(u32 rs, u32 ra, u32 rb, bool rc) = 0;
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virtual void MFSPR(u32 rd, u32 spr) = 0;
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virtual void LWAX(u32 rd, u32 ra, u32 rb) = 0;
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virtual void DST(u32 ra, u32 rb, u32 strm, u32 t) = 0;
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virtual void LHAX(u32 rd, u32 ra, u32 rb) = 0;
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virtual void LVXL(u32 vd, u32 ra, u32 rb) = 0;
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virtual void MFTB(u32 rd, u32 spr) = 0;
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virtual void LWAUX(u32 rd, u32 ra, u32 rb) = 0;
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virtual void DSTST(u32 ra, u32 rb, u32 strm, u32 t) = 0;
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virtual void LHAUX(u32 rd, u32 ra, u32 rb) = 0;
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virtual void STHX(u32 rs, u32 ra, u32 rb) = 0;
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virtual void ORC(u32 rs, u32 ra, u32 rb, bool rc) = 0;
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virtual void ECOWX(u32 rs, u32 ra, u32 rb) = 0;
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virtual void STHUX(u32 rs, u32 ra, u32 rb) = 0;
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virtual void OR(u32 ra, u32 rs, u32 rb, bool rc) = 0;
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virtual void DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
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virtual void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
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virtual void MTSPR(u32 spr, u32 rs) = 0;
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virtual void DCBI(u32 ra, u32 rb) = 0;
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virtual void NAND(u32 ra, u32 rs, u32 rb, bool rc) = 0;
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virtual void STVXL(u32 vs, u32 ra, u32 rb) = 0;
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virtual void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
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virtual void DIVW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
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virtual void LVLX(u32 vd, u32 ra, u32 rb) = 0;
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virtual void LDBRX(u32 rd, u32 ra, u32 rb) = 0;
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virtual void LSWX(u32 rd, u32 ra, u32 rb) = 0;
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virtual void LWBRX(u32 rd, u32 ra, u32 rb) = 0;
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virtual void LFSX(u32 frd, u32 ra, u32 rb) = 0;
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virtual void SRW(u32 ra, u32 rs, u32 rb, bool rc) = 0;
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virtual void SRD(u32 ra, u32 rs, u32 rb, bool rc) = 0;
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virtual void LVRX(u32 vd, u32 ra, u32 rb) = 0;
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virtual void LSWI(u32 rd, u32 ra, u32 nb) = 0;
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virtual void LFSUX(u32 frd, u32 ra, u32 rb) = 0;
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virtual void SYNC(u32 l) = 0;
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virtual void LFDX(u32 frd, u32 ra, u32 rb) = 0;
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virtual void LFDUX(u32 frd, u32 ra, u32 rb) = 0;
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virtual void STVLX(u32 vs, u32 ra, u32 rb) = 0;
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virtual void STDBRX(u32 rs, u32 ra, u32 rb) = 0;
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virtual void STSWX(u32 rs, u32 ra, u32 rb) = 0;
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virtual void STWBRX(u32 rs, u32 ra, u32 rb) = 0;
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virtual void STFSX(u32 frs, u32 ra, u32 rb) = 0;
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virtual void STVRX(u32 vs, u32 ra, u32 rb) = 0;
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virtual void STFSUX(u32 frs, u32 ra, u32 rb) = 0;
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virtual void STSWI(u32 rd, u32 ra, u32 nb) = 0;
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virtual void STFDX(u32 frs, u32 ra, u32 rb) = 0;
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virtual void STFDUX(u32 frs, u32 ra, u32 rb) = 0;
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virtual void LVLXL(u32 vd, u32 ra, u32 rb) = 0;
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virtual void LHBRX(u32 rd, u32 ra, u32 rb) = 0;
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virtual void SRAW(u32 ra, u32 rs, u32 rb, bool rc) = 0;
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virtual void SRAD(u32 ra, u32 rs, u32 rb, bool rc) = 0;
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virtual void LVRXL(u32 vd, u32 ra, u32 rb) = 0;
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virtual void DSS(u32 strm, u32 a) = 0;
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virtual void SRAWI(u32 ra, u32 rs, u32 sh, bool rc) = 0;
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virtual void SRADI1(u32 ra, u32 rs, u32 sh, bool rc) = 0;
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virtual void SRADI2(u32 ra, u32 rs, u32 sh, bool rc) = 0;
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virtual void EIEIO() = 0;
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virtual void STVLXL(u32 vs, u32 ra, u32 rb) = 0;
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virtual void STHBRX(u32 rs, u32 ra, u32 rb) = 0;
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virtual void EXTSH(u32 ra, u32 rs, bool rc) = 0;
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virtual void STVRXL(u32 sd, u32 ra, u32 rb) = 0;
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virtual void EXTSB(u32 ra, u32 rs, bool rc) = 0;
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virtual void STFIWX(u32 frs, u32 ra, u32 rb) = 0;
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virtual void EXTSW(u32 ra, u32 rs, bool rc) = 0;
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virtual void ICBI(u32 ra, u32 rb) = 0;
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virtual void DCBZ(u32 ra, u32 rb) = 0;
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virtual void LWZ(u32 rd, u32 ra, s32 d) = 0;
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virtual void LWZU(u32 rd, u32 ra, s32 d) = 0;
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virtual void LBZ(u32 rd, u32 ra, s32 d) = 0;
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virtual void LBZU(u32 rd, u32 ra, s32 d) = 0;
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virtual void STW(u32 rs, u32 ra, s32 d) = 0;
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virtual void STWU(u32 rs, u32 ra, s32 d) = 0;
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virtual void STB(u32 rs, u32 ra, s32 d) = 0;
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virtual void STBU(u32 rs, u32 ra, s32 d) = 0;
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virtual void LHZ(u32 rd, u32 ra, s32 d) = 0;
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virtual void LHZU(u32 rd, u32 ra, s32 d) = 0;
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virtual void LHA(u32 rs, u32 ra, s32 d) = 0;
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virtual void LHAU(u32 rs, u32 ra, s32 d) = 0;
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virtual void STH(u32 rs, u32 ra, s32 d) = 0;
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virtual void STHU(u32 rs, u32 ra, s32 d) = 0;
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virtual void LMW(u32 rd, u32 ra, s32 d) = 0;
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virtual void STMW(u32 rs, u32 ra, s32 d) = 0;
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virtual void LFS(u32 frd, u32 ra, s32 d) = 0;
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virtual void LFSU(u32 frd, u32 ra, s32 d) = 0;
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virtual void LFD(u32 frd, u32 ra, s32 d) = 0;
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virtual void LFDU(u32 frd, u32 ra, s32 d) = 0;
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virtual void STFS(u32 frs, u32 ra, s32 d) = 0;
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virtual void STFSU(u32 frs, u32 ra, s32 d) = 0;
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virtual void STFD(u32 frs, u32 ra, s32 d) = 0;
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virtual void STFDU(u32 frs, u32 ra, s32 d) = 0;
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virtual void LD(u32 rd, u32 ra, s32 ds) = 0;
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virtual void LDU(u32 rd, u32 ra, s32 ds) = 0;
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virtual void LWA(u32 rd, u32 ra, s32 ds) = 0;
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virtual void FDIVS(u32 frd, u32 fra, u32 frb, bool rc) = 0;
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virtual void FSUBS(u32 frd, u32 fra, u32 frb, bool rc) = 0;
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virtual void FADDS(u32 frd, u32 fra, u32 frb, bool rc) = 0;
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virtual void FSQRTS(u32 frd, u32 frb, bool rc) = 0;
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virtual void FRES(u32 frd, u32 frb, bool rc) = 0;
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virtual void FMULS(u32 frd, u32 fra, u32 frc, bool rc) = 0;
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virtual void FMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0;
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virtual void FMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0;
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virtual void FNMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0;
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virtual void FNMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0;
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virtual void STD(u32 rs, u32 ra, s32 ds) = 0;
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virtual void STDU(u32 rs, u32 ra, s32 ds) = 0;
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virtual void MTFSB1(u32 bt, bool rc) = 0;
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virtual void MCRFS(u32 bf, u32 bfa) = 0;
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virtual void MTFSB0(u32 bt, bool rc) = 0;
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virtual void MTFSFI(u32 crfd, u32 i, bool rc) = 0;
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virtual void MFFS(u32 frd, bool rc) = 0;
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virtual void MTFSF(u32 flm, u32 frb, bool rc) = 0;
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|
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virtual void FCMPU(u32 bf, u32 fra, u32 frb) = 0;
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virtual void FRSP(u32 frd, u32 frb, bool rc) = 0;
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virtual void FCTIW(u32 frd, u32 frb, bool rc) = 0;
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virtual void FCTIWZ(u32 frd, u32 frb, bool rc) = 0;
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virtual void FDIV(u32 frd, u32 fra, u32 frb, bool rc) = 0;
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virtual void FSUB(u32 frd, u32 fra, u32 frb, bool rc) = 0;
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|
virtual void FADD(u32 frd, u32 fra, u32 frb, bool rc) = 0;
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virtual void FSQRT(u32 frd, u32 frb, bool rc) = 0;
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virtual void FSEL(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0;
|
|
virtual void FMUL(u32 frd, u32 fra, u32 frc, bool rc) = 0;
|
|
virtual void FRSQRTE(u32 frd, u32 frb, bool rc) = 0;
|
|
virtual void FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0;
|
|
virtual void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0;
|
|
virtual void FNMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0;
|
|
virtual void FNMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0;
|
|
virtual void FCMPO(u32 crfd, u32 fra, u32 frb) = 0;
|
|
virtual void FNEG(u32 frd, u32 frb, bool rc) = 0;
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|
virtual void FMR(u32 frd, u32 frb, bool rc) = 0;
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|
virtual void FNABS(u32 frd, u32 frb, bool rc) = 0;
|
|
virtual void FABS(u32 frd, u32 frb, bool rc) = 0;
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|
virtual void FCTID(u32 frd, u32 frb, bool rc) = 0;
|
|
virtual void FCTIDZ(u32 frd, u32 frb, bool rc) = 0;
|
|
virtual void FCFID(u32 frd, u32 frb, bool rc) = 0;
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|
|
virtual void UNK(const u32 code, const u32 opcode, const u32 gcode) = 0;
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|
};
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