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https://github.com/RPCS3/rpcs3.git
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333 lines
7.4 KiB
C++
333 lines
7.4 KiB
C++
#include "stdafx.h"
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#include "SPUDisAsm.h"
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#include "SPUAnalyser.h"
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#include "SPUThread.h"
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const spu_decoder<SPUDisAsm> s_spu_disasm;
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const spu_decoder<spu_itype> s_spu_itype;
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const spu_decoder<spu_iflag> s_spu_iflag;
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#include "util/v128.hpp"
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#include "util/v128sse.hpp"
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u32 SPUDisAsm::disasm(u32 pc)
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{
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dump_pc = pc;
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be_t<u32> op;
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std::memcpy(&op, m_offset + pc, 4);
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m_op = op;
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(this->*(s_spu_disasm.decode(m_op)))({ m_op });
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return 4;
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}
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std::pair<bool, v128> SPUDisAsm::try_get_const_value(u32 reg, u32 pc) const
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{
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if (m_mode != cpu_disasm_mode::interpreter && m_mode != cpu_disasm_mode::normal)
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{
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return {};
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}
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if (pc == umax)
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{
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pc = dump_pc;
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}
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// Scan LS backwards from this instruction (until PC=0)
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// Search for the first register modification or branch instruction
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for (s32 i = pc - 4; i >= 0; i -= 4)
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{
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const u32 opcode = *reinterpret_cast<const be_t<u32>*>(m_offset + i);
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const spu_opcode_t op0{ opcode };
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const auto type = s_spu_itype.decode(opcode);
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if (type & spu_itype::branch || type == spu_itype::UNK || !opcode)
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{
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if (reg < 80u)
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{
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return {};
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}
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// We do not care about function calls if register is non-volatile
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if ((type != spu_itype::BRSL && type != spu_itype::BRASL && type != spu_itype::BISL) || op0.rt == reg)
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{
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return {};
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}
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continue;
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}
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//const auto flag = s_spu_iflag.decode(opcode);
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// TODO: It detects spurious register modifications
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if (u32 dst = type & spu_itype::_quadrop ? +op0.rt4 : +op0.rt; dst == reg)
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{
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// Note: It's not 100% reliable because it won't detect branch targets within [i, dump_pc] range (e.g. if-else statement for command's value)
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switch (type)
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{
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case spu_itype::IL:
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{
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return { true, v128::from32p(op0.si16) };
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}
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case spu_itype::ILA:
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{
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return { true, v128::from32p(op0.i18) };
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}
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case spu_itype::ILHU:
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{
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return { true, v128::from32p(op0.i16 << 16) };
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}
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case spu_itype::CBD:
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case spu_itype::CHD:
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case spu_itype::CWD:
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case spu_itype::CDD:
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{
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// Aligned stack assumption
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if (op0.ra == 1u)
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{
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u32 size = 0;
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switch (type)
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{
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case spu_itype::CBD: size = 1; break;
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case spu_itype::CHD: size = 2; break;
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case spu_itype::CWD: size = 4; break;
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case spu_itype::CDD: size = 8; break;
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default: fmt::throw_exception("Unreachable");
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}
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const u32 index = (~op0.i7 & 0xf) / size;
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auto res = v128::from64(0x18191A1B1C1D1E1Full, 0x1011121314151617ull);
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switch (size)
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{
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case 1: res._u8[index] = 0x03; break;
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case 2: res._u16[index] = 0x0203; break;
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case 4: res._u32[index] = 0x00010203; break;
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case 8: res._u64[index] = 0x0001020304050607ull; break;
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default: fmt::throw_exception("Unreachable");
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}
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return {true, res};
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}
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return {};
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}
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case spu_itype::FSMBI:
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{
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v128 res;
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for (s32 i = 0; i < 16; i++)
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{
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res._u8[i] = (op0.i16 & (1 << i)) ? 0xFF : 0x00;
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}
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return { true, res };
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}
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case spu_itype::IOHL:
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{
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// Avoid multi-recursion for now
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if (dump_pc != pc)
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{
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return {};
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}
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if (i >= 4)
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{
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// Search for ILHU+IOHL pattern (common pattern for 32-bit constants formation)
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// But don't limit to it
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const auto [is_const, value] = try_get_const_value(reg, i);
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if (is_const)
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{
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return { true, value | v128::from32p(op0.i16) };
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}
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}
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return {};
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}
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case spu_itype::STQA:
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case spu_itype::STQD:
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case spu_itype::STQR:
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case spu_itype::STQX:
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case spu_itype::WRCH:
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{
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// Do not modify RT
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break;
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}
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default: return {};
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}
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}
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}
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return {};
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}
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SPUDisAsm::insert_mask_info SPUDisAsm::try_get_insert_mask_info(const v128& mask)
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{
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if ((mask & v128::from8p(0xe0)) != v128{})
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{
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return {};
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}
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s32 first = -1, src_first = 0, last = 16;
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auto access = [&](u32 index) -> u8
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{
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return mask._u8[index ^ 0xf];
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};
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for (s32 i = 0; i < 16; i++)
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{
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if (access(i) & 0x10)
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{
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if ((access(i) & 0x0f) != i)
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{
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return {};
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}
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if (first != -1 && last == 16)
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{
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last = i;
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}
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continue;
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}
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if (last != 16)
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{
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return {};
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}
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if (first == -1)
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{
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src_first = access(i);
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first = i;
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}
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if (src_first + (i - first) != access(i))
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{
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return {};
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}
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}
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if (first == -1)
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{
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return {};
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}
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const u32 size = last - first;
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if ((size | src_first | first) & (size - 1))
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{
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return {};
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}
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if (size == 16)
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{
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// 0x0, 0x1, 0x2, .. 0xE, 0xF is not allowed
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return {};
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}
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// [type size, dst index, src index]
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return {size, first / size, src_first / size};
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}
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void SPUDisAsm::WRCH(spu_opcode_t op)
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{
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const auto [is_const, value] = try_get_const_value(op.rt);
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if (is_const)
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{
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switch (op.ra)
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{
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case MFC_Cmd:
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{
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DisAsm("wrch", spu_ch_name[op.ra], fmt::format("%s #%s", spu_reg_name[op.rt], MFC(value._u8[12])).c_str());
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return;
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}
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case MFC_WrListStallAck:
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case MFC_WrTagMask:
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{
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const u32 v = value._u32[3];
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if (v && !(v & (v - 1)))
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DisAsm("wrch", spu_ch_name[op.ra], fmt::format("%s #%s (tag=%u)", spu_reg_name[op.rt], SignedHex(v), std::countr_zero(v)).c_str()); // Single-tag mask
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else
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DisAsm("wrch", spu_ch_name[op.ra], fmt::format("%s #%s", spu_reg_name[op.rt], SignedHex(v)).c_str()); // Multi-tag mask (or zero)
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return;
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}
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case MFC_EAH:
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{
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DisAsm("wrch", spu_ch_name[op.ra], fmt::format("%s #%s", spu_reg_name[op.rt], SignedHex(value._u32[3])).c_str());
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return;
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}
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case MFC_Size:
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{
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DisAsm("wrch", spu_ch_name[op.ra], fmt::format("%s #%s", spu_reg_name[op.rt], SignedHex(value._u16[6])).c_str());
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return;
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}
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case MFC_TagID:
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{
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DisAsm("wrch", spu_ch_name[op.ra], fmt::format("%s #%u", spu_reg_name[op.rt], value._u8[12]).c_str());
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return;
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}
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case MFC_WrTagUpdate:
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{
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const auto upd = fmt::format("%s", mfc_tag_update(value._u32[3]));
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DisAsm("wrch", spu_ch_name[op.ra], fmt::format("%s #%s", spu_reg_name[op.rt], upd == "empty" ? "IMMEDIATE" : upd).c_str());
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return;
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}
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default:
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{
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DisAsm("wrch", spu_ch_name[op.ra], fmt::format("%s #%s", spu_reg_name[op.rt], SignedHex(value._u32[3])).c_str());
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return;
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}
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}
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}
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DisAsm("wrch", spu_ch_name[op.ra], spu_reg_name[op.rt]);
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}
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void SPUDisAsm::IOHL(spu_opcode_t op)
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{
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const auto [is_const, value] = try_get_const_value(op.rt);
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if (is_const)
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{
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// Only print constant for a 4 equal 32-bit constants array
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if (value == v128::from32p(value._u32[0]))
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{
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DisAsm("iohl", spu_reg_name[op.rt], fmt::format("%s #%s", SignedHex(+op.i16), (value._u32[0] | op.i16)).c_str());
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return;
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}
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}
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DisAsm("iohl", spu_reg_name[op.rt], op.i16);
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}
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void SPUDisAsm::SHUFB(spu_opcode_t op)
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{
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const auto [is_const, value] = try_get_const_value(op.rc);
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if (is_const)
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{
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const auto [size, dst, src] = try_get_insert_mask_info(value);
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if (size)
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{
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if ((size >= 4u && !src) || (size == 2u && src == 1u) || (size == 1u && src == 3u))
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{
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// Comment insertion pattern for CWD-alike instruction
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DisAsm("shufb", spu_reg_name[op.rt4], spu_reg_name[op.ra], spu_reg_name[op.rb], fmt::format("%s #i%u[%u]", spu_reg_name[op.rc], size * 8, dst).c_str());
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return;
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}
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// Comment insertion pattern for unknown instruction formations
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DisAsm("shufb", spu_reg_name[op.rt4], spu_reg_name[op.ra], spu_reg_name[op.rb], fmt::format("%s #i%u[%u] = [%u]", spu_reg_name[op.rc], size * 8, dst, src).c_str());
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return;
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}
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}
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DisAsm("shufb", spu_reg_name[op.rt4], spu_reg_name[op.ra], spu_reg_name[op.rb], spu_reg_name[op.rc]);
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}
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