mirror of
https://github.com/RPCS3/rpcs3.git
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629 lines
16 KiB
C++
629 lines
16 KiB
C++
#pragma once
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#include "Emu/Cell/Common.h"
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#include "Emu/Memory/atomic_type.h"
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#include "PPCThread.h"
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#include "Emu/SysCalls/lv2/sleep_queue_type.h"
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#include "Emu/SysCalls/lv2/sys_event.h"
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#include "Emu/Event.h"
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#include "MFC.h"
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enum SPUchannels
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{
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SPU_RdEventStat = 0, //Read event status with mask applied
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SPU_WrEventMask = 1, //Write event mask
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SPU_WrEventAck = 2, //Write end of event processing
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SPU_RdSigNotify1 = 3, //Signal notification 1
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SPU_RdSigNotify2 = 4, //Signal notification 2
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SPU_WrDec = 7, //Write decrementer count
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SPU_RdDec = 8, //Read decrementer count
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SPU_RdEventMask = 11, //Read event mask
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SPU_RdMachStat = 13, //Read SPU run status
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SPU_WrSRR0 = 14, //Write SPU machine state save/restore register 0 (SRR0)
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SPU_RdSRR0 = 15, //Read SPU machine state save/restore register 0 (SRR0)
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SPU_WrOutMbox = 28, //Write outbound mailbox contents
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SPU_RdInMbox = 29, //Read inbound mailbox contents
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SPU_WrOutIntrMbox = 30, //Write outbound interrupt mailbox contents (interrupting PPU)
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};
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enum MFCchannels
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{
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MFC_WrMSSyncReq = 9, //Write multisource synchronization request
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MFC_RdTagMask = 12, //Read tag mask
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MFC_LSA = 16, //Write local memory address command parameter
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MFC_EAH = 17, //Write high order DMA effective address command parameter
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MFC_EAL = 18, //Write low order DMA effective address command parameter
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MFC_Size = 19, //Write DMA transfer size command parameter
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MFC_TagID = 20, //Write tag identifier command parameter
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MFC_Cmd = 21, //Write and enqueue DMA command with associated class ID
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MFC_WrTagMask = 22, //Write tag mask
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MFC_WrTagUpdate = 23, //Write request for conditional or unconditional tag status update
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MFC_RdTagStat = 24, //Read tag status with mask applied
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MFC_RdListStallStat = 25, //Read DMA list stall-and-notify status
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MFC_WrListStallAck = 26, //Write DMA list stall-and-notify acknowledge
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MFC_RdAtomicStat = 27, //Read completion status of last completed immediate MFC atomic update command
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};
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enum SPUEvents
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{
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SPU_EVENT_MS = 0x1000, // multisource synchronization event
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SPU_EVENT_A = 0x800, // privileged attention event
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SPU_EVENT_LR = 0x400, // lock line reservation lost event
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SPU_EVENT_S1 = 0x200, // signal notification register 1 available
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SPU_EVENT_S2 = 0x100, // signal notification register 2 available
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SPU_EVENT_LE = 0x80, // SPU outbound mailbox available
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SPU_EVENT_ME = 0x40, // SPU outbound interrupt mailbox available
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SPU_EVENT_TM = 0x20, // SPU decrementer became negative (?)
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SPU_EVENT_MB = 0x10, // SPU inbound mailbox available
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SPU_EVENT_QV = 0x4, // MFC SPU command queue available
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SPU_EVENT_SN = 0x2, // MFC list command stall-and-notify event
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SPU_EVENT_TG = 0x1, // MFC tag-group status update event
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SPU_EVENT_IMPLEMENTED = SPU_EVENT_LR,
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};
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enum
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{
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SPU_RUNCNTL_STOP = 0,
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SPU_RUNCNTL_RUNNABLE = 1,
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};
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enum
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{
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SPU_STATUS_STOPPED = 0x0,
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SPU_STATUS_RUNNING = 0x1,
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SPU_STATUS_STOPPED_BY_STOP = 0x2,
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SPU_STATUS_STOPPED_BY_HALT = 0x4,
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SPU_STATUS_WAITING_FOR_CHANNEL = 0x8,
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SPU_STATUS_SINGLE_STEP = 0x10,
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};
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enum : u32
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{
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SYS_SPU_THREAD_BASE_LOW = 0xf0000000,
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SYS_SPU_THREAD_BASE_MASK = 0xfffffff,
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SYS_SPU_THREAD_OFFSET = 0x00100000,
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SYS_SPU_THREAD_SNR1 = 0x05400c,
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SYS_SPU_THREAD_SNR2 = 0x05C00c,
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};
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enum
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{
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MFC_LSA_offs = 0x3004,
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MFC_EAH_offs = 0x3008,
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MFC_EAL_offs = 0x300C,
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MFC_Size_Tag_offs = 0x3010,
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MFC_Class_CMD_offs = 0x3014,
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MFC_CMDStatus_offs = 0x3014,
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MFC_QStatus_offs = 0x3104,
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Prxy_QueryType_offs = 0x3204,
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Prxy_QueryMask_offs = 0x321C,
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Prxy_TagStatus_offs = 0x322C,
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SPU_Out_MBox_offs = 0x4004,
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SPU_In_MBox_offs = 0x400C,
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SPU_MBox_Status_offs = 0x4014,
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SPU_RunCntl_offs = 0x401C,
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SPU_Status_offs = 0x4024,
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SPU_NPC_offs = 0x4034,
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SPU_RdSigNotify1_offs = 0x1400C,
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SPU_RdSigNotify2_offs = 0x1C00C,
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};
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#define mmToU64Ptr(x) ((u64*)(&x))
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#define mmToU32Ptr(x) ((u32*)(&x))
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#define mmToU16Ptr(x) ((u16*)(&x))
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#define mmToU8Ptr(x) ((u8*)(&x))
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struct g_imm_table_struct
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{
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//u16 cntb_table[65536];
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__m128i fsmb_table[65536];
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__m128i fsmh_table[256];
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__m128i fsm_table[16];
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__m128i sldq_pshufb[32];
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__m128i srdq_pshufb[32];
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__m128i rldq_pshufb[16];
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g_imm_table_struct()
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{
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/*static_assert(offsetof(g_imm_table_struct, cntb_table) == 0, "offsetof(cntb_table) != 0");
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for (u32 i = 0; i < sizeof(cntb_table) / sizeof(cntb_table[0]); i++)
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{
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u32 cnt_low = 0, cnt_high = 0;
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for (u32 j = 0; j < 8; j++)
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{
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cnt_low += (i >> j) & 1;
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cnt_high += (i >> (j + 8)) & 1;
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}
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cntb_table[i] = (cnt_high << 8) | cnt_low;
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}*/
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for (u32 i = 0; i < sizeof(fsm_table) / sizeof(fsm_table[0]); i++)
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{
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for (u32 j = 0; j < 4; j++) mmToU32Ptr(fsm_table[i])[j] = (i & (1 << j)) ? ~0 : 0;
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}
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for (u32 i = 0; i < sizeof(fsmh_table) / sizeof(fsmh_table[0]); i++)
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{
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for (u32 j = 0; j < 8; j++) mmToU16Ptr(fsmh_table[i])[j] = (i & (1 << j)) ? ~0 : 0;
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}
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for (u32 i = 0; i < sizeof(fsmb_table) / sizeof(fsmb_table[0]); i++)
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{
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for (u32 j = 0; j < 16; j++) mmToU8Ptr(fsmb_table[i])[j] = (i & (1 << j)) ? ~0 : 0;
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}
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for (u32 i = 0; i < sizeof(sldq_pshufb) / sizeof(sldq_pshufb[0]); i++)
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{
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for (u32 j = 0; j < 16; j++) mmToU8Ptr(sldq_pshufb[i])[j] = (u8)(j - i);
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}
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for (u32 i = 0; i < sizeof(srdq_pshufb) / sizeof(srdq_pshufb[0]); i++)
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{
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for (u32 j = 0; j < 16; j++) mmToU8Ptr(srdq_pshufb[i])[j] = (j + i > 15) ? 0xff : (u8)(j + i);
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}
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for (u32 i = 0; i < sizeof(rldq_pshufb) / sizeof(rldq_pshufb[0]); i++)
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{
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for (u32 j = 0; j < 16; j++) mmToU8Ptr(rldq_pshufb[i])[j] = (u8)(j - i) & 0xf;
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}
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}
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};
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extern const g_imm_table_struct g_imm_table;
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enum FPSCR_EX
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{
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//Single-precision exceptions
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FPSCR_SOVF = 1 << 2, //Overflow
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FPSCR_SUNF = 1 << 1, //Underflow
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FPSCR_SDIFF = 1 << 0, //Different (could be IEEE non-compliant)
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//Double-precision exceptions
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FPSCR_DOVF = 1 << 13, //Overflow
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FPSCR_DUNF = 1 << 12, //Underflow
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FPSCR_DINX = 1 << 11, //Inexact
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FPSCR_DINV = 1 << 10, //Invalid operation
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FPSCR_DNAN = 1 << 9, //NaN
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FPSCR_DDENORM = 1 << 8, //Denormal
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};
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//Is 128 bits, but bits 0-19, 24-28, 32-49, 56-60, 64-81, 88-92, 96-115, 120-124 are unused
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class SPU_FPSCR
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{
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public:
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u32 _u32[4];
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SPU_FPSCR() {}
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std::string ToString() const
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{
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return fmt::Format("%08x%08x%08x%08x", _u32[3], _u32[2], _u32[1], _u32[0]);
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}
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void Reset()
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{
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memset(this, 0, sizeof(*this));
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}
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//slice -> 0 - 1 (double-precision slice index)
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//NOTE: slices follow u128 indexing, i.e. slice 0 is RIGHT end of register!
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//roundTo -> FPSCR_RN_*
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void setSliceRounding(u8 slice, u8 roundTo)
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{
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int shift = 8 + 2*slice;
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//rounding is located in the left end of the FPSCR
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this->_u32[3] = (this->_u32[3] & ~(3 << shift)) | (roundTo << shift);
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}
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//Slice 0 or 1
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u8 checkSliceRounding(u8 slice) const
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{
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switch(slice)
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{
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case 0:
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return this->_u32[3] >> 8 & 0x3;
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case 1:
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return this->_u32[3] >> 10 & 0x3;
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default:
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throw fmt::Format("Unexpected slice value in FPSCR::checkSliceRounding(): %d", slice);
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return 0;
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}
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}
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//Single-precision exception flags (all 4 slices)
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//slice -> slice number (0-3)
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//exception: FPSCR_S* bitmask
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void setSinglePrecisionExceptionFlags(u8 slice, u32 exceptions)
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{
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_u32[slice] |= exceptions;
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}
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//Single-precision divide-by-zero flags (all 4 slices)
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//slice -> slice number (0-3)
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void setDivideByZeroFlag(u8 slice)
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{
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_u32[0] |= 1 << (8 + slice);
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}
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//Double-precision exception flags
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//slice -> slice number (0-1)
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//exception: FPSCR_D* bitmask
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void setDoublePrecisionExceptionFlags(u8 slice, u32 exceptions)
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{
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_u32[1+slice] |= exceptions;
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}
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};
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union SPU_SNRConfig_hdr
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{
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u64 value;
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SPU_SNRConfig_hdr() {}
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std::string ToString() const
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{
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return fmt::Format("%01x", value);
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}
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void Reset()
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{
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memset(this, 0, sizeof(*this));
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}
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};
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struct SpuGroupInfo;
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class SPUThread : public PPCThread
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{
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public:
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u128 GPR[128]; // General-Purpose Registers
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SPU_FPSCR FPSCR;
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u32 SRR0;
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SPU_SNRConfig_hdr cfg; // Signal Notification Registers Configuration (OR-mode enabled: 0x1 for SNR1, 0x2 for SNR2)
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std::shared_ptr<EventPort> SPUPs[64]; // SPU Thread Event Ports
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EventManager SPUQs; // SPU Queue Mapping
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std::shared_ptr<SpuGroupInfo> group; // associated SPU Thread Group (null for raw spu)
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u64 m_dec_start; // timestamp of writing decrementer value
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u32 m_dec_value; // written decrementer value
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u32 m_event_mask;
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u32 m_events;
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struct IntrTag
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{
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u32 enabled; // 1 == true
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u32 thread; // established interrupt PPU thread
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u64 mask;
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u64 stat;
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IntrTag()
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: enabled(0)
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, thread(0)
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, mask(0)
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, stat(0)
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{
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}
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} m_intrtag[3];
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// limited lock-free queue, most functions are barrier-free
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template<size_t max_count>
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class Channel
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{
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static_assert(max_count >= 1, "Invalid channel count");
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struct ChannelData
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{
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u32 value;
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u32 is_set;
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};
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atomic_t<ChannelData> m_data[max_count];
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size_t m_push;
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size_t m_pop;
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public:
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__noinline Channel()
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{
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for (size_t i = 0; i < max_count; i++)
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{
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m_data[i].write_relaxed({});
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}
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m_push = 0;
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m_pop = 0;
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}
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__forceinline void PopUncond(u32& res)
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{
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res = m_data[m_pop].read_relaxed().value;
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m_data[m_pop].write_relaxed({});
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m_pop = (m_pop + 1) % max_count;
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}
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__forceinline bool Pop(u32& res)
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{
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const auto data = m_data[m_pop].read_relaxed();
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if (data.is_set)
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{
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res = data.value;
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m_data[m_pop].write_relaxed({});
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m_pop = (m_pop + 1) % max_count;
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return true;
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}
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else
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{
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return false;
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}
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}
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__forceinline bool Pop_XCHG(u32& res) // not barrier-free, not tested
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{
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const auto data = m_data[m_pop].exchange({});
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if (data.is_set)
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{
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res = data.value;
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m_pop = (m_pop + 1) % max_count;
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return true;
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}
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else
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{
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return false;
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}
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}
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__forceinline void PushUncond_OR(const u32 value) // not barrier-free, not tested
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{
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m_data[m_push]._or({ value, 1 });
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m_push = (m_push + 1) % max_count;
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}
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__forceinline void PushUncond(const u32 value)
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{
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m_data[m_push].write_relaxed({ value, 1 });
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m_push = (m_push + 1) % max_count;
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}
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__forceinline bool Push(const u32 value)
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{
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if (m_data[m_push].read_relaxed().is_set)
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{
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return false;
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}
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else
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{
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PushUncond(value);
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return true;
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}
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}
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__forceinline u32 GetCount() const
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{
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u32 res = 0;
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for (size_t i = 0; i < max_count; i++)
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{
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res += m_data[i].read_relaxed().is_set ? 1 : 0;
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}
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return res;
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}
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__forceinline u32 GetFreeCount() const
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{
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u32 res = 0;
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for (size_t i = 0; i < max_count; i++)
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{
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res += m_data[i].read_relaxed().is_set ? 0 : 1;
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}
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return res;
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}
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__forceinline void SetValue(const u32 value)
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{
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m_data[m_push].direct_op([value](ChannelData& v)
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{
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v.value = value;
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});
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}
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__forceinline u32 GetValue() const
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{
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return m_data[m_pop].read_relaxed().value;
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}
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};
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struct MFCReg
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{
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Channel<1> LSA;
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Channel<1> EAH;
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Channel<1> EAL;
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Channel<1> Size_Tag;
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Channel<1> CMDStatus;
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Channel<1> QueryType; // only for prxy
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Channel<1> QueryMask;
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Channel<1> TagStatus;
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Channel<1> AtomicStat;
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} MFC1, MFC2;
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struct StalledList
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{
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u32 lsa;
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u64 ea;
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u16 tag;
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u16 size;
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u32 cmd;
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MFCReg* MFCArgs;
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StalledList()
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: MFCArgs(nullptr)
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{
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}
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} StallList[32];
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Channel<1> StallStat;
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struct
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{
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Channel<1> Out_MBox;
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Channel<1> Out_IntrMBox;
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Channel<4> In_MBox;
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Channel<1> Status;
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Channel<1> NPC;
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Channel<1> SNR[2];
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} SPU;
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void WriteSNR(bool number, u32 value);
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u32 LSA;
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union
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{
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u64 EA;
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struct { u32 EAH, EAL; };
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};
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u32 ls_offset;
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void ProcessCmd(u32 cmd, u32 tag, u32 lsa, u64 ea, u32 size);
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void ListCmd(u32 lsa, u64 ea, u16 tag, u16 size, u32 cmd, MFCReg& MFCArgs);
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void EnqMfcCmd(MFCReg& MFCArgs);
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bool CheckEvents();
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u32 GetChannelCount(u32 ch);
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void WriteChannel(u32 ch, const u128& r);
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void ReadChannel(u128& r, u32 ch);
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void StopAndSignal(u32 code);
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u8 ReadLS8 (const u32 lsa) const { return vm::read8 (lsa + m_offset); }
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u16 ReadLS16 (const u32 lsa) const { return vm::read16 (lsa + m_offset); }
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u32 ReadLS32 (const u32 lsa) const { return vm::read32 (lsa + m_offset); }
|
|
u64 ReadLS64 (const u32 lsa) const { return vm::read64 (lsa + m_offset); }
|
|
u128 ReadLS128(const u32 lsa) const { return vm::read128(lsa + m_offset); }
|
|
|
|
void WriteLS8 (const u32 lsa, const u8& data) const { vm::write8 (lsa + m_offset, data); }
|
|
void WriteLS16 (const u32 lsa, const u16& data) const { vm::write16 (lsa + m_offset, data); }
|
|
void WriteLS32 (const u32 lsa, const u32& data) const { vm::write32 (lsa + m_offset, data); }
|
|
void WriteLS64 (const u32 lsa, const u64& data) const { vm::write64 (lsa + m_offset, data); }
|
|
void WriteLS128(const u32 lsa, const u128& data) const { vm::write128(lsa + m_offset, data); }
|
|
|
|
std::function<void(SPUThread& SPU)> m_custom_task;
|
|
std::function<u64(SPUThread& SPU)> m_code3_func;
|
|
|
|
public:
|
|
SPUThread(CPUThreadType type = CPU_THREAD_SPU);
|
|
virtual ~SPUThread();
|
|
|
|
virtual std::string RegsToString()
|
|
{
|
|
std::string ret = "Registers:\n=========\n";
|
|
|
|
for(uint i=0; i<128; ++i) ret += fmt::Format("GPR[%d] = 0x%s\n", i, GPR[i].to_hex().c_str());
|
|
|
|
return ret;
|
|
}
|
|
|
|
virtual std::string ReadRegString(const std::string& reg)
|
|
{
|
|
std::string::size_type first_brk = reg.find('[');
|
|
if (first_brk != std::string::npos)
|
|
{
|
|
long reg_index;
|
|
reg_index = atol(reg.substr(first_brk + 1, reg.length()-2).c_str());
|
|
if (reg.find("GPR")==0) return fmt::Format("%016llx%016llx", GPR[reg_index]._u64[1], GPR[reg_index]._u64[0]);
|
|
}
|
|
return "";
|
|
}
|
|
|
|
bool WriteRegString(const std::string& reg, std::string value)
|
|
{
|
|
while (value.length() < 32) value = "0"+value;
|
|
std::string::size_type first_brk = reg.find('[');
|
|
if (first_brk != std::string::npos)
|
|
{
|
|
long reg_index;
|
|
reg_index = atol(reg.substr(first_brk + 1, reg.length() - 2).c_str());
|
|
if (reg.find("GPR")==0)
|
|
{
|
|
unsigned long long reg_value0;
|
|
unsigned long long reg_value1;
|
|
try
|
|
{
|
|
reg_value0 = std::stoull(value.substr(16, 31), 0, 16);
|
|
reg_value1 = std::stoull(value.substr(0, 15), 0, 16);
|
|
}
|
|
catch (std::invalid_argument& /*e*/)
|
|
{
|
|
return false;
|
|
}
|
|
GPR[reg_index]._u64[0] = (u64)reg_value0;
|
|
GPR[reg_index]._u64[1] = (u64)reg_value1;
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
public:
|
|
virtual void InitRegs();
|
|
virtual void InitStack();
|
|
virtual void CloseStack();
|
|
virtual void Task();
|
|
void FastCall(u32 ls_addr);
|
|
void FastStop();
|
|
|
|
protected:
|
|
virtual void DoReset();
|
|
virtual void DoRun();
|
|
virtual void DoPause();
|
|
virtual void DoResume();
|
|
virtual void DoStop();
|
|
virtual void DoClose();
|
|
};
|
|
|
|
SPUThread& GetCurrentSPUThread();
|
|
|
|
class spu_thread : cpu_thread
|
|
{
|
|
static const u32 stack_align = 0x10;
|
|
vm::ptr<u64> argv;
|
|
u32 argc;
|
|
vm::ptr<u64> envp;
|
|
|
|
public:
|
|
spu_thread(u32 entry, const std::string& name = "", u32 stack_size = 0, u32 prio = 0);
|
|
|
|
cpu_thread& args(std::initializer_list<std::string> values) override
|
|
{
|
|
if (!values.size())
|
|
return *this;
|
|
|
|
assert(argc == 0);
|
|
|
|
envp.set(Memory.MainMem.AllocAlign((u32)sizeof(envp), stack_align));
|
|
*envp = 0;
|
|
argv.set(Memory.MainMem.AllocAlign(u32(sizeof(argv)* values.size()), stack_align));
|
|
|
|
for (auto &arg : values)
|
|
{
|
|
u32 arg_size = align(u32(arg.size() + 1), stack_align);
|
|
u32 arg_addr = Memory.MainMem.AllocAlign(arg_size, stack_align);
|
|
|
|
std::strcpy(vm::get_ptr<char>(arg_addr), arg.c_str());
|
|
|
|
argv[argc++] = arg_addr;
|
|
}
|
|
|
|
return *this;
|
|
}
|
|
|
|
cpu_thread& run() override
|
|
{
|
|
thread->Run();
|
|
|
|
static_cast<SPUThread*>(thread)->GPR[3].from64(argc);
|
|
static_cast<SPUThread*>(thread)->GPR[4].from64(argv.addr());
|
|
static_cast<SPUThread*>(thread)->GPR[5].from64(envp.addr());
|
|
|
|
return *this;
|
|
}
|
|
};
|