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12251 commits 6 branches 41 tags 239 MiB
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492 commits

Author SHA1 Message Date
Nekotekina
f1e66085cd Fixup for cpu_flag::temp 
Wrong check_state() result was triggering assertion.
 2020-10-26 01:18:26 +03:00
Nekotekina
130a0ef20e Implement cpu_flag::temp flag 
Accompanies wait flag, indicating that it was set in limited conditions.
Such condition don't allow thread to terminate after its removal.
 2020-10-25 21:48:20 +03:00
kd-11
18ca3ed449 rsx: Block-level reservation access 2020-10-25 20:21:04 +03:00
Nekotekina
dc8252bb9f Remove XABORT in PPU/SPU transactions. 
It's expensive for unknown reason. Simply XEND is usually much cheaper.
Add some minor improvements. Use g_sudo_addr.
 2020-10-20 09:10:21 +03:00
Nekotekina
72d1ac22aa SPU: report too many PUTLLC attempts (TSX) 
Mirrored to PPU STCX code and PUTLLUC (STORE128).
 2020-10-19 19:41:28 +03:00
Nekotekina
8ce5392390 TSX: add prefetchw instruction in transaction code 2020-10-19 19:41:28 +03:00
Nekotekina
120849c734 Implement perf stat counter for PPU/SPU reservation ops 
Adds Emu/perf_meter.hpp header file.
Uses RDTSC for speed.
Prints stats at exit.
 2020-10-19 19:41:28 +03:00
Nekotekina
adf50b7c4b Implement cpu_thread::if_suspended 
Use it for opportunistic guaranteed GETLLAR execution (TSX-FA).
 2020-10-18 20:10:48 +03:00
Nekotekina
4078f43984 Fix ppu_stcx_accurate_tx (operand size mismatch) 2020-10-17 21:26:17 +03:00
Eladash
443c2b920d PPU: Handle cache line inconsistencies (PPU 128 reservations) 2020-10-16 22:51:30 +03:00
Nekotekina
583ed61712 SPU: return some give-up behaviour for PUTLLC (TSX) 
Despite using concept of "shared" lock, allow only first to proceed.
This is similar how conditional stores for PPU are implemented.
 2020-10-16 12:14:42 +03:00
Nekotekina
facde63460 PPU: fix ppu_stcx_accurate_tx 
Don't destroy xmm6/xmm7 state on exit.
Improve addr arg handling (simplify).
 2020-10-15 19:24:00 +03:00
Nekotekina
494953997e PPU/SPU: give up on conditional stores if locking fails 
Restores Non-TSX behaviour partially.
 2020-10-15 17:18:49 +03:00
Nekotekina
3bddba0c7a SPU: fix spu_getllar_tx 
Was not executing.
 2020-10-14 02:53:29 +03:00
Nekotekina
97cd641da9 TSX: reimplement spu_getllar_tx 
Only used as a backup method of reading reservation data.
Increase long GETLLAR reporting threshold.
 2020-10-13 21:10:04 +03:00
Nekotekina
dcff8c2637 Fix remaining vm::reservation_lock usages (for now) 
Optimization can be restored later.
 2020-10-13 12:04:59 +03:00
Nekotekina
7a76fb1469 PPU: Add loop logging in STWCX/STDCX 2020-10-13 11:06:58 +03:00
Nekotekina
17f805ae64 PPU: cleanup for TSX path remnant 2020-10-13 10:54:10 +03:00
Nekotekina
dc39a9b84f SPU: Report 'GETLLAR took too long' 
Also move similar code in PPU.
 2020-10-13 00:12:11 +03:00
Nekotekina
5bd5a382c0 PPU: fix LDARX/LWARX in accurate mode (closes #9058) 
Fixup after #9048
Use SSE intrinsics in mov_rdata.
 2020-10-11 19:52:10 +03:00
Nekotekina
2f329cf7b5 PPU: minor improvement for LWARX/LDARX 
Improve chances of loading actual data in memory.
 2020-10-11 17:22:28 +03:00
Nekotekina
f2d2a6b605 JIT cleanup for PPU LLVM 
Remove MemoryManager3 as unnecessary.
Rewrite MemoryManager1 to use its own 512M reservations.
Disabled unwind info registration on all platforms.
Use 64-bit executable pointers under vm::g_exec_addr area.
Stop relying on deploying PPU LLVM objects in first 2G of address space.
Implement jit_module_manager, protect its data with mutex.
 2020-10-11 17:22:28 +03:00
Nekotekina
e8e3a3b2a2 PPU: improve LWARX/LDARX progression 
Should reduce spam ("...took too long")
 2020-10-10 17:36:41 +03:00
Nekotekina
050c3e1d6b Rewrite cpu_thread::suspend_all 
Now it's a function of higher order.
Make only one thread do the hard work of thread pausing.
 2020-10-10 13:58:48 +03:00
Nekotekina
6d83c9cc0e PPU: remove ppu_stcx_tx 
Very small transaction, benefit questionable.
 2020-10-10 13:58:48 +03:00
Nekotekina
346a1d4433 vm: rewrite reservation bits 
Implement classic unique/shared locking concept.
Implement vm::reservation_light_op.
 2020-10-10 13:58:48 +03:00
Eladash
871b15f6e1
PPU: fixup for Accurate 128-byte reservations (#8998) 2020-10-01 18:15:07 +03:00
Eladash
f4ca6f02a1 PPU: Implement support for 128-byte reservations coherency 2020-09-28 22:34:42 +03:00
Eladash
3f7eba19c8 PPU: Upgrade reservations to 8-byte always 2020-09-28 22:34:42 +03:00
Eladash
09cddc84be SPU/PPU: Implement Atomic Cache Line Stores 2020-09-27 20:09:21 +03:00
Eladash
a52a16807f PPU: Use SEQ-CST memory barrier in reservation load 2020-09-15 11:20:17 +02:00
Eladash
d489b02fc1 PPU: Do not allow unaligned/unmapped reservation addresses 2020-09-10 13:35:57 +02:00
Eladash
43fce92aa9 PPU: reduce LARX logging level to warning 2020-09-08 15:23:55 +02:00
Eladash
2f3e0044f1
PPU: Cleanup & unify reservation loads (#8849) 2020-09-07 22:06:09 +01:00
Eladash
73d23eb6e6
SPU: Implement Accurate DMA (#8822) 2020-09-02 23:58:29 +02:00
Eladash
933737e8f0 PPU: log LR in HLE functions 2020-08-27 23:52:37 +01:00
Eladash
c099bb817f Debugger: Disable PPU address redirection 
It causes more confusion than it helps.
 2020-08-25 17:43:07 +02:00
Eladash
7fe98d8d66 Debugger: Add missing PPU stack register checks 2020-08-25 17:43:07 +02:00
Eladash
3ce7fd7894 Debugger: Fix instructions editor 2020-08-25 17:43:07 +02:00
Eladash
917069e31a
PPU Precise/LLVM: Support NJ modes (#8617) 2020-07-25 07:41:41 +01:00
Eladash
84470c34db SPU: Disable PUTLLC NOP transfers detection on TSX path 2020-07-09 03:17:35 +01:00
Eladash
dc25a3fa2a PPU debugger: Show stack address of each function 2020-07-06 18:58:16 +02:00
Eladash
c98ec4d014 PPU debugger: Fix functions stack bounds check 2020-07-06 18:58:16 +02:00
sampletext32
437f374bae Fix some checks 2020-06-04 19:48:08 +03:00
Nekotekina
938ca90a02 Improve Stop Watchdog 
Prevent termination if PPU LLVM compilation is in progress.
 2020-06-01 02:27:33 +03:00
Eladash
f0cdd8ace6 PPU: Implement PPU Traps Stubbing option 2020-05-27 22:39:29 +03:00
Eladash
91d06a9729
SPU LLVM: fixup after #8175 (#8214) 
Mask out RESULT cmd bit, do not create unbound branch blocks. (non-TSX)
 2020-05-14 13:34:14 +01:00
Nick Renieris
b1fb5b6239 Emu/Config: Add option for accurate PPU LLVM vector NaNs 
Turned off by default.
 2020-05-14 11:14:28 +01:00
Eladash
5c4c8f4539 PPU: Use optimized reservation waiting for reservation load (non-TSX) 2020-05-13 16:53:59 +03:00
Eladash
525453794f SPU/PPU reservations: Optimizations part 1 
- Implement vm::reservation_trylock, optimized locking on reservation stores with no waiting. Always fail if reservation lock bitsa are set.
- Make SPU accurate GET transfers on non-TSX not modify reservation lock bits.
- Add some optimization regarding to unmodified data reservations writes.
 2020-05-13 11:10:13 +01:00