Commit graph

314 commits

Author SHA1 Message Date
Nekotekina
5d934c8759 Improve narrow() and size32() with src_loc detection 2020-12-09 16:26:20 +03:00
Nekotekina
e055d16b2c Replace verify() with ensure() with auto src location.
Expression ensure(x) returns x.
Using comma operator removed.
2020-12-09 15:43:38 +03:00
RipleyTom
af8c661a64 Remove BOM markers 2020-12-06 15:30:12 +03:00
Eladash
28cbba5a7d
SPU LLVM: fix AND instruction family (#9290)
Incorrect immediate test (looks like copypasta)
2020-11-18 14:36:26 +03:00
Nekotekina
1b8bf081b5 Upgrade to LLVM 11 Stable 2020-11-02 21:23:25 +03:00
Nekotekina
fe03b55046 TSX: tiny optimization of transaction functions
Because new memory manager puts them in first 2G.
2020-11-01 14:44:59 +03:00
Eladash
c2c559f8d9 Disasm: do not allow to access previous instructions in non-interpreter mode 2020-10-31 17:15:47 +03:00
Nekotekina
425fce5070 SPU: load previous data on PUTLLC failure
Since it will most likely execute GETLLAR to load it again.
Only implemented for TSX at moment.
2020-10-30 02:58:39 +03:00
Eladash
4cafd5a31c SPU: Remove dead additions in Accurate Xfloat 2020-10-03 20:31:35 +03:00
Eladash
ad37259ccc SPU: Implement many missing channel counts 2020-09-22 19:47:47 +03:00
eladash
36ac68b436 SPU: Implement events channel count, minor interrupts fixes 2020-09-18 21:57:24 +03:00
Eladash
4ffc58a8ce SPU: Cleanup for Accurate PUTLLUC
Should no longer affect GET commands because Accurate DMA is available for this functionality.
2020-09-04 10:20:44 +02:00
Eladash
73d23eb6e6
SPU: Implement Accurate DMA (#8822) 2020-09-02 23:58:29 +02:00
Eladash
47b545282e
SPU: Fix events ACK, minor optimizations (#8771) 2020-08-27 21:36:54 +01:00
Eladash
995cb8125e
SPU LLVM: Improve approx FCGT (#8728) 2020-08-14 19:33:35 +01:00
Whatcookie
9e4f43f4d1
SPU LLVM: Add icelake optimized paths for SHUFB (#8712) 2020-08-13 15:00:56 +01:00
Eladash
8cdfe5952a
SPU/PPU LLVM: Improve 0 addend FMA detection (#8709) 2020-08-13 04:13:08 +03:00
Eladash
57471f8c94 SPU LLVM: Fix signed zeroes handling on Accurate xfloat 2020-08-08 22:21:22 +01:00
Eladash
7e11855330 SPU/PPU LLVM: Fix FMA signed zeroes handling 2020-08-08 22:21:22 +01:00
Eladash
f6764767f6 SPU/PPU LLVM: Fix cpu_translator::get_const_vector<v128>() 2020-07-30 17:06:24 +01:00
Eladash
21a1072117 SPU LLVM: Minor cleanup after #8559 2020-07-29 03:32:21 +03:00
Malcolm Jestadt
a9d0ffcac1 SPU LLVM: Avoid additional endian swapping
- Avoid additional endian swapping with the ROTQBY and ROTQBYBI instructions
- ROTQBYI is left out intentionally, since it caused worse codegen
2020-07-26 11:36:50 +01:00
Malcolm Jestadt
824be77bba SPU LLVM: Avoid redundant endian swapping
- PSHUFB operates in reverse byte order from SHUFB, so we can take advantage of that to swap endianness without additional transformations in some situations
2020-07-26 11:36:50 +01:00
Whatcookie
9f829b375a
SPU/PPU LLVM: Optimize VSEL/SELB with constant mask (#8559) 2020-07-25 17:59:35 +01:00
Eladash
3354c800d7
SPU/PPU LLVM: Improve expressions matching (#8620) 2020-07-24 16:53:48 +01:00
Eladash
c37bc3c55c SPU: Make spu_thread::offset private 2020-07-19 17:58:49 +03:00
Malcolm Jestadt
6cc0fe4221 SPU LLVM: Avoid negative clamping when the input is known to be positive 2020-07-19 17:56:59 +03:00
Eladash
af1ceb1151 SPU LLVM: LS Memory Mirrors (Optimize loads/stores) 2020-07-18 02:01:33 +03:00
Eladash
282b00674a SPU LLVM: Optimize non-constant Tag Update requests 2020-07-10 02:52:02 +03:00
Eladash
235d12aa6b SPU MFC: Never clear tag status in WrTagUpdate 2020-07-10 02:52:02 +03:00
Eladash
5d1fc546a8 SPU MFC: Fix MFC_WrTagUpdate channel count
Always report available, in realhw this is just a hint if the previous tag update hasnt been checked yet by the MFC, avoiding blocking writes and allowing the SPU to execute some code while it processes the previous update request.
Except for MFC_TAG_UPDATE_IMMEDIATE, where it also waits for MFC to process it.
2020-07-10 02:52:02 +03:00
Eladash
72337f2678 SPU LLVM: Fix barrier commands enqueuing 2020-07-02 22:46:02 +03:00
Eladash
2c93fecd8b SPU: Use named constants for MFC tag updates 2020-06-27 20:42:41 +01:00
Eladash
20fcc6530f SPU LLVM: Fix WRCH instruction to WrTagUpd 2020-06-27 20:42:41 +01:00
Eladash
d7842b7de2 SPU LLVM: Fix WRCH instruction to WrTagMask 2020-06-27 07:04:37 +01:00
Eladash
3ee1d8aed1 fixup 2020-06-18 06:47:07 +03:00
Eladash
5c6dae498b SPU LLVM: Avoid bad optimization in FCGT 2020-06-18 06:47:07 +03:00
Malcolm Jestadt
dcf5c06d6d SPU LLVM: Optimize FM when op.ra == op.rb 2020-06-06 22:27:48 +03:00
Malcolm Jestadt
8357523ec0 SPU LLVM: Additional FCGT optimizations 2020-06-06 22:27:48 +03:00
Malcolm Jestadt
39149fd84d SPU LLVM: Partial revert for FM/FMA changes and other improvements
- Revert changes to FM and FMA instructions
- Allow non accurate/approx FMA family instructions to use native FMA
- Minor optimization for FMA ops with a constant 0 multiply
2020-06-06 22:27:48 +03:00
Malcolm Jestadt
289c594187 SPU LLVM: Fix theoretical issue with FCGT optimizations 2020-06-06 22:27:48 +03:00
Malcolm Jestadt
c601374b1f SPU LLVM: Use clamping helpers for FMA32x4 and FM 2020-06-01 21:39:28 +03:00
Nekotekina
1507a59786 SPU LLVM: fix spu_cache dependency
Should fix possible crash on exit.
2020-05-31 21:54:04 +03:00
Nekotekina
8e9d2fa70e SPU LLVM: implement get_segment_base()
Fake function used to compute 32-bit offset of local functions.
2020-05-27 18:53:09 +03:00
Eladash
81684919f5 SPU MFC: Implement MFC_SDCRZ_CMD 2020-05-20 22:55:30 +03:00
Malcolm Jestadt
c47d04fd2f SPU: Optimize FCGT
- Optimize FCGT to a single signed integer comparison when possible
- Add is_spu_float_zero helper
2020-05-20 21:55:01 +03:00
Eladash
91d06a9729
SPU LLVM: fixup after #8175 (#8214)
Mask out RESULT cmd bit, do not create unbound branch blocks. (non-TSX)
2020-05-14 13:34:14 +01:00
Eladash
12f0278808 SPU LLVM: Improve MFC transfers recompilation for non-TSX 2020-05-13 11:10:13 +01:00
Nekotekina
e1042bc631 Get rid of "module" keyword
Workaround some intellisense problems.
2020-05-06 18:20:11 +03:00
Malcolm Jestadt
c1bd154bcd SPU: Optimize FMA ops with 0 addend 2020-05-01 17:52:10 +03:00