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https://github.com/RPCS3/rpcs3.git
synced 2025-07-11 17:28:36 +12:00
Fix handling of VRSAVE, and remove references to nonexistent USPRG registers.
This commit is contained in:
parent
e47d21024c
commit
ee508f85b4
5 changed files with 23 additions and 32 deletions
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@ -144,14 +144,8 @@ private:
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case 0x001: return CPU.XER.XER;
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case 0x001: return CPU.XER.XER;
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case 0x008: return CPU.LR;
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case 0x008: return CPU.LR;
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case 0x009: return CPU.CTR;
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case 0x009: return CPU.CTR;
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case 0x100:
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case 0x100: return CPU.VRSAVE;
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case 0x101:
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case 0x103: return CPU.SPRG[3];
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case 0x102:
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case 0x103:
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case 0x104:
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case 0x105:
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case 0x106:
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case 0x107: return CPU.USPRG[n - 0x100];
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case 0x10C: CPU.TB = get_time(); return CPU.TB;
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case 0x10C: CPU.TB = get_time(); return CPU.TB;
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case 0x10D: CPU.TB = get_time(); return CPU.TBH;
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case 0x10D: CPU.TB = get_time(); return CPU.TBH;
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@ -178,14 +172,8 @@ private:
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case 0x001: CPU.XER.XER = value; return;
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case 0x001: CPU.XER.XER = value; return;
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case 0x008: CPU.LR = value; return;
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case 0x008: CPU.LR = value; return;
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case 0x009: CPU.CTR = value; return;
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case 0x009: CPU.CTR = value; return;
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case 0x100:
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case 0x100: CPU.VRSAVE = (u32)value; return;
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case 0x101:
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case 0x103: throw fmt::Format("WriteSPR(0x103, 0x%llx): Write to read-only SPR", value);
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case 0x102:
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case 0x103:
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case 0x104:
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case 0x105:
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case 0x106:
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case 0x107: CPU.USPRG[n - 0x100] = value; return;
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case 0x10C: throw fmt::Format("WriteSPR(0x10C, 0x%llx): Write to time-based SPR", value);
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case 0x10C: throw fmt::Format("WriteSPR(0x10C, 0x%llx): Write to time-based SPR", value);
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case 0x10D: throw fmt::Format("WriteSPR(0x10D, 0x%llx): Write to time-based SPR", value);
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case 0x10D: throw fmt::Format("WriteSPR(0x10D, 0x%llx): Write to time-based SPR", value);
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@ -3311,7 +3311,7 @@ void Compiler::MFSPR(u32 rd, u32 spr) {
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rd_i64 = GetCtr();
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rd_i64 = GetCtr();
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break;
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break;
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case 0x100:
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case 0x100:
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rd_i64 = GetUsprg0();
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rd_i64 = GetVrsave();
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break;
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break;
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case 0x10C:
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case 0x10C:
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rd_i64 = Call<u64>("get_time", get_time);
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rd_i64 = Call<u64>("get_time", get_time);
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@ -3503,7 +3503,7 @@ void Compiler::MTSPR(u32 spr, u32 rs) {
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SetCtr(rs_i64);
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SetCtr(rs_i64);
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break;
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break;
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case 0x100:
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case 0x100:
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SetUsprg0(rs_i64);
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SetVrsave(rs_i64);
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break;
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break;
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default:
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default:
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assert(0);
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assert(0);
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@ -5278,17 +5278,19 @@ void Compiler::SetXerSo(Value * so) {
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SetXer(xer_i64);
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SetXer(xer_i64);
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}
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}
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Value * Compiler::GetUsprg0() {
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Value * Compiler::GetVrsave() {
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auto usrpg0_i8_ptr = m_ir_builder->CreateConstGEP1_32(m_state.args[CompileTaskState::Args::State], (unsigned int)offsetof(PPUThread, USPRG));
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auto vrsave_i8_ptr = m_ir_builder->CreateConstGEP1_32(m_state.args[CompileTaskState::Args::State], (unsigned int)offsetof(PPUThread, VRSAVE));
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auto usprg0_i64_ptr = m_ir_builder->CreateBitCast(usrpg0_i8_ptr, m_ir_builder->getInt64Ty()->getPointerTo());
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auto vrsave_i32_ptr = m_ir_builder->CreateBitCast(vrsave_i8_ptr, m_ir_builder->getInt32Ty()->getPointerTo());
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return m_ir_builder->CreateAlignedLoad(usprg0_i64_ptr, 8);
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auto val_i32 = m_ir_builder->CreateAlignedLoad(vrsave_i32_ptr, 4);
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return m_ir_builder->CreateZExtOrTrunc(val_i32, m_ir_builder->getInt64Ty());
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}
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}
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void Compiler::SetUsprg0(Value * val_x64) {
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void Compiler::SetVrsave(Value * val_x64) {
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auto val_i64 = m_ir_builder->CreateBitCast(val_x64, m_ir_builder->getInt64Ty());
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auto val_i64 = m_ir_builder->CreateBitCast(val_x64, m_ir_builder->getInt64Ty());
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auto usprg0_i8_ptr = m_ir_builder->CreateConstGEP1_32(m_state.args[CompileTaskState::Args::State], (unsigned int)offsetof(PPUThread, USPRG));
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auto val_i32 = m_ir_builder->CreateZExtOrTrunc(val_i64, m_ir_builder->getInt32Ty());
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auto usprg0_i64_ptr = m_ir_builder->CreateBitCast(usprg0_i8_ptr, m_ir_builder->getInt64Ty()->getPointerTo());
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auto vrsave_i8_ptr = m_ir_builder->CreateConstGEP1_32(m_state.args[CompileTaskState::Args::State], (unsigned int)offsetof(PPUThread, VRSAVE));
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m_ir_builder->CreateAlignedStore(val_i64, usprg0_i64_ptr, 8);
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auto vrsave_i32_ptr = m_ir_builder->CreateBitCast(vrsave_i8_ptr, m_ir_builder->getInt32Ty()->getPointerTo());
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m_ir_builder->CreateAlignedStore(val_i32, vrsave_i32_ptr, 8);
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}
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}
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Value * Compiler::GetFpscr() {
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Value * Compiler::GetFpscr() {
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@ -860,11 +860,11 @@ namespace ppu_recompiler_llvm {
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/// Set the SO bit of XER
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/// Set the SO bit of XER
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void SetXerSo(llvm::Value * so);
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void SetXerSo(llvm::Value * so);
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/// Get USPRG0
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/// Get VRSAVE
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llvm::Value * GetUsprg0();
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llvm::Value * GetVrsave();
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/// Set USPRG0
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/// Set VRSAVE
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void SetUsprg0(llvm::Value * val_x64);
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void SetVrsave(llvm::Value * val_x64);
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/// Load FPSCR
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/// Load FPSCR
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llvm::Value * GetFpscr();
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llvm::Value * GetFpscr();
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@ -43,7 +43,6 @@ void PPUThread::DoReset()
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memset(FPR, 0, sizeof(FPR));
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memset(FPR, 0, sizeof(FPR));
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memset(GPR, 0, sizeof(GPR));
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memset(GPR, 0, sizeof(GPR));
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memset(SPRG, 0, sizeof(SPRG));
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memset(SPRG, 0, sizeof(SPRG));
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memset(USPRG, 0, sizeof(USPRG));
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CR.CR = 0;
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CR.CR = 0;
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LR = 0;
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LR = 0;
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@ -52,6 +51,7 @@ void PPUThread::DoReset()
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XER.XER = 0;
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XER.XER = 0;
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FPSCR.FPSCR = 0;
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FPSCR.FPSCR = 0;
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VSCR.VSCR = 0;
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VSCR.VSCR = 0;
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VRSAVE = 0;
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cycle = 0;
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cycle = 0;
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}
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}
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@ -531,7 +531,8 @@ public:
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u64 LR; //SPR 0x008 : Link Register
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u64 LR; //SPR 0x008 : Link Register
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u64 CTR; //SPR 0x009 : Count Register
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u64 CTR; //SPR 0x009 : Count Register
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u64 USPRG[8]; //SPR 0x100 - 0x107: User-SPR General-Purpose Registers
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u32 VRSAVE; //SPR 0x100: VR Save/Restore Register (32 bits)
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u64 SPRG[8]; //SPR 0x110 - 0x117 : SPR General-Purpose Registers
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u64 SPRG[8]; //SPR 0x110 - 0x117 : SPR General-Purpose Registers
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//TBR : Time-Base Registers
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//TBR : Time-Base Registers
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