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Fix handling of VRSAVE, and remove references to nonexistent USPRG registers.

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This commit is contained in:
Andrew Church 2015-01-18 07:01:52 +09:00
parent e47d21024c
commit ee508f85b4
5 changed files with 23 additions and 32 deletions
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20
rpcs3/Emu/Cell/PPUInterpreter.h
View file

@ -144,14 +144,8 @@ private:
case 0x001: return CPU.XER.XER; case 0x001: return CPU.XER.XER;
case 0x008: return CPU.LR; case 0x008: return CPU.LR;
case 0x009: return CPU.CTR; case 0x009: return CPU.CTR;
case 0x100: case 0x100: return CPU.VRSAVE;
case 0x101: case 0x103: return CPU.SPRG[3];
case 0x102:
case 0x103:
case 0x104:
case 0x105:
case 0x106:
case 0x107: return CPU.USPRG[n - 0x100];
case 0x10C: CPU.TB = get_time(); return CPU.TB; case 0x10C: CPU.TB = get_time(); return CPU.TB;
case 0x10D: CPU.TB = get_time(); return CPU.TBH; case 0x10D: CPU.TB = get_time(); return CPU.TBH;
@ -178,14 +172,8 @@ private:
case 0x001: CPU.XER.XER = value; return; case 0x001: CPU.XER.XER = value; return;
case 0x008: CPU.LR = value; return; case 0x008: CPU.LR = value; return;
case 0x009: CPU.CTR = value; return; case 0x009: CPU.CTR = value; return;
case 0x100: case 0x100: CPU.VRSAVE = (u32)value; return;
case 0x101: case 0x103: throw fmt::Format("WriteSPR(0x103, 0x%llx): Write to read-only SPR", value);
case 0x102:
case 0x103:
case 0x104:
case 0x105:
case 0x106:
case 0x107: CPU.USPRG[n - 0x100] = value; return;
case 0x10C: throw fmt::Format("WriteSPR(0x10C, 0x%llx): Write to time-based SPR", value); case 0x10C: throw fmt::Format("WriteSPR(0x10C, 0x%llx): Write to time-based SPR", value);
case 0x10D: throw fmt::Format("WriteSPR(0x10D, 0x%llx): Write to time-based SPR", value); case 0x10D: throw fmt::Format("WriteSPR(0x10D, 0x%llx): Write to time-based SPR", value);

22
rpcs3/Emu/Cell/PPULLVMRecompiler.cpp
View file

@ -3311,7 +3311,7 @@ void Compiler::MFSPR(u32 rd, u32 spr) {
rd_i64 = GetCtr(); rd_i64 = GetCtr();
break; break;
case 0x100: case 0x100:
rd_i64 = GetUsprg0(); rd_i64 = GetVrsave();
break; break;
case 0x10C: case 0x10C:
rd_i64 = Call<u64>("get_time", get_time); rd_i64 = Call<u64>("get_time", get_time);
@ -3503,7 +3503,7 @@ void Compiler::MTSPR(u32 spr, u32 rs) {
SetCtr(rs_i64); SetCtr(rs_i64);
break; break;
case 0x100: case 0x100:
SetUsprg0(rs_i64); SetVrsave(rs_i64);
break; break;
default: default:
assert(0); assert(0);
@ -5278,17 +5278,19 @@ void Compiler::SetXerSo(Value * so) {
SetXer(xer_i64); SetXer(xer_i64);
} }
Value * Compiler::GetUsprg0() { Value * Compiler::GetVrsave() {
auto usrpg0_i8_ptr = m_ir_builder->CreateConstGEP1_32(m_state.args[CompileTaskState::Args::State], (unsigned int)offsetof(PPUThread, USPRG)); auto vrsave_i8_ptr = m_ir_builder->CreateConstGEP1_32(m_state.args[CompileTaskState::Args::State], (unsigned int)offsetof(PPUThread, VRSAVE));
auto usprg0_i64_ptr = m_ir_builder->CreateBitCast(usrpg0_i8_ptr, m_ir_builder->getInt64Ty()->getPointerTo()); auto vrsave_i32_ptr = m_ir_builder->CreateBitCast(vrsave_i8_ptr, m_ir_builder->getInt32Ty()->getPointerTo());
return m_ir_builder->CreateAlignedLoad(usprg0_i64_ptr, 8); auto val_i32 = m_ir_builder->CreateAlignedLoad(vrsave_i32_ptr, 4);
return m_ir_builder->CreateZExtOrTrunc(val_i32, m_ir_builder->getInt64Ty());
} }
void Compiler::SetUsprg0(Value * val_x64) { void Compiler::SetVrsave(Value * val_x64) {
auto val_i64 = m_ir_builder->CreateBitCast(val_x64, m_ir_builder->getInt64Ty()); auto val_i64 = m_ir_builder->CreateBitCast(val_x64, m_ir_builder->getInt64Ty());
auto usprg0_i8_ptr = m_ir_builder->CreateConstGEP1_32(m_state.args[CompileTaskState::Args::State], (unsigned int)offsetof(PPUThread, USPRG)); auto val_i32 = m_ir_builder->CreateZExtOrTrunc(val_i64, m_ir_builder->getInt32Ty());
auto usprg0_i64_ptr = m_ir_builder->CreateBitCast(usprg0_i8_ptr, m_ir_builder->getInt64Ty()->getPointerTo()); auto vrsave_i8_ptr = m_ir_builder->CreateConstGEP1_32(m_state.args[CompileTaskState::Args::State], (unsigned int)offsetof(PPUThread, VRSAVE));
m_ir_builder->CreateAlignedStore(val_i64, usprg0_i64_ptr, 8); auto vrsave_i32_ptr = m_ir_builder->CreateBitCast(vrsave_i8_ptr, m_ir_builder->getInt32Ty()->getPointerTo());
m_ir_builder->CreateAlignedStore(val_i32, vrsave_i32_ptr, 8);
} }
Value * Compiler::GetFpscr() { Value * Compiler::GetFpscr() {

8
rpcs3/Emu/Cell/PPULLVMRecompiler.h
View file

@ -860,11 +860,11 @@ namespace ppu_recompiler_llvm {
/// Set the SO bit of XER /// Set the SO bit of XER
void SetXerSo(llvm::Value * so); void SetXerSo(llvm::Value * so);
/// Get USPRG0 /// Get VRSAVE
llvm::Value * GetUsprg0(); llvm::Value * GetVrsave();
/// Set USPRG0 /// Set VRSAVE
void SetUsprg0(llvm::Value * val_x64); void SetVrsave(llvm::Value * val_x64);
/// Load FPSCR /// Load FPSCR
llvm::Value * GetFpscr(); llvm::Value * GetFpscr();

2
rpcs3/Emu/Cell/PPUThread.cpp
View file

@ -43,7 +43,6 @@ void PPUThread::DoReset()
memset(FPR, 0, sizeof(FPR)); memset(FPR, 0, sizeof(FPR));
memset(GPR, 0, sizeof(GPR)); memset(GPR, 0, sizeof(GPR));
memset(SPRG, 0, sizeof(SPRG)); memset(SPRG, 0, sizeof(SPRG));
memset(USPRG, 0, sizeof(USPRG));
CR.CR = 0; CR.CR = 0;
LR = 0; LR = 0;
@ -52,6 +51,7 @@ void PPUThread::DoReset()
XER.XER = 0; XER.XER = 0;
FPSCR.FPSCR = 0; FPSCR.FPSCR = 0;
VSCR.VSCR = 0; VSCR.VSCR = 0;
VRSAVE = 0;
cycle = 0; cycle = 0;
} }

3
rpcs3/Emu/Cell/PPUThread.h
View file

@ -531,7 +531,8 @@ public:
u64 LR; //SPR 0x008 : Link Register u64 LR; //SPR 0x008 : Link Register
u64 CTR; //SPR 0x009 : Count Register u64 CTR; //SPR 0x009 : Count Register
u64 USPRG[8]; //SPR 0x100 - 0x107: User-SPR General-Purpose Registers u32 VRSAVE; //SPR 0x100: VR Save/Restore Register (32 bits)
u64 SPRG[8]; //SPR 0x110 - 0x117 : SPR General-Purpose Registers u64 SPRG[8]; //SPR 0x110 - 0x117 : SPR General-Purpose Registers
//TBR : Time-Base Registers //TBR : Time-Base Registers