Fix an assign. Some other misc changes.

This commit is contained in:
Sacha 2014-03-26 10:29:17 +10:00
parent 3e9cbb4a24
commit ebc6b9e66e
2 changed files with 10 additions and 15 deletions

View file

@ -8,11 +8,11 @@
// Error Codes // Error Codes
enum enum
{ {
CELL_DMUX_ERROR_ARG = 0x80610201, CELL_DMUX_ERROR_ARG = 0x80610201,
CELL_DMUX_ERROR_SEQ = 0x80610202, CELL_DMUX_ERROR_SEQ = 0x80610202,
CELL_DMUX_ERROR_BUSY = 0x80610203, CELL_DMUX_ERROR_BUSY = 0x80610203,
CELL_DMUX_ERROR_EMPTY = 0x80610204, CELL_DMUX_ERROR_EMPTY = 0x80610204,
CELL_DMUX_ERROR_FATAL = 0x80610205, CELL_DMUX_ERROR_FATAL = 0x80610205,
}; };
enum CellDmuxStreamType enum CellDmuxStreamType
@ -605,14 +605,9 @@ public:
//(u32)info->auSize, put, (u32)info->ptsLower); //(u32)info->auSize, put, (u32)info->ptsLower);
u32 new_addr = a128(put + 128 + size); u32 new_addr = a128(put + 128 + size);
if ((new_addr + GetMaxAU()) > (memAddr + memSize)) put = ((new_addr + GetMaxAU()) > (memAddr + memSize))
{ ? memAddr : new_addr;
put = memAddr;
}
else
{
put = new_addr;
}
size = 0; size = 0;
put_count++; put_count++;
@ -750,7 +745,7 @@ public:
if (update_index) if (update_index)
{ {
/*u32 new_addr = a128(peek + 128 + info->auSize); /*u32 new_addr = a128(peek + 128 + info->auSize);
if (new_addr = put) if (new_addr == put)
{ {
peek = 0; peek = 0;
} }

View file

@ -175,7 +175,7 @@ bool SleepQueue::invalidate(u32 tid)
if (tid) for (u32 i = 0; i < list.GetCount(); i++) if (tid) for (u32 i = 0; i < list.GetCount(); i++)
{ {
if (list[i] = tid) if (list[i] == tid)
{ {
list.RemoveAt(i); list.RemoveAt(i);
return true; return true;