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https://github.com/RPCS3/rpcs3.git
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TTY output improved; ARMv7: new instructions
ADC_REG, MVN_REG, ORR_REG, ROR_IMM, ROR_REG, TST_IMM, armv7_fmt improved
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d5bbea097b
commit
e3f55a75a3
7 changed files with 426 additions and 76 deletions
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@ -402,11 +402,51 @@ void ARMv7_instrs::ADC_IMM(ARMv7Context& context, const ARMv7Code code, const AR
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void ARMv7_instrs::ADC_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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{
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bool set_flags = !context.ITSTATE;
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u32 cond, d, n, m, shift_t, shift_n;
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switch (type)
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{
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case T1:
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{
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cond = context.ITSTATE.advance();
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d = n = (code.data & 0x7);
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m = (code.data & 0x38) >> 3;
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shift_t = SRType_LSL;
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shift_n = 0;
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break;
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}
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case T2:
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{
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cond = context.ITSTATE.advance();
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d = (code.data & 0xf00) >> 8;
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n = (code.data & 0xf0000) >> 16;
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m = (code.data & 0xf);
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set_flags = (code.data & 0x100000);
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shift_t = DecodeImmShift((code.data & 0x30) >> 4, (code.data & 0x7000) >> 10 | (code.data & 0xc0) >> 6, &shift_n);
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reject(d == 13 || d == 15 || n == 13 || n == 15 || m == 13 || m == 15, "UNPREDICTABLE");
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break;
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}
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case A1: throw __FUNCTION__;
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default: throw __FUNCTION__;
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}
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if (ConditionPassed(context, cond))
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{
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bool carry, overflow;
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const u32 shifted = Shift(context.read_gpr(m), shift_t, shift_n, context.APSR.C);
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const u32 result = AddWithCarry(context.read_gpr(n), shifted, context.APSR.C, carry, overflow);
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context.write_gpr(d, result);
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if (set_flags)
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{
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context.APSR.N = result >> 31;
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context.APSR.Z = result == 0;
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context.APSR.C = carry;
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context.APSR.V = overflow;
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}
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}
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}
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void ARMv7_instrs::ADC_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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@ -1359,6 +1399,34 @@ void ARMv7_instrs::CMP_RSR(ARMv7Context& context, const ARMv7Code code, const AR
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}
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void ARMv7_instrs::DBG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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{
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switch (type)
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{
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case A1: throw __FUNCTION__;
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default: throw __FUNCTION__;
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}
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}
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void ARMv7_instrs::DMB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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{
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switch (type)
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{
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case A1: throw __FUNCTION__;
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default: throw __FUNCTION__;
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}
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}
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void ARMv7_instrs::DSB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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{
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switch (type)
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{
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case A1: throw __FUNCTION__;
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default: throw __FUNCTION__;
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}
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}
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void ARMv7_instrs::EOR_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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{
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switch (type)
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@ -2541,11 +2609,49 @@ void ARMv7_instrs::MVN_IMM(ARMv7Context& context, const ARMv7Code code, const AR
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void ARMv7_instrs::MVN_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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{
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bool set_flags = !context.ITSTATE;
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u32 cond, d, m, shift_t, shift_n;
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switch (type)
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{
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case T1:
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{
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cond = context.ITSTATE.advance();
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d = (code.data & 0x7);
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m = (code.data & 0x38) >> 3;
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shift_t = SRType_LSL;
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shift_n = 0;
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break;
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}
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case T2:
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{
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cond = context.ITSTATE.advance();
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d = (code.data & 0xf00) >> 8;
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m = (code.data & 0xf);
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set_flags = (code.data & 0x100000);
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shift_t = DecodeImmShift((code.data & 0x30) >> 4, (code.data & 0x7000) >> 10 | (code.data & 0xc0) >> 6, &shift_n);
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reject(d == 13 || d == 15 || m == 13 || m == 15, "UNPREDICTABLE");
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break;
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}
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case A1: throw __FUNCTION__;
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default: throw __FUNCTION__;
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}
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if (ConditionPassed(context, cond))
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{
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bool carry;
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const u32 shifted = Shift_C(context.read_gpr(m), shift_t, shift_n, context.APSR.C, carry);
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const u32 result = ~shifted;
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context.write_gpr(d, result);
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if (set_flags)
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{
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context.APSR.N = result >> 31;
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context.APSR.Z = result == 0;
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context.APSR.C = carry;
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}
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}
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}
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void ARMv7_instrs::MVN_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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@ -2646,11 +2752,51 @@ void ARMv7_instrs::ORR_IMM(ARMv7Context& context, const ARMv7Code code, const AR
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void ARMv7_instrs::ORR_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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{
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bool set_flags = !context.ITSTATE;
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u32 cond, d, n, m, shift_t, shift_n;
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switch (type)
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{
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case T1:
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{
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cond = context.ITSTATE.advance();
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d = n = (code.data & 0x7);
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m = (code.data & 0x38) >> 3;
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shift_t = SRType_LSL;
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shift_n = 0;
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break;
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}
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case T2:
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{
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cond = context.ITSTATE.advance();
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d = (code.data & 0xf00) >> 8;
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n = (code.data & 0xf0000) >> 16;
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m = (code.data & 0xf);
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set_flags = (code.data & 0x100000);
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shift_t = DecodeImmShift((code.data & 0x30) >> 4, (code.data & 0x7000) >> 10 | (code.data & 0xc0) >> 6, &shift_n);
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reject(n == 15, "ROR (immediate)");
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reject(d == 13 || d == 15 || n == 13 || m == 13 || m == 15, "UNPREDICTABLE");
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break;
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}
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case A1: throw __FUNCTION__;
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default: throw __FUNCTION__;
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}
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if (ConditionPassed(context, cond))
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{
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bool carry;
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const u32 shifted = Shift_C(context.read_gpr(m), shift_t, shift_n, context.APSR.C, carry);
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const u32 result = context.read_gpr(n) | shifted;
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context.write_gpr(d, result);
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if (set_flags)
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{
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context.APSR.N = result >> 31;
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context.APSR.Z = result == 0;
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context.APSR.C = carry;
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}
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}
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}
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void ARMv7_instrs::ORR_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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@ -2936,20 +3082,84 @@ void ARMv7_instrs::REVSH(ARMv7Context& context, const ARMv7Code code, const ARMv
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void ARMv7_instrs::ROR_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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{
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u32 cond, d, m, shift_n;
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bool set_flags;
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switch (type)
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{
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case T1:
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{
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cond = context.ITSTATE.advance();
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d = (code.data & 0xf00) >> 8;
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m = (code.data & 0xf);
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set_flags = (code.data & 0x100000);
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const u32 shift_t = DecodeImmShift(3, (code.data & 0x7000) >> 10 | (code.data & 0xc0) >> 6, &shift_n);
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reject(shift_t == SRType_RRX, "RRX");
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reject(d == 13 || d == 15 || m == 13 || m == 15, "UNPREDICTABLE");
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break;
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}
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case A1: throw __FUNCTION__;
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default: throw __FUNCTION__;
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}
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if (ConditionPassed(context, cond))
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{
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bool carry;
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const u32 result = Shift_C(context.read_gpr(m), SRType_ROR, shift_n, context.APSR.C, carry);
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context.write_gpr(d, result);
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if (set_flags)
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{
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context.APSR.N = result >> 31;
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context.APSR.Z = result == 0;
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context.APSR.C = carry;
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}
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}
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}
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void ARMv7_instrs::ROR_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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{
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bool set_flags = !context.ITSTATE;
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u32 cond, d, n, m;
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switch (type)
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{
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case T1:
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{
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cond = context.ITSTATE.advance();
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d = n = (code.data & 0x7);
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m = (code.data & 0x38) >> 3;
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break;
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}
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case T2:
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{
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d = (code.data & 0xf00) >> 8;
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n = (code.data & 0xf0000) >> 16;
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m = (code.data & 0xf);
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set_flags = (code.data & 0x100000);
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reject(d == 13 || d == 15 || n == 13 || n == 15 || m == 13 || m == 15, "UNPREDICTABLE");
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break;
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}
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case A1: throw __FUNCTION__;
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default: throw __FUNCTION__;
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}
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if (ConditionPassed(context, cond))
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{
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bool carry;
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const u32 shift_n = context.read_gpr(m) & 0xff;
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const u32 result = Shift_C(context.read_gpr(n), SRType_ROR, shift_n, context.APSR.C, carry);
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context.write_gpr(d, result);
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if (set_flags)
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{
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context.APSR.N = result >> 31;
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context.APSR.Z = result == 0;
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context.APSR.C = carry;
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}
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}
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}
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@ -4212,11 +4422,31 @@ void ARMv7_instrs::TEQ_RSR(ARMv7Context& context, const ARMv7Code code, const AR
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void ARMv7_instrs::TST_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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{
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bool carry = context.APSR.C;
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u32 cond, n, imm32;
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switch (type)
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{
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case T1:
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{
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cond = context.ITSTATE.advance();
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n = (code.data & 0xf0000) >> 16;
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imm32 = ThumbExpandImm_C((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff), carry, carry);
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reject(n == 13 || n == 15, "UNPREDICTABLE");
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break;
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}
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case A1: throw __FUNCTION__;
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default: throw __FUNCTION__;
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}
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if (ConditionPassed(context, cond))
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{
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const u32 result = context.read_gpr(n) & imm32;
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context.APSR.N = result >> 31;
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context.APSR.Z = result == 0;
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context.APSR.C = carry;
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}
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}
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void ARMv7_instrs::TST_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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