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rsx: Changes to surface pitch handling
- Zeta pitch is ignored by real HW for some reason - Monitor ptch value changes as well since they may affect disabled surfaces - TODO: Verify if MRT pitch is really taken into consideration
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89bc333295
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3 changed files with 11 additions and 23 deletions
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@ -186,17 +186,12 @@ void GLGSRender::init_buffers(rsx::framebuffer_creation_context context, bool sk
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const auto depth_format = rsx::method_registers.surface_depth_fmt();
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const auto depth_format = rsx::method_registers.surface_depth_fmt();
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const auto target = rsx::method_registers.surface_color_target();
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const auto target = rsx::method_registers.surface_color_target();
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const auto required_z_pitch = depth_format == rsx::surface_depth_format::z16 ? clip_horizontal * 2u : clip_horizontal * 4u;
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//NOTE: Z buffers with pitch = 64 are valid even if they would not fit (GT HD Concept)
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const auto required_color_pitch = std::max<u32>((u32)rsx::utility::get_packed_pitch(surface_format, clip_horizontal), 64u);
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const auto required_color_pitch = std::max<u32>((u32)rsx::utility::get_packed_pitch(surface_format, clip_horizontal), 64u);
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if (depth_address)
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if (depth_address)
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{
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{
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//TODO: Verify that buffers <= 16 pixels in X (pitch=64) cannot have a depth buffer
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if (!rsx::method_registers.depth_test_enabled() && target != rsx::surface_target::none)
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if (zeta_pitch < required_z_pitch || zeta_pitch <= 64)
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{
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depth_address = 0;
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}
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else if (!rsx::method_registers.depth_test_enabled() && target != rsx::surface_target::none)
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{
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{
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//Disable depth buffer if depth testing is not enabled, unless a clear command is targeting the depth buffer
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//Disable depth buffer if depth testing is not enabled, unless a clear command is targeting the depth buffer
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const bool is_depth_clear = !!(context & rsx::framebuffer_creation_context::context_clear_depth);
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const bool is_depth_clear = !!(context & rsx::framebuffer_creation_context::context_clear_depth);
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@ -213,8 +208,7 @@ void GLGSRender::init_buffers(rsx::framebuffer_creation_context context, bool sk
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if (pitchs[index] < required_color_pitch)
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if (pitchs[index] < required_color_pitch)
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surface_addresses[index] = 0;
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surface_addresses[index] = 0;
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if (surface_addresses[index] == depth_address &&
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if (surface_addresses[index] == depth_address)
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zeta_pitch >= required_z_pitch)
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{
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{
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LOG_TRACE(RSX, "Framebuffer at 0x%X has aliasing color/depth targets, zeta_pitch = %d, color_pitch=%d", depth_address, zeta_pitch, pitchs[index]);
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LOG_TRACE(RSX, "Framebuffer at 0x%X has aliasing color/depth targets, zeta_pitch = %d, color_pitch=%d", depth_address, zeta_pitch, pitchs[index]);
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//TODO: Research clearing both depth AND color
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//TODO: Research clearing both depth AND color
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@ -376,11 +370,6 @@ void GLGSRender::init_buffers(rsx::framebuffer_creation_context context, bool sk
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if (m_depth_surface_info.depth_format != rsx::surface_depth_format::z16) pitch *= 2;
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if (m_depth_surface_info.depth_format != rsx::surface_depth_format::z16) pitch *= 2;
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const u32 range = pitch * m_depth_surface_info.height;
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const u32 range = pitch * m_depth_surface_info.height;
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//TODO: Verify that depth surface pitch variance affects results
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if (pitch != m_depth_surface_info.pitch)
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LOG_WARNING(RSX, "Depth surface pitch does not match computed pitch, %d vs %d", m_depth_surface_info.pitch, pitch);
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m_gl_texture_cache.lock_memory_region(std::get<1>(m_rtts.m_bound_depth_stencil), m_depth_surface_info.address, range, m_depth_surface_info.width, m_depth_surface_info.height, pitch,
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m_gl_texture_cache.lock_memory_region(std::get<1>(m_rtts.m_bound_depth_stencil), m_depth_surface_info.address, range, m_depth_surface_info.width, m_depth_surface_info.height, pitch,
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depth_format_gl.format, depth_format_gl.type, true);
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depth_format_gl.format, depth_format_gl.type, true);
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}
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}
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@ -2425,17 +2425,12 @@ void VKGSRender::prepare_rtts(rsx::framebuffer_creation_context context)
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const auto depth_fmt = rsx::method_registers.surface_depth_fmt();
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const auto depth_fmt = rsx::method_registers.surface_depth_fmt();
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const auto target = rsx::method_registers.surface_color_target();
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const auto target = rsx::method_registers.surface_color_target();
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const auto required_z_pitch = depth_fmt == rsx::surface_depth_format::z16 ? clip_width * 2 : clip_width * 4;
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//NOTE: Z buffers with pitch = 64 are valid even if they would not fit (GT HD Concept)
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const auto required_color_pitch = std::max<u32>((u32)rsx::utility::get_packed_pitch(color_fmt, clip_width), 64u);
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const auto required_color_pitch = std::max<u32>((u32)rsx::utility::get_packed_pitch(color_fmt, clip_width), 64u);
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if (zeta_address)
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if (zeta_address)
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{
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{
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//TODO: Verify that buffers <= 16 pixels in X (pitch=64) cannot have a depth buffer
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if (!rsx::method_registers.depth_test_enabled() && target != rsx::surface_target::none)
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if (zeta_pitch < required_z_pitch || zeta_pitch <= 64)
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{
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zeta_address = 0;
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}
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else if (!rsx::method_registers.depth_test_enabled() && target != rsx::surface_target::none)
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{
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{
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//Disable depth buffer if depth testing is not enabled, unless a clear command is targeting the depth buffer
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//Disable depth buffer if depth testing is not enabled, unless a clear command is targeting the depth buffer
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const bool is_depth_clear = !!(context & rsx::framebuffer_creation_context::context_clear_depth);
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const bool is_depth_clear = !!(context & rsx::framebuffer_creation_context::context_clear_depth);
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@ -2452,8 +2447,7 @@ void VKGSRender::prepare_rtts(rsx::framebuffer_creation_context context)
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if (surface_pitchs[index] < required_color_pitch)
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if (surface_pitchs[index] < required_color_pitch)
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surface_addresses[index] = 0;
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surface_addresses[index] = 0;
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if (surface_addresses[index] == zeta_address &&
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if (surface_addresses[index] == zeta_address)
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zeta_pitch >= required_z_pitch)
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{
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{
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LOG_TRACE(RSX, "Framebuffer at 0x%X has aliasing color/depth targets, zeta_pitch = %d, color_pitch=%d", zeta_address, zeta_pitch, surface_pitchs[index]);
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LOG_TRACE(RSX, "Framebuffer at 0x%X has aliasing color/depth targets, zeta_pitch = %d, color_pitch=%d", zeta_address, zeta_pitch, surface_pitchs[index]);
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if (context == rsx::framebuffer_creation_context::context_clear_depth ||
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if (context == rsx::framebuffer_creation_context::context_clear_depth ||
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@ -1581,6 +1581,11 @@ namespace rsx
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bind<NV4097_SET_CONTEXT_DMA_COLOR_D, nv4097::set_surface_dirty_bit>();
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bind<NV4097_SET_CONTEXT_DMA_COLOR_D, nv4097::set_surface_dirty_bit>();
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bind<NV4097_SET_CONTEXT_DMA_ZETA, nv4097::set_surface_dirty_bit>();
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bind<NV4097_SET_CONTEXT_DMA_ZETA, nv4097::set_surface_dirty_bit>();
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bind<NV4097_SET_SURFACE_FORMAT, nv4097::set_surface_dirty_bit>();
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bind<NV4097_SET_SURFACE_FORMAT, nv4097::set_surface_dirty_bit>();
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bind<NV4097_SET_SURFACE_PITCH_A, nv4097::set_surface_dirty_bit>();
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bind<NV4097_SET_SURFACE_PITCH_B, nv4097::set_surface_dirty_bit>();
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bind<NV4097_SET_SURFACE_PITCH_C, nv4097::set_surface_dirty_bit>();
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bind<NV4097_SET_SURFACE_PITCH_D, nv4097::set_surface_dirty_bit>();
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bind<NV4097_SET_SURFACE_PITCH_Z, nv4097::set_surface_dirty_bit>();
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bind_range<NV4097_SET_TEXTURE_OFFSET, 8, 16, nv4097::set_texture_dirty_bit>();
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bind_range<NV4097_SET_TEXTURE_OFFSET, 8, 16, nv4097::set_texture_dirty_bit>();
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bind_range<NV4097_SET_TEXTURE_FORMAT, 8, 16, nv4097::set_texture_dirty_bit>();
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bind_range<NV4097_SET_TEXTURE_FORMAT, 8, 16, nv4097::set_texture_dirty_bit>();
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bind_range<NV4097_SET_TEXTURE_ADDRESS, 8, 16, nv4097::set_texture_dirty_bit>();
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bind_range<NV4097_SET_TEXTURE_ADDRESS, 8, 16, nv4097::set_texture_dirty_bit>();
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