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rsx: Pass vertex attributes streamed via register write in PS3-correct format
- TODO: Optimize this, we can avoid the double bswap in FIFO and then in attribute push Not very important since nobody is doing register push in high-performance path.
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6f874be41b
commit
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3 changed files with 10 additions and 29 deletions
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@ -341,9 +341,10 @@ namespace glsl
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" ret.xy = unpackHalf2x16(tmp.x);\n"
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" ret.xy = unpackHalf2x16(tmp.x);\n"
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" ret.zw = unpackHalf2x16(tmp.y);\n"
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" ret.zw = unpackHalf2x16(tmp.y);\n"
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" }\n"
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" }\n"
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" else if (desc.type == VTX_FMT_UINT8 || desc.type == VTX_FMT_UNORM8)\n"
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" else if (elem_size == 1) //(desc.type == VTX_FMT_UINT8 || desc.type == VTX_FMT_UNORM8)\n"
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" {\n"
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" {\n"
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" ret = vec4(desc.swap_bytes? result.wzyx : result);\n"
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" // Ignore bswap on single byte channels\n"
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" ret = vec4(result);\n"
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" }\n"
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" }\n"
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" else //if (desc.type == VTX_FMT_COMP32)\n"
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" else //if (desc.type == VTX_FMT_COMP32)\n"
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" {\n"
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" {\n"
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@ -2279,27 +2279,14 @@ namespace rsx
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}
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}
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} //end attribute placement check
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} //end attribute placement check
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// If data is passed via registers, it is already received in little endian
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// Special compressed 4 components into one 4-byte value. Decoded as one value.
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const bool is_be_type = (layout.attribute_placement[index] != attribute_buffer_placement::transient);
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if (type == rsx::vertex_base_type::cmp)
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bool to_swap_bytes = is_be_type;
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switch (type)
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{
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{
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case rsx::vertex_base_type::cmp:
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// Compressed 4 components into one 4-byte value
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size = 1;
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size = 1;
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break;
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case rsx::vertex_base_type::ub:
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case rsx::vertex_base_type::ub256:
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// These are single byte formats, but inverted order (BGRA vs ARGB) when passed via registers
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to_swap_bytes = (layout.attribute_placement[index] == attribute_buffer_placement::transient);
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break;
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default:
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break;
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}
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}
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if (to_swap_bytes) attrib1 |= swap_storage_mask;
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// All data is passed in in PS3-native order (BE) so swap flag should be set
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attrib1 |= swap_storage_mask;
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attrib0 |= (static_cast<s32>(type) << 24);
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attrib0 |= (static_cast<s32>(type) << 24);
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attrib0 |= (size << 27);
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attrib0 |= (size << 27);
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attrib1 |= offset_in_block[index];
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attrib1 |= offset_in_block[index];
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@ -263,16 +263,8 @@ namespace rsx
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const auto vtype = vertex_data_type_from_element_type<type>::type;
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const auto vtype = vertex_data_type_from_element_type<type>::type;
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ensure(vtype != rsx::vertex_base_type::cmp);
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ensure(vtype != rsx::vertex_base_type::cmp);
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switch (vtype)
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{
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case rsx::vertex_base_type::ub:
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case rsx::vertex_base_type::ub256:
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// Get BE data
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// Get BE data
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arg = std::bit_cast<u32, be_t<u32>>(arg);
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arg = std::bit_cast<u32, be_t<u32>>(arg);
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break;
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default:
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break;
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}
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if (rsx->in_begin_end)
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if (rsx->in_begin_end)
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{
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{
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@ -398,6 +390,7 @@ namespace rsx
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void draw_inline_array(thread* /*rsx*/, u32 /*reg*/, u32 arg)
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void draw_inline_array(thread* /*rsx*/, u32 /*reg*/, u32 arg)
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{
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{
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arg = std::bit_cast<u32, be_t<u32>>(arg);
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rsx::method_registers.current_draw_clause.command = rsx::draw_command::inlined_array;
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rsx::method_registers.current_draw_clause.command = rsx::draw_command::inlined_array;
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rsx::method_registers.current_draw_clause.inline_vertex_array.push_back(arg);
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rsx::method_registers.current_draw_clause.inline_vertex_array.push_back(arg);
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}
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}
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