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Use spaces for vertical alignment
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lioncash
parent
e25796f0d0
commit
d0c9d7c0ae
96 changed files with 2990 additions and 2992 deletions
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@ -21,40 +21,40 @@ enum
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enum
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{
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PPU_THREAD_STATUS_IDLE = (1 << 0),
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PPU_THREAD_STATUS_RUNNABLE = (1 << 1),
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PPU_THREAD_STATUS_ONPROC = (1 << 2),
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PPU_THREAD_STATUS_SLEEP = (1 << 3),
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PPU_THREAD_STATUS_STOP = (1 << 4),
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PPU_THREAD_STATUS_ZOMBIE = (1 << 5),
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PPU_THREAD_STATUS_DELETED = (1 << 6),
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PPU_THREAD_STATUS_UNKNOWN = (1 << 7),
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PPU_THREAD_STATUS_IDLE = (1 << 0),
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PPU_THREAD_STATUS_RUNNABLE = (1 << 1),
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PPU_THREAD_STATUS_ONPROC = (1 << 2),
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PPU_THREAD_STATUS_SLEEP = (1 << 3),
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PPU_THREAD_STATUS_STOP = (1 << 4),
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PPU_THREAD_STATUS_ZOMBIE = (1 << 5),
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PPU_THREAD_STATUS_DELETED = (1 << 6),
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PPU_THREAD_STATUS_UNKNOWN = (1 << 7),
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};
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enum FPSCR_EXP
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{
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FPSCR_FX = 0x80000000,
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FPSCR_FEX = 0x40000000,
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FPSCR_VX = 0x20000000,
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FPSCR_OX = 0x10000000,
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FPSCR_FX = 0x80000000,
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FPSCR_FEX = 0x40000000,
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FPSCR_VX = 0x20000000,
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FPSCR_OX = 0x10000000,
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FPSCR_UX = 0x08000000,
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FPSCR_ZX = 0x04000000,
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FPSCR_XX = 0x02000000,
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FPSCR_VXSNAN = 0x01000000,
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FPSCR_UX = 0x08000000,
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FPSCR_ZX = 0x04000000,
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FPSCR_XX = 0x02000000,
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FPSCR_VXSNAN = 0x01000000,
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FPSCR_VXISI = 0x00800000,
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FPSCR_VXIDI = 0x00400000,
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FPSCR_VXZDZ = 0x00200000,
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FPSCR_VXIMZ = 0x00100000,
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FPSCR_VXISI = 0x00800000,
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FPSCR_VXIDI = 0x00400000,
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FPSCR_VXZDZ = 0x00200000,
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FPSCR_VXIMZ = 0x00100000,
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FPSCR_VXVC = 0x00080000,
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FPSCR_FR = 0x00040000,
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FPSCR_FI = 0x00020000,
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FPSCR_VXVC = 0x00080000,
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FPSCR_FR = 0x00040000,
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FPSCR_FI = 0x00020000,
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FPSCR_VXSOFT = 0x00000400,
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FPSCR_VXSQRT = 0x00000200,
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FPSCR_VXCVI = 0x00000100,
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FPSCR_VXSOFT = 0x00000400,
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FPSCR_VXSQRT = 0x00000200,
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FPSCR_VXCVI = 0x00000100,
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};
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enum FPSCR_RN
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@ -74,33 +74,33 @@ union FPSCRhdr
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{
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struct
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{
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u32 RN :2; //Floating-point rounding control
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u32 NI :1; //Floating-point non-IEEE mode
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u32 XE :1; //Floating-point inexact exception enable
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u32 ZE :1; //IEEE floating-point zero divide exception enable
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u32 UE :1; //IEEE floating-point underflow exception enable
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u32 OE :1; //IEEE floating-point overflow exception enable
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u32 VE :1; //Floating-point invalid operation exception enable
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u32 VXCVI :1; //Floating-point invalid operation exception for invalid integer convert
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u32 VXSQRT :1; //Floating-point invalid operation exception for invalid square root
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u32 VXSOFT :1; //Floating-point invalid operation exception for software request
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u32 :1; //Reserved
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u32 FPRF :5; //Floating-point result flags
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u32 FI :1; //Floating-point fraction inexact
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u32 FR :1; //Floating-point fraction rounded
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u32 VXVC :1; //Floating-point invalid operation exception for invalid compare
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u32 VXIMZ :1; //Floating-point invalid operation exception for * * 0
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u32 VXZDZ :1; //Floating-point invalid operation exception for 0 / 0
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u32 VXIDI :1; //Floating-point invalid operation exception for * + *
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u32 VXISI :1; //Floating-point invalid operation exception for * - *
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u32 VXSNAN :1; //Floating-point invalid operation exception for SNaN
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u32 XX :1; //Floating-point inexact exception
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u32 ZX :1; //Floating-point zero divide exception
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u32 UX :1; //Floating-point underflow exception
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u32 OX :1; //Floating-point overflow exception
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u32 VX :1; //Floating-point invalid operation exception summary
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u32 FEX :1; //Floating-point enabled exception summary
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u32 FX :1; //Floating-point exception summary
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u32 RN :2; //Floating-point rounding control
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u32 NI :1; //Floating-point non-IEEE mode
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u32 XE :1; //Floating-point inexact exception enable
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u32 ZE :1; //IEEE floating-point zero divide exception enable
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u32 UE :1; //IEEE floating-point underflow exception enable
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u32 OE :1; //IEEE floating-point overflow exception enable
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u32 VE :1; //Floating-point invalid operation exception enable
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u32 VXCVI :1; //Floating-point invalid operation exception for invalid integer convert
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u32 VXSQRT :1; //Floating-point invalid operation exception for invalid square root
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u32 VXSOFT :1; //Floating-point invalid operation exception for software request
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u32 :1; //Reserved
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u32 FPRF :5; //Floating-point result flags
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u32 FI :1; //Floating-point fraction inexact
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u32 FR :1; //Floating-point fraction rounded
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u32 VXVC :1; //Floating-point invalid operation exception for invalid compare
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u32 VXIMZ :1; //Floating-point invalid operation exception for * * 0
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u32 VXZDZ :1; //Floating-point invalid operation exception for 0 / 0
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u32 VXIDI :1; //Floating-point invalid operation exception for * + *
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u32 VXISI :1; //Floating-point invalid operation exception for * - *
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u32 VXSNAN :1; //Floating-point invalid operation exception for SNaN
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u32 XX :1; //Floating-point inexact exception
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u32 ZX :1; //Floating-point zero divide exception
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u32 UX :1; //Floating-point underflow exception
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u32 OX :1; //Floating-point overflow exception
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u32 VX :1; //Floating-point invalid operation exception summary
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u32 FEX :1; //Floating-point enabled exception summary
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u32 FX :1; //Floating-point exception summary
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};
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u32 FPSCR;
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@ -113,38 +113,38 @@ union MSRhdr
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//Little-endian mode enable
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//0 The processor runs in big-endian mode.
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//1 The processor runs in little-endian mode.
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u64 LE : 1;
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u64 LE : 1;
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//Recoverable exception (for system reset and machine check exceptions).
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//0 Exception is not recoverable.
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//1 Exception is recoverable.
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u64 RI : 1;
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u64 RI : 1;
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//Reserved
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u64 : 2;
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u64 : 2;
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//Data address translation
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//0 Data address translation is disabled.
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//1 Data address translation is enabled.
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u64 DR : 1;
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u64 DR : 1;
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//Instruction address translation
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//0 Instruction address translation is disabled.
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//1 Instruction address translation is enabled.
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u64 IR : 1;
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u64 IR : 1;
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//Exception prefix. The setting of this bit specifies whether an exception vector offset
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//is prepended with Fs or 0s. In the following description, nnnnn is the offset of the
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//exception.
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//0 Exceptions are vectored to the physical address 0x0000_0000_000n_nnnn in 64-bit implementations.
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//1 Exceptions are vectored to the physical address 0xFFFF_FFFF_FFFn_nnnn in 64-bit implementations.
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u64 IP : 1;
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u64 IP : 1;
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//Reserved
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u64 : 1;
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u64 : 1;
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//Floating-point exception mode 1
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u64 FE1 : 1;
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u64 FE1 : 1;
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//Branch trace enable (Optional)
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//0 The processor executes branch instructions normally.
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@ -152,62 +152,62 @@ union MSRhdr
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//execution of a branch instruction, regardless of whether or not the branch was
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//taken.
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//Note: If the function is not implemented, this bit is treated as reserved.
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u64 BE : 1;
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u64 BE : 1;
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//Single-step trace enable (Optional)
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//0 The processor executes instructions normally.
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//1 The processor generates a single-step trace exception upon the successful
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//execution of the next instruction.
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//Note: If the function is not implemented, this bit is treated as reserved.
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u64 SE : 1;
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u64 SE : 1;
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//Floating-point exception mode 0
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u64 FE0 : 1;
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u64 FE0 : 1;
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//Machine check enable
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//0 Machine check exceptions are disabled.
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//1 Machine check exceptions are enabled.
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u64 ME : 1;
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u64 ME : 1;
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//Floating-point available
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//0 The processor prevents dispatch of floating-point instructions, including
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//floating-point loads, stores, and moves.
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//1 The processor can execute floating-point instructions.
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u64 FP : 1;
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u64 FP : 1;
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//Privilege level
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//0 The processor can execute both user- and supervisor-level instructions.
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//1 The processor can only execute user-level instructions.
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u64 PR : 1;
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u64 PR : 1;
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//External interrupt enable
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//0 While the bit is cleared the processor delays recognition of external interrupts
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//and decrementer exception conditions.
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//1 The processor is enabled to take an external interrupt or the decrementer
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//exception.
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u64 EE : 1;
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u64 EE : 1;
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//Exception little-endian mode. When an exception occurs, this bit is copied into
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//MSR[LE] to select the endian mode for the context established by the exception
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u64 ILE : 1;
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u64 ILE : 1;
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//Reserved
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u64 : 1;
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u64 : 1;
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//Power management enable
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//0 Power management disabled (normal operation mode).
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//1 Power management enabled (reduced power mode).
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//Note: Power management functions are implementation-dependent. If the function
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//is not implemented, this bit is treated as reserved.
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u64 POW : 1;
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u64 POW : 1;
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//Reserved
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u64 : 44;
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u64 : 44;
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//Sixty-four bit mode
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//0 The 64-bit processor runs in 32-bit mode.
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//1 The 64-bit processor runs in 64-bit mode. Note that this is the default setting.
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u64 SF : 1;
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u64 SF : 1;
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};
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u64 MSR;
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@ -230,14 +230,14 @@ union CRhdr
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struct
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{
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u8 cr7 : 4;
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u8 cr6 : 4;
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u8 cr5 : 4;
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u8 cr4 : 4;
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u8 cr3 : 4;
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u8 cr2 : 4;
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u8 cr1 : 4;
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u8 cr0 : 4;
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u8 cr7 : 4;
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u8 cr6 : 4;
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u8 cr5 : 4;
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u8 cr4 : 4;
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u8 cr3 : 4;
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u8 cr2 : 4;
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u8 cr1 : 4;
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u8 cr0 : 4;
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};
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};
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@ -247,10 +247,10 @@ union XERhdr
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struct
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{
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u64 L : 61;
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u64 CA : 1;
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u64 OV : 1;
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u64 SO : 1;
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u64 L : 61;
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u64 CA : 1;
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u64 OV : 1;
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u64 SO : 1;
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};
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};
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@ -279,8 +279,8 @@ union VSCRhdr
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Vector Convert to Fixed-Point with Saturation (vctuxs, vctsxs)
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0 Indicates no saturation occurred; mtvscr can explicitly clear this bit.
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*/
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u32 SAT : 1;
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u32 X : 15;
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u32 SAT : 1;
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u32 X : 15;
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/*
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Non-Java. A mode control bit that determines whether vector floating-point operations will be performed
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@ -292,8 +292,8 @@ union VSCRhdr
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exception, the corresponding element in the target VR is cleared to ‘0’. In both cases, the ‘0’
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has the same sign as the denormalized or underflowing value.
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*/
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u32 NJ : 1;
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u32 Y : 15;
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u32 NJ : 1;
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u32 Y : 15;
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};
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};
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@ -327,16 +327,16 @@ struct PPCdouble
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struct
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{
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u64 frac : 52;
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u64 exp : 11;
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u64 sign : 1;
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u64 frac : 52;
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u64 exp : 11;
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u64 sign : 1;
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};
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struct
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{
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u64 : 51;
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u64 : 51;
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u64 nan : 1;
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u64 : 12;
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u64 : 12;
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};
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};
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@ -360,24 +360,24 @@ struct PPCdouble
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switch(fpc)
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{
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case _FPCLASS_SNAN:// return FPR_SNAN;
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case _FPCLASS_QNAN: return FPR_QNAN;
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case _FPCLASS_NINF: return FPR_NINF;
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case _FPCLASS_NN: return FPR_NN;
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case _FPCLASS_ND: return FPR_ND;
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case _FPCLASS_NZ: return FPR_NZ;
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case _FPCLASS_PZ: return FPR_PZ;
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case _FPCLASS_PD: return FPR_PD;
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case _FPCLASS_PN: return FPR_PN;
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case _FPCLASS_PINF: return FPR_PINF;
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case _FPCLASS_QNAN: return FPR_QNAN;
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case _FPCLASS_NINF: return FPR_NINF;
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case _FPCLASS_NN: return FPR_NN;
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case _FPCLASS_ND: return FPR_ND;
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case _FPCLASS_NZ: return FPR_NZ;
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case _FPCLASS_PZ: return FPR_PZ;
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case _FPCLASS_PD: return FPR_PD;
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case _FPCLASS_PN: return FPR_PN;
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case _FPCLASS_PINF: return FPR_PINF;
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}
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#else
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switch (fpc)
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{
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case FP_NAN: return FPR_QNAN;
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case FP_INFINITE: return std::signbit(_double) ? FPR_NINF : FPR_PINF;
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case FP_SUBNORMAL: return std::signbit(_double) ? FPR_ND : FPR_PD;
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case FP_ZERO: return std::signbit(_double) ? FPR_NZ : FPR_PZ;
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default: return std::signbit(_double) ? FPR_NN : FPR_PN;
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case FP_NAN: return FPR_QNAN;
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case FP_INFINITE: return std::signbit(_double) ? FPR_NINF : FPR_PINF;
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case FP_SUBNORMAL: return std::signbit(_double) ? FPR_ND : FPR_PD;
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case FP_ZERO: return std::signbit(_double) ? FPR_NZ : FPR_PZ;
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default: return std::signbit(_double) ? FPR_NN : FPR_PN;
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}
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#endif
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@ -585,8 +585,8 @@ public:
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VSCRhdr VSCR; // Vector Status and Control Register
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u64 LR; //SPR 0x008 : Link Register
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u64 CTR; //SPR 0x009 : Count Register
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u64 LR; //SPR 0x008 : Link Register
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u64 CTR; //SPR 0x009 : Count Register
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union
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{
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@ -670,9 +670,9 @@ public:
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template<typename T> void UpdateCRn(const u8 n, const T a, const T b)
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{
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if (a < b) SetCR(n, CR_LT);
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else if (a > b) SetCR(n, CR_GT);
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else if (a == b) SetCR(n, CR_EQ);
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if (a < b) SetCR(n, CR_LT);
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else if (a > b) SetCR(n, CR_GT);
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else if (a == b) SetCR(n, CR_EQ);
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SetCR_SO(n, XER.SO);
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}
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@ -773,11 +773,11 @@ public:
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if (reg.find("FPR")==0) return fmt::Format("%016llx", (double)FPR[reg_index]);
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if (reg.find("VPR")==0) return fmt::Format("%016llx%016llx", VPR[reg_index]._u64[1], VPR[reg_index]._u64[0]);
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}
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if (reg == "CR") return fmt::Format("%08x", CR.CR);
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if (reg == "LR") return fmt::Format("%016llx", LR);
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if (reg == "CTR") return fmt::Format("%016llx", CTR);
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if (reg == "XER") return fmt::Format("%016llx", XER.XER);
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if (reg == "FPSCR") return fmt::Format("%08x", FPSCR.FPSCR);
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if (reg == "CR") return fmt::Format("%08x", CR.CR);
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if (reg == "LR") return fmt::Format("%016llx", LR);
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if (reg == "CTR") return fmt::Format("%016llx", CTR);
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if (reg == "XER") return fmt::Format("%016llx", XER.XER);
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if (reg == "FPSCR") return fmt::Format("%08x", FPSCR.FPSCR);
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return "";
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}
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