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rsx: Fix some pipe state signal propagation routines

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kd-11 2023-01-16 14:57:55 +03:00 • committed by kd-11
parent e6a7597444
commit bd69466e94
1 changed files with 30 additions and 14 deletions
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30
rpcs3/Emu/RSX/rsx_methods.cpp
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@ -783,13 +783,22 @@ namespace rsx
void set_surface_dirty_bit(thread* rsx, u32 reg, u32 arg) void set_surface_dirty_bit(thread* rsx, u32 reg, u32 arg)
{ {
if (reg == NV4097_SET_SURFACE_CLIP_VERTICAL || if (arg == method_registers.register_previous_value)
reg == NV4097_SET_SURFACE_CLIP_HORIZONTAL)
{ {
if (arg != method_registers.register_previous_value) return;
{
rsx->m_graphics_state |= rsx::pipeline_state::vertex_state_dirty;
} }
switch (reg)
{
case NV4097_SET_SURFACE_COLOR_TARGET:
rsx->m_graphics_state |= rsx::pipeline_state::pipeline_config_dirty;
break;
case NV4097_SET_SURFACE_CLIP_VERTICAL:
case NV4097_SET_SURFACE_CLIP_HORIZONTAL:
rsx->m_graphics_state |= rsx::pipeline_state::vertex_state_dirty;
break;
default:
break;
} }
rsx->m_rtts_dirty = true; rsx->m_rtts_dirty = true;
@ -798,8 +807,16 @@ namespace rsx
void set_surface_format(thread* rsx, u32 reg, u32 arg) void set_surface_format(thread* rsx, u32 reg, u32 arg)
{ {
if (reg == NV4097_SET_SURFACE_FORMAT) // The high bits of this register are just log2(dimension), ignore them
if ((arg & 0xFFFF) == (method_registers.register_previous_value & 0xFFFF))
{ {
return;
}
// The important parameters have changed (format, type, antialias)
rsx->m_graphics_state |= rsx::pipeline_state::pipeline_config_dirty;
// Check if we need to also update fragment state
const auto current = method_registers.decode<NV4097_SET_SURFACE_FORMAT>(arg); const auto current = method_registers.decode<NV4097_SET_SURFACE_FORMAT>(arg);
const auto previous = method_registers.decode<NV4097_SET_SURFACE_FORMAT>(method_registers.register_previous_value); const auto previous = method_registers.decode<NV4097_SET_SURFACE_FORMAT>(method_registers.register_previous_value);
@ -808,7 +825,6 @@ namespace rsx
{ {
rsx->m_graphics_state |= rsx::pipeline_state::fragment_state_dirty; rsx->m_graphics_state |= rsx::pipeline_state::fragment_state_dirty;
} }
}
set_surface_dirty_bit(rsx, reg, arg); set_surface_dirty_bit(rsx, reg, arg);
} }