archive/rpcs3
1
0
Fork 0
mirror of https://github.com/RPCS3/rpcs3.git synced 2025-07-07 07:21:25 +12:00
Code Issues Projects Releases Packages Wiki Activity Actions

SPU Fixes

Browse source 
Mandelbrot set does work now and its modified version included in
TEST12345 folder.
This commit is contained in:
Nekotekina 2013-12-23 15:57:09 +04:00
parent 37b5b49f58
commit ba8108d595
4 changed files with 7 additions and 17 deletions
Download patch file Download diff file Expand all files Collapse all files

BIN
bin/dev_hdd0/game/TEST12345/USRDIR/mandelbrot_set_no_pads.self Normal file
View file

Binary file not shown.

BIN
bin/dev_hdd0/game/TEST12345/USRDIR/mandelbrot_set_spu.self Normal file
View file

Binary file not shown.

18
rpcs3/Emu/Cell/SPUInterpreter.h
View file

@ -192,17 +192,7 @@ private:
const u32 s = i7 & 0x3f; const u32 s = i7 & 0x3f;
for (u32 j = 0; j < 4; ++j) for (u32 j = 0; j < 4; ++j)
{ CPU.GPR[rt]._u32[j] = CPU.GPR[ra]._u32[j] << s;
const u32 t = CPU.GPR[ra]._u32[j];
u32 r = 0;
for(u32 b = 0; b + s < 32; ++b)
{
r |= t & (1 << (b + s));
}
CPU.GPR[rt]._u32[j] = r;
}
} }
void ROTHI(u32 rt, u32 ra, s32 i7) void ROTHI(u32 rt, u32 ra, s32 i7)
{ {
@ -1412,7 +1402,7 @@ private:
} }
} }
} }
void MPYA(u32 rc, u32 ra, u32 rb, u32 rt) void MPYA(u32 rt, u32 ra, u32 rb, u32 rc)
{ {
for (int w = 0; w < 4; w++) for (int w = 0; w < 4; w++)
CPU.GPR[rt]._i32[w] = CPU.GPR[ra]._i16[w*2] * CPU.GPR[rb]._i16[w*2] + CPU.GPR[rc]._i32[w]; CPU.GPR[rt]._i32[w] = CPU.GPR[ra]._i16[w*2] * CPU.GPR[rb]._i16[w*2] + CPU.GPR[rc]._i32[w];
@ -1424,14 +1414,14 @@ private:
CPU.GPR[rt]._f[2] = CPU.GPR[rc]._f[2] - CPU.GPR[ra]._f[2] * CPU.GPR[rb]._f[2]; CPU.GPR[rt]._f[2] = CPU.GPR[rc]._f[2] - CPU.GPR[ra]._f[2] * CPU.GPR[rb]._f[2];
CPU.GPR[rt]._f[3] = CPU.GPR[rc]._f[3] - CPU.GPR[ra]._f[3] * CPU.GPR[rb]._f[3]; CPU.GPR[rt]._f[3] = CPU.GPR[rc]._f[3] - CPU.GPR[ra]._f[3] * CPU.GPR[rb]._f[3];
} }
void FMA(u32 rc, u32 ra, u32 rb, u32 rt) void FMA(u32 rt, u32 ra, u32 rb, u32 rc)
{ {
CPU.GPR[rt]._f[0] = CPU.GPR[ra]._f[0] * CPU.GPR[rb]._f[0] + CPU.GPR[rc]._f[0]; CPU.GPR[rt]._f[0] = CPU.GPR[ra]._f[0] * CPU.GPR[rb]._f[0] + CPU.GPR[rc]._f[0];
CPU.GPR[rt]._f[1] = CPU.GPR[ra]._f[1] * CPU.GPR[rb]._f[1] + CPU.GPR[rc]._f[1]; CPU.GPR[rt]._f[1] = CPU.GPR[ra]._f[1] * CPU.GPR[rb]._f[1] + CPU.GPR[rc]._f[1];
CPU.GPR[rt]._f[2] = CPU.GPR[ra]._f[2] * CPU.GPR[rb]._f[2] + CPU.GPR[rc]._f[2]; CPU.GPR[rt]._f[2] = CPU.GPR[ra]._f[2] * CPU.GPR[rb]._f[2] + CPU.GPR[rc]._f[2];
CPU.GPR[rt]._f[3] = CPU.GPR[ra]._f[3] * CPU.GPR[rb]._f[3] + CPU.GPR[rc]._f[3]; CPU.GPR[rt]._f[3] = CPU.GPR[ra]._f[3] * CPU.GPR[rb]._f[3] + CPU.GPR[rc]._f[3];
} }
void FMS(u32 rc, u32 ra, u32 rb, u32 rt) void FMS(u32 rt, u32 ra, u32 rb, u32 rc)
{ {
CPU.GPR[rt]._f[0] = CPU.GPR[ra]._f[0] * CPU.GPR[rb]._f[0] - CPU.GPR[rc]._f[0]; CPU.GPR[rt]._f[0] = CPU.GPR[ra]._f[0] * CPU.GPR[rb]._f[0] - CPU.GPR[rc]._f[0];
CPU.GPR[rt]._f[1] = CPU.GPR[ra]._f[1] * CPU.GPR[rb]._f[1] - CPU.GPR[rc]._f[1]; CPU.GPR[rt]._f[1] = CPU.GPR[ra]._f[1] * CPU.GPR[rb]._f[1] - CPU.GPR[rc]._f[1];

4
rpcs3/Emu/Cell/SPUThread.h
View file

@ -444,11 +444,11 @@ public:
case MFC_PUT_CMD: case MFC_PUT_CMD:
case MFC_GET_CMD: case MFC_GET_CMD:
{ {
ConLog.Warning("DMA %s%s%s: lsa = 0x%x, ea = 0x%llx, tag = 0x%x, size = 0x%x, cmd = 0x%x", /* ConLog.Warning("DMA %s%s%s: lsa = 0x%x, ea = 0x%llx, tag = 0x%x, size = 0x%x, cmd = 0x%x",
op & MFC_PUT_CMD ? "PUT" : "GET", op & MFC_PUT_CMD ? "PUT" : "GET",
op & MFC_BARRIER_MASK ? "B" : "", op & MFC_BARRIER_MASK ? "B" : "",
op & MFC_FENCE_MASK ? "F" : "", op & MFC_FENCE_MASK ? "F" : "",
lsa, ea, tag, size, cmd); lsa, ea, tag, size, cmd); */
MFCArgs.CMDStatus.SetValue(dmac.Cmd(cmd, tag, lsa, ea, size)); MFCArgs.CMDStatus.SetValue(dmac.Cmd(cmd, tag, lsa, ea, size));
} }
break; break;