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251
rpcs3/Emu/Cell/SPUThread.h
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251
rpcs3/Emu/Cell/SPUThread.h
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#pragma once
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#include "PPCThread.h"
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static const wxString spu_reg_name[128] =
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{
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"$LR", "$SP", "$3", "$4", "$5", "$6", "$7", "$8",
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"$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16",
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"$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24",
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"$25", "$26", "$27", "$28", "$29", "$30", "$31", "$32",
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"$33", "$34", "$35", "$36", "$37", "$38", "$39", "$40",
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"$41", "$42", "$43", "$44", "$45", "$46", "$47", "$48",
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"$49", "$50", "$51", "$52", "$53", "$54", "$55", "$56",
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"$57", "$58", "$59", "$60", "$61", "$62", "$63", "$64",
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"$65", "$66", "$67", "$68", "$69", "$70", "$71", "$72",
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"$73", "$74", "$75", "$76", "$77", "$78", "$79", "$80",
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"$81", "$82", "$83", "$84", "$85", "$86", "$87", "$88",
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"$89", "$90", "$91", "$92", "$93", "$94", "$95", "$96",
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"$97", "$98", "$99", "$100", "$101", "$102", "$103", "$104",
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"$105", "$106", "$107", "$108", "$109", "$110", "$111", "$112",
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"$113", "$114", "$115", "$116", "$117", "$118", "$119", "$120",
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"$121", "$122", "$123", "$124", "$125", "$126", "$127",
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};
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static const wxString spu_ch_name[128] =
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{
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"$SPU_RdEventStat", "$SPU_WrEventMask", "$SPU_RdSigNotify1",
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"$SPU_RdSigNotify2", "$ch5", "$ch6", "$SPU_WrDec", "$SPU_RdDec",
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"$MFC_WrMSSyncReq", "$ch10", "$SPU_RdEventMask", "$MFC_RdTagMask", "$SPU_RdMachStat",
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"$SPU_WrSRR0", "$SPU_RdSRR0", "$MFC_LSA", "$MFC_EAH", "$MFC_EAL", "$MFC_Size",
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"$MFC_TagID", "$MFC_Cmd", "$MFC_WrTagMask", "$MFC_WrTagUpdate", "$MFC_RdTagStat",
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"$MFC_RdListStallStat", "$MFC_WrListStallAck", "$MFC_RdAtomicStat",
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"$SPU_WrOutMbox", "$SPU_RdInMbox", "$SPU_WrOutIntrMbox", "$ch31", "$ch32",
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"$ch33", "$ch34", "$ch35", "$ch36", "$ch37", "$ch38", "$ch39", "$ch40",
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"$ch41", "$ch42", "$ch43", "$ch44", "$ch45", "$ch46", "$ch47", "$ch48",
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"$ch49", "$ch50", "$ch51", "$ch52", "$ch53", "$ch54", "$ch55", "$ch56",
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"$ch57", "$ch58", "$ch59", "$ch60", "$ch61", "$ch62", "$ch63", "$ch64",
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"$ch65", "$ch66", "$ch67", "$ch68", "$ch69", "$ch70", "$ch71", "$ch72",
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"$ch73", "$ch74", "$ch75", "$ch76", "$ch77", "$ch78", "$ch79", "$ch80",
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"$ch81", "$ch82", "$ch83", "$ch84", "$ch85", "$ch86", "$ch87", "$ch88",
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"$ch89", "$ch90", "$ch91", "$ch92", "$ch93", "$ch94", "$ch95", "$ch96",
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"$ch97", "$ch98", "$ch99", "$ch100", "$ch101", "$ch102", "$ch103", "$ch104",
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"$ch105", "$ch106", "$ch107", "$ch108", "$ch109", "$ch110", "$ch111", "$ch112",
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"$ch113", "$ch114", "$ch115", "$ch116", "$ch117", "$ch118", "$ch119", "$ch120",
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"$ch121", "$ch122", "$ch123", "$ch124", "$ch125", "$ch126", "$ch127",
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};
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enum SPUchannels
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{
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SPU_RdEventStat = 0, //Read event status with mask applied
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SPU_WrEventMask = 1, //Write event mask
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SPU_WrEventAck = 2, //Write end of event processing
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SPU_RdSigNotify1 = 3, //Signal notification 1
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SPU_RdSigNotify2 = 4, //Signal notification 2
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SPU_WrDec = 7, //Write decrementer count
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SPU_RdDec = 8, //Read decrementer count
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SPU_RdEventMask = 11, //Read event mask
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SPU_RdMachStat = 13, //Read SPU run status
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SPU_WrSRR0 = 14, //Write SPU machine state save/restore register 0 (SRR0)
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SPU_RdSRR0 = 15, //Read SPU machine state save/restore register 0 (SRR0)
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SPU_WrOutMbox = 28, //Write outbound mailbox contents
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SPU_RdInMbox = 29, //Read inbound mailbox contents
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SPU_WrOutIntrMbox = 30, //Write outbound interrupt mailbox contents (interrupting PPU)
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};
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enum MFCchannels
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{
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MFC_WrMSSyncReq = 9, //Write multisource synchronization request
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MFC_RdTagMask = 12, //Read tag mask
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MFC_LSA = 16, //Write local memory address command parameter
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MFC_EAH = 17, //Write high order DMA effective address command parameter
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MFC_EAL = 18, //Write low order DMA effective address command parameter
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MFC_Size = 19, //Write DMA transfer size command parameter
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MFC_TagID = 20, //Write tag identifier command parameter
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MFC_Cmd = 21, //Write and enqueue DMA command with associated class ID
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MFC_WrTagMask = 22, //Write tag mask
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MFC_WrTagUpdate = 23, //Write request for conditional or unconditional tag status update
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MFC_RdTagStat = 24, //Read tag status with mask applied
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MFC_RdListStallStat = 25, //Read DMA list stall-and-notify status
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MFC_WrListStallAck = 26, //Write DMA list stall-and-notify acknowledge
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MFC_RdAtomicStat = 27, //Read completion status of last completed immediate MFC atomic update command
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};
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union SPU_GPR_hdr
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{
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//__m128i _m128i;
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u128 _u128;
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s128 _i128;
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u64 _u64[2];
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s64 _i64[2];
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u32 _u32[4];
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s32 _i32[4];
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u16 _u16[8];
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s16 _i16[8];
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u8 _u8[16];
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s8 _i8[16];
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SPU_GPR_hdr() {}
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/*
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SPU_GPR_hdr(const __m128i val){_u128._u64[0] = val.m128i_u64[0]; _u128._u64[1] = val.m128i_u64[1];}
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SPU_GPR_hdr(const u128 val) { _u128 = val; }
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SPU_GPR_hdr(const u64 val) { Reset(); _u64[0] = val; }
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SPU_GPR_hdr(const u32 val) { Reset(); _u32[0] = val; }
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SPU_GPR_hdr(const u16 val) { Reset(); _u16[0] = val; }
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SPU_GPR_hdr(const u8 val) { Reset(); _u8[0] = val; }
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SPU_GPR_hdr(const s128 val) { _i128 = val; }
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SPU_GPR_hdr(const s64 val) { Reset(); _i64[0] = val; }
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SPU_GPR_hdr(const s32 val) { Reset(); _i32[0] = val; }
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SPU_GPR_hdr(const s16 val) { Reset(); _i16[0] = val; }
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SPU_GPR_hdr(const s8 val) { Reset(); _i8[0] = val; }
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*/
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wxString ToString() const
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{
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return wxString::Format("%08x%08x%08x%08x", _u32[3], _u32[2], _u32[1], _u32[0]);
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}
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void Reset()
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{
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memset(this, 0, sizeof(*this));
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}
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//operator __m128i() { __m128i ret; ret.m128i_u64[0]=_u128._u64[0]; ret.m128i_u64[1]=_u128._u64[1]; return ret; }
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/*
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SPU_GPR_hdr operator ^ (__m128i right) { return _mm_xor_si128(*this, right); }
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SPU_GPR_hdr operator | (__m128i right) { return _mm_or_si128 (*this, right); }
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SPU_GPR_hdr operator & (__m128i right) { return _mm_and_si128(*this, right); }
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SPU_GPR_hdr operator << (int right) { return _mm_slli_epi32(*this, right); }
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SPU_GPR_hdr operator << (__m128i right) { return _mm_sll_epi32(*this, right); }
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SPU_GPR_hdr operator >> (int right) { return _mm_srai_epi32(*this, right); }
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SPU_GPR_hdr operator >> (__m128i right) { return _mm_sra_epi32(*this, right); }
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SPU_GPR_hdr operator | (__m128i right) { return _mm_or_si128 (*this, right); }
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SPU_GPR_hdr operator & (__m128i right) { return _mm_and_si128(*this, right); }
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SPU_GPR_hdr operator << (int right) { return _mm_slli_epi32(*this, right); }
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SPU_GPR_hdr operator << (__m128i right) { return _mm_sll_epi32(*this, right); }
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SPU_GPR_hdr operator >> (int right) { return _mm_srai_epi32(*this, right); }
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SPU_GPR_hdr operator >> (__m128i right) { return _mm_sra_epi32(*this, right); }
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SPU_GPR_hdr operator ^= (__m128i right) { return *this = *this ^ right; }
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SPU_GPR_hdr operator |= (__m128i right) { return *this = *this | right; }
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SPU_GPR_hdr operator &= (__m128i right) { return *this = *this & right; }
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SPU_GPR_hdr operator <<= (int right) { return *this = *this << right; }
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SPU_GPR_hdr operator <<= (__m128i right){ return *this = *this << right; }
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SPU_GPR_hdr operator >>= (int right) { return *this = *this >> right; }
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SPU_GPR_hdr operator >>= (__m128i right){ return *this = *this >> right; }
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*/
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};
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class SPUThread : public PPCThread
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{
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public:
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SPU_GPR_hdr GPR[128]; //General-Purpose Register
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Stack<u32> Mbox;
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u32 LSA; //local storage address
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union
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{
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u64 EA;
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struct { u32 EAH, EAL; };
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};
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u32 GetChannelCount(u32 ch)
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{
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switch(ch)
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{
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case SPU_RdInMbox:
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return 1;
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case SPU_WrOutIntrMbox:
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return 0;
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default:
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ConLog.Error("%s error: unknown/illegal channel (%d).", __FUNCTION__, ch);
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break;
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}
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return 0;
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}
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void WriteChannel(u32 ch, const SPU_GPR_hdr& r)
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{
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const u32 v = r._u32[0];
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switch(ch)
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{
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case SPU_WrOutIntrMbox:
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Mbox.Push(v);
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break;
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default:
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ConLog.Error("%s error: unknown/illegal channel (%d).", __FUNCTION__, ch);
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break;
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}
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}
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void ReadChannel(SPU_GPR_hdr& r, u32 ch)
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{
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r.Reset();
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u32& v = r._u32[0];
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switch(ch)
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{
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case SPU_RdInMbox:
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v = Mbox.Pop();
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break;
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default:
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ConLog.Error("%s error: unknown/illegal channel (%d).", __FUNCTION__, ch);
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break;
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}
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}
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u8 ReadLSA8 () { return Memory.Read8 (LSA + m_offset); }
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u16 ReadLSA16 () { return Memory.Read16 (LSA + m_offset); }
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u32 ReadLSA32 () { return Memory.Read32 (LSA + m_offset); }
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u64 ReadLSA64 () { return Memory.Read64 (LSA + m_offset); }
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u128 ReadLSA128() { return Memory.Read128(LSA + m_offset); }
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void WriteLSA8 (const u8& data) { Memory.Write8 (LSA + m_offset, data); }
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void WriteLSA16 (const u16& data) { Memory.Write16 (LSA + m_offset, data); }
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void WriteLSA32 (const u32& data) { Memory.Write32 (LSA + m_offset, data); }
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void WriteLSA64 (const u64& data) { Memory.Write64 (LSA + m_offset, data); }
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void WriteLSA128(const u128& data) { Memory.Write128(LSA + m_offset, data); }
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public:
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SPUThread();
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~SPUThread();
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virtual wxString RegsToString()
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{
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wxString ret = PPCThread::RegsToString();
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for(uint i=0; i<128; ++i) ret += wxString::Format("GPR[%d] = 0x%s\n", i, GPR[i].ToString());
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return ret;
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}
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public:
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virtual void InitRegs();
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virtual u64 GetFreeStackSize() const;
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protected:
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virtual void DoReset();
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virtual void DoRun();
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virtual void DoPause();
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virtual void DoResume();
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virtual void DoStop();
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private:
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virtual void DoCode(const s32 code);
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};
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