From a52a16807f6a3d67c54899039df5ce9b40528fd2 Mon Sep 17 00:00:00 2001 From: Eladash Date: Mon, 14 Sep 2020 08:08:26 +0300 Subject: [PATCH] PPU: Use SEQ-CST memory barrier in reservation load --- rpcs3/Emu/Cell/PPUThread.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/rpcs3/Emu/Cell/PPUThread.cpp b/rpcs3/Emu/Cell/PPUThread.cpp index 9494252b0c..ebbdacce49 100644 --- a/rpcs3/Emu/Cell/PPUThread.cpp +++ b/rpcs3/Emu/Cell/PPUThread.cpp @@ -1076,6 +1076,9 @@ static void ppu_trace(u64 addr) template static T ppu_load_acquire_reservation(ppu_thread& ppu, u32 addr) { + // Do not allow stores accessed from the same cache line to past reservation load + std::atomic_thread_fence(std::memory_order_seq_cst); + if (addr % sizeof(T)) { fmt::throw_exception("PPU %s: Unaligned address: 0x%08x" HERE, sizeof(T) == 4 ? "LWARX" : "LDARX", addr);