mirror of
https://github.com/RPCS3/rpcs3.git
synced 2025-07-11 01:08:39 +12:00
Few instructions simplified
This commit is contained in:
parent
7777be6fc1
commit
973e3f8f7e
1 changed files with 117 additions and 61 deletions
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@ -1384,18 +1384,21 @@ private:
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}
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}
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void CBX(u32 rt, u32 ra, u32 rb)
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void CBX(u32 rt, u32 ra, u32 rb)
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{
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{
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c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
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c.mov(*addr, cpu_dword(GPR[rb]._u32[3]));
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if (ra == rb)
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if (ra == 1)
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{
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// assuming that SP % 16 is always zero
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}
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else if (ra == rb)
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{
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{
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c.add(*addr, *addr);
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c.add(*addr, *addr);
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}
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}
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else
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else
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{
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{
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c.add(*addr, cpu_dword(GPR[rb]._u32[3]));
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c.add(*addr, cpu_dword(GPR[ra]._u32[3]));
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}
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}
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c.not_(*addr);
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c.and_(*addr, 0xf);
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c.and_(*addr, 0xf);
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c.neg(*addr);
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c.add(*addr, 0xf);
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const XmmLink& vr = XmmAlloc(rt);
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const XmmLink& vr = XmmAlloc(rt);
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c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
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c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
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XmmFinalize(vr, rt);
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XmmFinalize(vr, rt);
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@ -1405,18 +1408,21 @@ private:
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}
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}
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void CHX(u32 rt, u32 ra, u32 rb)
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void CHX(u32 rt, u32 ra, u32 rb)
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{
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{
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c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
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c.mov(*addr, cpu_dword(GPR[rb]._u32[3]));
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if (ra == rb)
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if (ra == 1)
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{
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// assuming that SP % 16 is always zero
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}
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else if (ra == rb)
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{
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{
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c.add(*addr, *addr);
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c.add(*addr, *addr);
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}
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}
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else
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else
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{
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{
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c.add(*addr, cpu_dword(GPR[rb]._u32[3]));
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c.add(*addr, cpu_dword(GPR[ra]._u32[3]));
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}
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}
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c.not_(*addr);
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c.and_(*addr, 0xe);
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c.and_(*addr, 0xe);
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c.neg(*addr);
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c.add(*addr, 0xe);
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const XmmLink& vr = XmmAlloc(rt);
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const XmmLink& vr = XmmAlloc(rt);
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c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
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c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
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XmmFinalize(vr, rt);
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XmmFinalize(vr, rt);
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@ -1426,18 +1432,21 @@ private:
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}
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}
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void CWX(u32 rt, u32 ra, u32 rb)
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void CWX(u32 rt, u32 ra, u32 rb)
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{
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{
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c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
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c.mov(*addr, cpu_dword(GPR[rb]._u32[3]));
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if (ra == rb)
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if (ra == 1)
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{
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// assuming that SP % 16 is always zero
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}
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else if (ra == rb)
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{
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{
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c.add(*addr, *addr);
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c.add(*addr, *addr);
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}
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}
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else
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else
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{
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{
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c.add(*addr, cpu_dword(GPR[rb]._u32[3]));
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c.add(*addr, cpu_dword(GPR[ra]._u32[3]));
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}
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}
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c.not_(*addr);
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c.and_(*addr, 0xc);
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c.and_(*addr, 0xc);
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c.neg(*addr);
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c.add(*addr, 0xc);
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const XmmLink& vr = XmmAlloc(rt);
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const XmmLink& vr = XmmAlloc(rt);
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c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
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c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
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XmmFinalize(vr, rt);
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XmmFinalize(vr, rt);
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@ -1447,18 +1456,21 @@ private:
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}
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}
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void CDX(u32 rt, u32 ra, u32 rb)
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void CDX(u32 rt, u32 ra, u32 rb)
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{
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{
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c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
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c.mov(*addr, cpu_dword(GPR[rb]._u32[3]));
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if (ra == rb)
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if (ra == 1)
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{
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// assuming that SP % 16 is always zero
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}
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else if (ra == rb)
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{
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{
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c.add(*addr, *addr);
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c.add(*addr, *addr);
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}
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}
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else
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else
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{
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{
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c.add(*addr, cpu_dword(GPR[rb]._u32[3]));
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c.add(*addr, cpu_dword(GPR[ra]._u32[3]));
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}
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}
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c.not_(*addr);
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c.and_(*addr, 0x8);
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c.and_(*addr, 0x8);
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c.neg(*addr);
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c.add(*addr, 0x8);
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const XmmLink& vr = XmmAlloc(rt);
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const XmmLink& vr = XmmAlloc(rt);
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c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
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c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
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XmmFinalize(vr, rt);
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XmmFinalize(vr, rt);
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@ -1555,59 +1567,103 @@ private:
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}
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}
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void CBD(u32 rt, u32 ra, s32 i7)
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void CBD(u32 rt, u32 ra, s32 i7)
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{
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{
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c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
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if (ra == 1)
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c.add(*addr, i7);
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{
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c.and_(*addr, 0xf);
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// assuming that SP % 16 is always zero
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c.neg(*addr);
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const XmmLink& vr = XmmAlloc(rt);
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c.add(*addr, 0xf);
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u128 value = u128::from32r(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f);
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const XmmLink& vr = XmmAlloc(rt);
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value._u8[i7 & 0xf] = 0x03;
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c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
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c.movdqa(vr.get(), XmmConst(value.vi));
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XmmFinalize(vr, rt);
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XmmFinalize(vr, rt);
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XmmInvalidate(rt);
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}
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c.mov(byte_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u8[0])), 0x03);
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else
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{
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c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
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c.add(*addr, i7);
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c.not_(*addr);
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c.and_(*addr, 0xf);
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const XmmLink& vr = XmmAlloc(rt);
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c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
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XmmFinalize(vr, rt);
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XmmInvalidate(rt);
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c.mov(byte_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u8[0])), 0x03);
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}
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LOG_OPCODE();
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LOG_OPCODE();
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}
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}
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void CHD(u32 rt, u32 ra, s32 i7)
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void CHD(u32 rt, u32 ra, s32 i7)
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{
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{
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c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
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if (ra == 1)
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c.add(*addr, i7);
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{
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c.and_(*addr, 0xe);
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// assuming that SP % 16 is always zero
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c.neg(*addr);
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const XmmLink& vr = XmmAlloc(rt);
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c.add(*addr, 0xe);
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u128 value = u128::from32r(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f);
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const XmmLink& vr = XmmAlloc(rt);
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value._u16[i7 & 0x7] = 0x0203;
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c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
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c.movdqa(vr.get(), XmmConst(value.vi));
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XmmFinalize(vr, rt);
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XmmFinalize(vr, rt);
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XmmInvalidate(rt);
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}
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c.mov(word_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u16[0])), 0x0203);
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else
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{
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c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
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c.add(*addr, i7);
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c.not_(*addr);
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c.and_(*addr, 0xe);
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const XmmLink& vr = XmmAlloc(rt);
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c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
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XmmFinalize(vr, rt);
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XmmInvalidate(rt);
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c.mov(word_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u16[0])), 0x0203);
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}
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LOG_OPCODE();
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LOG_OPCODE();
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}
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}
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void CWD(u32 rt, u32 ra, s32 i7)
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void CWD(u32 rt, u32 ra, s32 i7)
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{
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{
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c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
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if (ra == 1)
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c.add(*addr, i7);
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{
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c.and_(*addr, 0xc);
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// assuming that SP % 16 is always zero
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c.neg(*addr);
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const XmmLink& vr = XmmAlloc(rt);
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c.add(*addr, 0xc);
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u128 value = u128::from32r(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f);
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const XmmLink& vr = XmmAlloc(rt);
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value._u32[i7 & 0x3] = 0x00010203;
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c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
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c.movdqa(vr.get(), XmmConst(value.vi));
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XmmFinalize(vr, rt);
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XmmFinalize(vr, rt);
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XmmInvalidate(rt);
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}
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c.mov(dword_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u32[0])), 0x00010203);
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else
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{
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c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
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c.add(*addr, i7);
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c.not_(*addr);
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c.and_(*addr, 0xc);
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const XmmLink& vr = XmmAlloc(rt);
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c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
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XmmFinalize(vr, rt);
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XmmInvalidate(rt);
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c.mov(dword_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u32[0])), 0x00010203);
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}
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LOG_OPCODE();
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LOG_OPCODE();
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}
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}
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void CDD(u32 rt, u32 ra, s32 i7)
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void CDD(u32 rt, u32 ra, s32 i7)
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{
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{
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c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
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if (ra == 1)
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c.add(*addr, i7);
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{
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c.and_(*addr, 0x8);
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// assuming that SP % 16 is always zero
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c.neg(*addr);
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const XmmLink& vr = XmmAlloc(rt);
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c.add(*addr, 0x8);
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u128 value = u128::from32r(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f);
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const XmmLink& vr = XmmAlloc(rt);
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value._u64[i7 & 0x1] = 0x0001020304050607ull;
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c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
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c.movdqa(vr.get(), XmmConst(value.vi));
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XmmFinalize(vr, rt);
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XmmFinalize(vr, rt);
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XmmInvalidate(rt);
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}
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c.mov(dword_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u32[0])), 0x04050607);
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else
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c.mov(dword_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u32[1])), 0x00010203);
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{
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c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
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c.add(*addr, i7);
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c.not_(*addr);
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c.and_(*addr, 0x8);
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const XmmLink& vr = XmmAlloc(rt);
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c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
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XmmFinalize(vr, rt);
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XmmInvalidate(rt);
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c.mov(dword_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u32[0])), 0x04050607);
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c.mov(dword_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u32[1])), 0x00010203);
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}
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LOG_OPCODE();
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LOG_OPCODE();
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}
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}
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void ROTQBII(u32 rt, u32 ra, s32 i7)
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void ROTQBII(u32 rt, u32 ra, s32 i7)
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