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This commit is contained in:
Nekotekina 2014-10-24 02:06:15 +04:00
parent 7777be6fc1
commit 973e3f8f7e
1 changed files with 117 additions and 61 deletions
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178
rpcs3/Emu/Cell/SPURecompiler.h
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@ -1384,18 +1384,21 @@ private:
} }
void CBX(u32 rt, u32 ra, u32 rb) void CBX(u32 rt, u32 ra, u32 rb)
{ {
c.mov(*addr, cpu_dword(GPR[ra]._u32[3])); c.mov(*addr, cpu_dword(GPR[rb]._u32[3]));
if (ra == rb) if (ra == 1)
{
// assuming that SP % 16 is always zero
}
else if (ra == rb)
{ {
c.add(*addr, *addr); c.add(*addr, *addr);
} }
else else
{ {
c.add(*addr, cpu_dword(GPR[rb]._u32[3])); c.add(*addr, cpu_dword(GPR[ra]._u32[3]));
} }
c.not_(*addr);
c.and_(*addr, 0xf); c.and_(*addr, 0xf);
c.neg(*addr);
c.add(*addr, 0xf);
const XmmLink& vr = XmmAlloc(rt); const XmmLink& vr = XmmAlloc(rt);
c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))); c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
XmmFinalize(vr, rt); XmmFinalize(vr, rt);
@ -1405,18 +1408,21 @@ private:
} }
void CHX(u32 rt, u32 ra, u32 rb) void CHX(u32 rt, u32 ra, u32 rb)
{ {
c.mov(*addr, cpu_dword(GPR[ra]._u32[3])); c.mov(*addr, cpu_dword(GPR[rb]._u32[3]));
if (ra == rb) if (ra == 1)
{
// assuming that SP % 16 is always zero
}
else if (ra == rb)
{ {
c.add(*addr, *addr); c.add(*addr, *addr);
} }
else else
{ {
c.add(*addr, cpu_dword(GPR[rb]._u32[3])); c.add(*addr, cpu_dword(GPR[ra]._u32[3]));
} }
c.not_(*addr);
c.and_(*addr, 0xe); c.and_(*addr, 0xe);
c.neg(*addr);
c.add(*addr, 0xe);
const XmmLink& vr = XmmAlloc(rt); const XmmLink& vr = XmmAlloc(rt);
c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))); c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
XmmFinalize(vr, rt); XmmFinalize(vr, rt);
@ -1426,18 +1432,21 @@ private:
} }
void CWX(u32 rt, u32 ra, u32 rb) void CWX(u32 rt, u32 ra, u32 rb)
{ {
c.mov(*addr, cpu_dword(GPR[ra]._u32[3])); c.mov(*addr, cpu_dword(GPR[rb]._u32[3]));
if (ra == rb) if (ra == 1)
{
// assuming that SP % 16 is always zero
}
else if (ra == rb)
{ {
c.add(*addr, *addr); c.add(*addr, *addr);
} }
else else
{ {
c.add(*addr, cpu_dword(GPR[rb]._u32[3])); c.add(*addr, cpu_dword(GPR[ra]._u32[3]));
} }
c.not_(*addr);
c.and_(*addr, 0xc); c.and_(*addr, 0xc);
c.neg(*addr);
c.add(*addr, 0xc);
const XmmLink& vr = XmmAlloc(rt); const XmmLink& vr = XmmAlloc(rt);
c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))); c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
XmmFinalize(vr, rt); XmmFinalize(vr, rt);
@ -1447,18 +1456,21 @@ private:
} }
void CDX(u32 rt, u32 ra, u32 rb) void CDX(u32 rt, u32 ra, u32 rb)
{ {
c.mov(*addr, cpu_dword(GPR[ra]._u32[3])); c.mov(*addr, cpu_dword(GPR[rb]._u32[3]));
if (ra == rb) if (ra == 1)
{
// assuming that SP % 16 is always zero
}
else if (ra == rb)
{ {
c.add(*addr, *addr); c.add(*addr, *addr);
} }
else else
{ {
c.add(*addr, cpu_dword(GPR[rb]._u32[3])); c.add(*addr, cpu_dword(GPR[ra]._u32[3]));
} }
c.not_(*addr);
c.and_(*addr, 0x8); c.and_(*addr, 0x8);
c.neg(*addr);
c.add(*addr, 0x8);
const XmmLink& vr = XmmAlloc(rt); const XmmLink& vr = XmmAlloc(rt);
c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))); c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
XmmFinalize(vr, rt); XmmFinalize(vr, rt);
@ -1555,59 +1567,103 @@ private:
} }
void CBD(u32 rt, u32 ra, s32 i7) void CBD(u32 rt, u32 ra, s32 i7)
{ {
c.mov(*addr, cpu_dword(GPR[ra]._u32[3])); if (ra == 1)
c.add(*addr, i7); {
c.and_(*addr, 0xf); // assuming that SP % 16 is always zero
c.neg(*addr); const XmmLink& vr = XmmAlloc(rt);
c.add(*addr, 0xf); u128 value = u128::from32r(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f);
const XmmLink& vr = XmmAlloc(rt); value._u8[i7 & 0xf] = 0x03;
c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))); c.movdqa(vr.get(), XmmConst(value.vi));
XmmFinalize(vr, rt); XmmFinalize(vr, rt);
XmmInvalidate(rt); }
c.mov(byte_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u8[0])), 0x03); else
{
c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
c.add(*addr, i7);
c.not_(*addr);
c.and_(*addr, 0xf);
const XmmLink& vr = XmmAlloc(rt);
c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
XmmFinalize(vr, rt);
XmmInvalidate(rt);
c.mov(byte_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u8[0])), 0x03);
}
LOG_OPCODE(); LOG_OPCODE();
} }
void CHD(u32 rt, u32 ra, s32 i7) void CHD(u32 rt, u32 ra, s32 i7)
{ {
c.mov(*addr, cpu_dword(GPR[ra]._u32[3])); if (ra == 1)
c.add(*addr, i7); {
c.and_(*addr, 0xe); // assuming that SP % 16 is always zero
c.neg(*addr); const XmmLink& vr = XmmAlloc(rt);
c.add(*addr, 0xe); u128 value = u128::from32r(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f);
const XmmLink& vr = XmmAlloc(rt); value._u16[i7 & 0x7] = 0x0203;
c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))); c.movdqa(vr.get(), XmmConst(value.vi));
XmmFinalize(vr, rt); XmmFinalize(vr, rt);
XmmInvalidate(rt); }
c.mov(word_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u16[0])), 0x0203); else
{
c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
c.add(*addr, i7);
c.not_(*addr);
c.and_(*addr, 0xe);
const XmmLink& vr = XmmAlloc(rt);
c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
XmmFinalize(vr, rt);
XmmInvalidate(rt);
c.mov(word_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u16[0])), 0x0203);
}
LOG_OPCODE(); LOG_OPCODE();
} }
void CWD(u32 rt, u32 ra, s32 i7) void CWD(u32 rt, u32 ra, s32 i7)
{ {
c.mov(*addr, cpu_dword(GPR[ra]._u32[3])); if (ra == 1)
c.add(*addr, i7); {
c.and_(*addr, 0xc); // assuming that SP % 16 is always zero
c.neg(*addr); const XmmLink& vr = XmmAlloc(rt);
c.add(*addr, 0xc); u128 value = u128::from32r(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f);
const XmmLink& vr = XmmAlloc(rt); value._u32[i7 & 0x3] = 0x00010203;
c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))); c.movdqa(vr.get(), XmmConst(value.vi));
XmmFinalize(vr, rt); XmmFinalize(vr, rt);
XmmInvalidate(rt); }
c.mov(dword_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u32[0])), 0x00010203); else
{
c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
c.add(*addr, i7);
c.not_(*addr);
c.and_(*addr, 0xc);
const XmmLink& vr = XmmAlloc(rt);
c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
XmmFinalize(vr, rt);
XmmInvalidate(rt);
c.mov(dword_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u32[0])), 0x00010203);
}
LOG_OPCODE(); LOG_OPCODE();
} }
void CDD(u32 rt, u32 ra, s32 i7) void CDD(u32 rt, u32 ra, s32 i7)
{ {
c.mov(*addr, cpu_dword(GPR[ra]._u32[3])); if (ra == 1)
c.add(*addr, i7); {
c.and_(*addr, 0x8); // assuming that SP % 16 is always zero
c.neg(*addr); const XmmLink& vr = XmmAlloc(rt);
c.add(*addr, 0x8); u128 value = u128::from32r(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f);
const XmmLink& vr = XmmAlloc(rt); value._u64[i7 & 0x1] = 0x0001020304050607ull;
c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))); c.movdqa(vr.get(), XmmConst(value.vi));
XmmFinalize(vr, rt); XmmFinalize(vr, rt);
XmmInvalidate(rt); }
c.mov(dword_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u32[0])), 0x04050607); else
c.mov(dword_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u32[1])), 0x00010203); {
c.mov(*addr, cpu_dword(GPR[ra]._u32[3]));
c.add(*addr, i7);
c.not_(*addr);
c.and_(*addr, 0x8);
const XmmLink& vr = XmmAlloc(rt);
c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
XmmFinalize(vr, rt);
XmmInvalidate(rt);
c.mov(dword_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u32[0])), 0x04050607);
c.mov(dword_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u32[1])), 0x00010203);
}
LOG_OPCODE(); LOG_OPCODE();
} }
void ROTQBII(u32 rt, u32 ra, s32 i7) void ROTQBII(u32 rt, u32 ra, s32 i7)