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Implemented some vector instructions

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This commit is contained in:
S Gopal Rajagopal 2014-11-23 19:06:20 +05:30
parent 5addbcbbb0
commit 921ee1464b
3 changed files with 175 additions and 28 deletions
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26
rpcs3/Emu/Cell/PPUInterpreter.h
View file

@ -807,9 +807,15 @@ private:
float result = CPU.VPR[vb]._f[w] * nScale; float result = CPU.VPR[vb]._f[w] * nScale;
if (result > 0x7fffffff) if (result > 0x7fffffff)
{
CPU.VPR[vd]._s32[w] = (int)0x7fffffff; CPU.VPR[vd]._s32[w] = (int)0x7fffffff;
CPU.VSCR.SAT = 1;
}
else if (result < -pow(2, 31)) else if (result < -pow(2, 31))
{
CPU.VPR[vd]._s32[w] = (int)0x80000000; CPU.VPR[vd]._s32[w] = (int)0x80000000;
CPU.VSCR.SAT = 1;
}
else // C rounding = Round towards 0 else // C rounding = Round towards 0
CPU.VPR[vd]._s32[w] = (int)result; CPU.VPR[vd]._s32[w] = (int)result;
} }
@ -821,24 +827,30 @@ private:
for (uint w = 0; w < 4; w++) for (uint w = 0; w < 4; w++)
{ {
// C rounding = Round towards 0 // C rounding = Round towards 0
s64 result = (s64)(CPU.VPR[vb]._f[w] * nScale); float result = CPU.VPR[vb]._f[w] * nScale;
if (result > 0xffffffffu) if (result > 0xffffffffu)
{
CPU.VPR[vd]._u32[w] = 0xffffffffu; CPU.VPR[vd]._u32[w] = 0xffffffffu;
CPU.VSCR.SAT = 1;
}
else if (result < 0) else if (result < 0)
{
CPU.VPR[vd]._u32[w] = 0; CPU.VPR[vd]._u32[w] = 0;
CPU.VSCR.SAT = 1;
}
else else
CPU.VPR[vd]._u32[w] = (u32)result; CPU.VPR[vd]._u32[w] = (u32)result;
} }
} }
void VEXPTEFP(u32 vd, u32 vb) void VEXPTEFP(u32 vd, u32 vb)
{ {
// vd = exp(vb * log(2)) // vd = 2^x
// ISA : Note that the value placed into the element of vD may vary between implementations // ISA : Note that the value placed into the element of vD may vary between implementations
// and between different executions on the same implementation. // and between different executions on the same implementation.
for (uint w = 0; w < 4; w++) for (uint w = 0; w < 4; w++)
{ {
CPU.VPR[vd]._f[w] = exp(CPU.VPR[vb]._f[w] * log(2.0f)); CPU.VPR[vd]._f[w] = powf(2.0f, CPU.VPR[vb]._f[w]);
} }
} }
void VLOGEFP(u32 vd, u32 vb) void VLOGEFP(u32 vd, u32 vb)
@ -847,7 +859,7 @@ private:
// and between different executions on the same implementation. // and between different executions on the same implementation.
for (uint w = 0; w < 4; w++) for (uint w = 0; w < 4; w++)
{ {
CPU.VPR[vd]._f[w] = log(CPU.VPR[vb]._f[w]) / log(2.0f); CPU.VPR[vd]._f[w] = log2(CPU.VPR[vb]._f[w]);
} }
} }
void VMADDFP(u32 vd, u32 va, u32 vc, u32 vb) void VMADDFP(u32 vd, u32 va, u32 vc, u32 vb)
@ -906,7 +918,8 @@ private:
{ {
for (uint h = 0; h < 8; h++) for (uint h = 0; h < 8; h++)
{ {
s32 result = (s32)CPU.VPR[va]._s16[h] * (s32)CPU.VPR[vb]._s16[h] + (s32)CPU.VPR[vc]._s16[h]; s32 result = (s32)CPU.VPR[va]._s16[h] * (s32)CPU.VPR[vb]._s16[h];
result = (result >> 15) + (s32)CPU.VPR[vc]._s16[h];
if (result > INT16_MAX) if (result > INT16_MAX)
{ {
@ -926,7 +939,8 @@ private:
{ {
for (uint h = 0; h < 8; h++) for (uint h = 0; h < 8; h++)
{ {
s32 result = (s32)CPU.VPR[va]._s16[h] * (s32)CPU.VPR[vb]._s16[h] + (s32)CPU.VPR[vc]._s16[h] + 0x4000; s32 result = ((s32)CPU.VPR[va]._s16[h] * (s32)CPU.VPR[vb]._s16[h]) + 0x4000;
result = (result >> 15) + (s32)CPU.VPR[vc]._s16[h];
if (result > INT16_MAX) if (result > INT16_MAX)
{ {

148
rpcs3/Emu/Cell/PPULLVMRecompiler.cpp
View file

@ -288,7 +288,7 @@ void Compiler::NULL_OP() {
} }
void Compiler::NOP() { void Compiler::NOP() {
InterpreterCall("NOP", &PPUInterpreter::NOP); m_ir_builder->CreateCall(Intrinsic::getDeclaration(m_module, Intrinsic::donothing));
} }
void Compiler::TDI(u32 to, u32 ra, s32 simm16) { void Compiler::TDI(u32 to, u32 ra, s32 simm16) {
@ -725,19 +725,47 @@ void Compiler::VCMPGTUW_(u32 vd, u32 va, u32 vb) {
} }
void Compiler::VCTSXS(u32 vd, u32 uimm5, u32 vb) { void Compiler::VCTSXS(u32 vd, u32 uimm5, u32 vb) {
InterpreterCall("VCTSXS", &PPUInterpreter::VCTSXS, vd, uimm5, vb); auto vb_v4f32 = GetVrAsFloatVec(vb);
if (uimm5) {
vb_v4f32 = m_ir_builder->CreateFMul(vb_v4f32, m_ir_builder->CreateVectorSplat(4, ConstantFP::get(m_ir_builder->getFloatTy(), 1 << uimm5)));
}
auto res_v4i32 = (Value *)m_ir_builder->CreateCall(Intrinsic::getDeclaration(m_module, Intrinsic::x86_sse2_cvtps2dq), vb_v4f32);
auto cmp_v4i1 = m_ir_builder->CreateFCmpOGE(vb_v4f32, m_ir_builder->CreateVectorSplat(4, ConstantFP::get(m_ir_builder->getFloatTy(), 0x7FFFFFFF)));
auto cmp_v4i32 = m_ir_builder->CreateSExt(cmp_v4i1, VectorType::get(m_ir_builder->getInt32Ty(), 4));
res_v4i32 = m_ir_builder->CreateXor(cmp_v4i32, res_v4i32);
SetVr(vd, res_v4i32);
// TODO: Set VSCR.SAT
} }
void Compiler::VCTUXS(u32 vd, u32 uimm5, u32 vb) { void Compiler::VCTUXS(u32 vd, u32 uimm5, u32 vb) {
InterpreterCall("VCTUXS", &PPUInterpreter::VCTUXS, vd, uimm5, vb); auto vb_v4f32 = GetVrAsFloatVec(vb);
if (uimm5) {
vb_v4f32 = m_ir_builder->CreateFMul(vb_v4f32, m_ir_builder->CreateVectorSplat(4, ConstantFP::get(m_ir_builder->getFloatTy(), 1 << uimm5)));
}
auto res_v4f32 = (Value *)m_ir_builder->CreateCall2(Intrinsic::getDeclaration(m_module, Intrinsic::x86_sse_max_ps), vb_v4f32, m_ir_builder->CreateVectorSplat(4, ConstantFP::get(m_ir_builder->getFloatTy(), 0)));
auto cmp_v4i1 = m_ir_builder->CreateFCmpOGE(res_v4f32, m_ir_builder->CreateVectorSplat(4, ConstantFP::get(m_ir_builder->getFloatTy(), 0xFFFFFFFFu)));
auto cmp_v4i32 = m_ir_builder->CreateSExt(cmp_v4i1, VectorType::get(m_ir_builder->getInt32Ty(), 4));
auto res_v4i32 = m_ir_builder->CreateFPToUI(res_v4f32, VectorType::get(m_ir_builder->getInt32Ty(), 4));
res_v4i32 = m_ir_builder->CreateOr(res_v4i32, cmp_v4i32);
SetVr(vd, res_v4i32);
// TODO: Set VSCR.SAT
} }
void Compiler::VEXPTEFP(u32 vd, u32 vb) { void Compiler::VEXPTEFP(u32 vd, u32 vb) {
InterpreterCall("VEXPTEFP", &PPUInterpreter::VEXPTEFP, vd, vb); auto vb_v4f32 = GetVrAsFloatVec(vb);
auto res_v4f32 = (Value *)m_ir_builder->CreateCall2(Intrinsic::getDeclaration(m_module, Intrinsic::pow, VectorType::get(m_ir_builder->getFloatTy(), 4)),
m_ir_builder->CreateVectorSplat(4, ConstantFP::get(m_ir_builder->getFloatTy(), 2.0f)), vb_v4f32);
SetVr(vd, res_v4f32);
} }
void Compiler::VLOGEFP(u32 vd, u32 vb) { void Compiler::VLOGEFP(u32 vd, u32 vb) {
InterpreterCall("VLOGEFP", &PPUInterpreter::VLOGEFP, vd, vb); auto vb_v4f32 = GetVrAsFloatVec(vb);
auto res_v4f32 = (Value *)m_ir_builder->CreateCall(Intrinsic::getDeclaration(m_module, Intrinsic::log2, VectorType::get(m_ir_builder->getFloatTy(), 4)), vb_v4f32);
SetVr(vd, res_v4f32);
} }
void Compiler::VMADDFP(u32 vd, u32 va, u32 vc, u32 vb) { void Compiler::VMADDFP(u32 vd, u32 va, u32 vc, u32 vb) {
@ -798,11 +826,46 @@ void Compiler::VMAXUW(u32 vd, u32 va, u32 vb) {
} }
void Compiler::VMHADDSHS(u32 vd, u32 va, u32 vb, u32 vc) { void Compiler::VMHADDSHS(u32 vd, u32 va, u32 vb, u32 vc) {
InterpreterCall("VMHADDSHS", &PPUInterpreter::VMHADDSHS, vd, va, vb, vc); auto va_v8i16 = GetVrAsIntVec(va, 16);
auto vb_v8i16 = GetVrAsIntVec(vb, 16);
auto vc_v8i16 = GetVrAsIntVec(vc, 16);
auto va_v8i32 = m_ir_builder->CreateSExt(va_v8i16, VectorType::get(m_ir_builder->getInt32Ty(), 8));
auto vb_v8i32 = m_ir_builder->CreateSExt(vb_v8i16, VectorType::get(m_ir_builder->getInt32Ty(), 8));
auto vc_v8i32 = m_ir_builder->CreateSExt(vc_v8i16, VectorType::get(m_ir_builder->getInt32Ty(), 8));
auto res_v8i32 = m_ir_builder->CreateMul(va_v8i32, vb_v8i32);
res_v8i32 = m_ir_builder->CreateAShr(res_v8i32, 15);
res_v8i32 = m_ir_builder->CreateAdd(res_v8i32, vc_v8i32);
u32 mask1_v4i32[4] = {0, 1, 2, 3};
auto res1_v4i32 = m_ir_builder->CreateShuffleVector(res_v8i32, UndefValue::get(VectorType::get(m_ir_builder->getInt32Ty(), 8)), ConstantDataVector::get(m_ir_builder->getContext(), mask1_v4i32));
u32 mask2_v4i32[4] = {4, 5, 6, 7};
auto res2_v4i32 = m_ir_builder->CreateShuffleVector(res_v8i32, UndefValue::get(VectorType::get(m_ir_builder->getInt32Ty(), 8)), ConstantDataVector::get(m_ir_builder->getContext(), mask2_v4i32));
auto res_v8i16 = m_ir_builder->CreateCall2(Intrinsic::getDeclaration(m_module, Intrinsic::x86_sse2_packssdw_128), res1_v4i32, res2_v4i32);
SetVr(vd, res_v8i16);
// TODO: Set VSCR.SAT
} }
void Compiler::VMHRADDSHS(u32 vd, u32 va, u32 vb, u32 vc) { void Compiler::VMHRADDSHS(u32 vd, u32 va, u32 vb, u32 vc) {
InterpreterCall("VMHRADDSHS", &PPUInterpreter::VMHRADDSHS, vd, va, vb, vc); auto va_v8i16 = GetVrAsIntVec(va, 16);
auto vb_v8i16 = GetVrAsIntVec(vb, 16);
auto vc_v8i16 = GetVrAsIntVec(vc, 16);
auto va_v8i32 = m_ir_builder->CreateSExt(va_v8i16, VectorType::get(m_ir_builder->getInt32Ty(), 8));
auto vb_v8i32 = m_ir_builder->CreateSExt(vb_v8i16, VectorType::get(m_ir_builder->getInt32Ty(), 8));
auto vc_v8i32 = m_ir_builder->CreateSExt(vc_v8i16, VectorType::get(m_ir_builder->getInt32Ty(), 8));
auto res_v8i32 = m_ir_builder->CreateMul(va_v8i32, vb_v8i32);
res_v8i32 = m_ir_builder->CreateAdd(res_v8i32, m_ir_builder->CreateVectorSplat(8, m_ir_builder->getInt32(0x4000)));
res_v8i32 = m_ir_builder->CreateAShr(res_v8i32, 15);
res_v8i32 = m_ir_builder->CreateAdd(res_v8i32, vc_v8i32);
u32 mask1_v4i32[4] = {0, 1, 2, 3};
auto res1_v4i32 = m_ir_builder->CreateShuffleVector(res_v8i32, UndefValue::get(VectorType::get(m_ir_builder->getInt32Ty(), 8)), ConstantDataVector::get(m_ir_builder->getContext(), mask1_v4i32));
u32 mask2_v4i32[4] = {4, 5, 6, 7};
auto res2_v4i32 = m_ir_builder->CreateShuffleVector(res_v8i32, UndefValue::get(VectorType::get(m_ir_builder->getInt32Ty(), 8)), ConstantDataVector::get(m_ir_builder->getContext(), mask2_v4i32));
auto res_v8i16 = m_ir_builder->CreateCall2(Intrinsic::getDeclaration(m_module, Intrinsic::x86_sse2_packssdw_128), res1_v4i32, res2_v4i32);
SetVr(vd, res_v8i16);
// TODO: Set VSCR.SAT
} }
void Compiler::VMINFP(u32 vd, u32 va, u32 vb) { void Compiler::VMINFP(u32 vd, u32 va, u32 vb) {
@ -855,7 +918,12 @@ void Compiler::VMINUW(u32 vd, u32 va, u32 vb) {
} }
void Compiler::VMLADDUHM(u32 vd, u32 va, u32 vb, u32 vc) { void Compiler::VMLADDUHM(u32 vd, u32 va, u32 vb, u32 vc) {
InterpreterCall("VMLADDUHM", &PPUInterpreter::VMLADDUHM, vd, va, vb, vc); auto va_v8i16 = GetVrAsIntVec(va, 16);
auto vb_v8i16 = GetVrAsIntVec(vb, 16);
auto vc_v8i16 = GetVrAsIntVec(vc, 16);
auto res_v8i16 = m_ir_builder->CreateMul(va_v8i16, vb_v8i16);
res_v8i16 = m_ir_builder->CreateAdd(res_v8i16, vc_v8i16);
SetVr(vd, res_v8i16);
} }
void Compiler::VMRGHB(u32 vd, u32 va, u32 vb) { void Compiler::VMRGHB(u32 vd, u32 va, u32 vb) {
@ -1010,35 +1078,83 @@ void Compiler::VMSUMUHS(u32 vd, u32 va, u32 vb, u32 vc) {
} }
void Compiler::VMULESB(u32 vd, u32 va, u32 vb) { void Compiler::VMULESB(u32 vd, u32 va, u32 vb) {
InterpreterCall("VMULESB", &PPUInterpreter::VMULESB, vd, va, vb); auto va_v8i16 = GetVrAsIntVec(va, 16);
auto vb_v8i16 = GetVrAsIntVec(vb, 16);
va_v8i16 = m_ir_builder->CreateAShr(va_v8i16, 8);
vb_v8i16 = m_ir_builder->CreateAShr(vb_v8i16, 8);
auto res_v8i16 = m_ir_builder->CreateMul(va_v8i16, vb_v8i16);
SetVr(vd, res_v8i16);
} }
void Compiler::VMULESH(u32 vd, u32 va, u32 vb) { void Compiler::VMULESH(u32 vd, u32 va, u32 vb) {
InterpreterCall("VMULESH", &PPUInterpreter::VMULESH, vd, va, vb); auto va_v4i32 = GetVrAsIntVec(va, 32);
auto vb_v4i32 = GetVrAsIntVec(vb, 32);
va_v4i32 = m_ir_builder->CreateAShr(va_v4i32, 16);
vb_v4i32 = m_ir_builder->CreateAShr(vb_v4i32, 16);
auto res_v4i32 = m_ir_builder->CreateMul(va_v4i32, vb_v4i32);
SetVr(vd, res_v4i32);
} }
void Compiler::VMULEUB(u32 vd, u32 va, u32 vb) { void Compiler::VMULEUB(u32 vd, u32 va, u32 vb) {
InterpreterCall("VMULEUB", &PPUInterpreter::VMULEUB, vd, va, vb); auto va_v8i16 = GetVrAsIntVec(va, 16);
auto vb_v8i16 = GetVrAsIntVec(vb, 16);
va_v8i16 = m_ir_builder->CreateLShr(va_v8i16, 8);
vb_v8i16 = m_ir_builder->CreateLShr(vb_v8i16, 8);
auto res_v8i16 = m_ir_builder->CreateMul(va_v8i16, vb_v8i16);
SetVr(vd, res_v8i16);
} }
void Compiler::VMULEUH(u32 vd, u32 va, u32 vb) { void Compiler::VMULEUH(u32 vd, u32 va, u32 vb) {
InterpreterCall("VMULEUH", &PPUInterpreter::VMULEUH, vd, va, vb); auto va_v4i32 = GetVrAsIntVec(va, 32);
auto vb_v4i32 = GetVrAsIntVec(vb, 32);
va_v4i32 = m_ir_builder->CreateLShr(va_v4i32, 16);
vb_v4i32 = m_ir_builder->CreateLShr(vb_v4i32, 16);
auto res_v4i32 = m_ir_builder->CreateMul(va_v4i32, vb_v4i32);
SetVr(vd, res_v4i32);
} }
void Compiler::VMULOSB(u32 vd, u32 va, u32 vb) { void Compiler::VMULOSB(u32 vd, u32 va, u32 vb) {
InterpreterCall("VMULOSB", &PPUInterpreter::VMULOSB, vd, va, vb); auto va_v8i16 = GetVrAsIntVec(va, 16);
auto vb_v8i16 = GetVrAsIntVec(vb, 16);
va_v8i16 = m_ir_builder->CreateShl(va_v8i16, 8);
va_v8i16 = m_ir_builder->CreateAShr(va_v8i16, 8);
vb_v8i16 = m_ir_builder->CreateShl(vb_v8i16, 8);
vb_v8i16 = m_ir_builder->CreateAShr(vb_v8i16, 8);
auto res_v8i16 = m_ir_builder->CreateMul(va_v8i16, vb_v8i16);
SetVr(vd, res_v8i16);
} }
void Compiler::VMULOSH(u32 vd, u32 va, u32 vb) { void Compiler::VMULOSH(u32 vd, u32 va, u32 vb) {
InterpreterCall("VMULOSH", &PPUInterpreter::VMULOSH, vd, va, vb); auto va_v4i32 = GetVrAsIntVec(va, 32);
auto vb_v4i32 = GetVrAsIntVec(vb, 32);
va_v4i32 = m_ir_builder->CreateShl(va_v4i32, 16);
va_v4i32 = m_ir_builder->CreateAShr(va_v4i32, 16);
vb_v4i32 = m_ir_builder->CreateShl(vb_v4i32, 16);
vb_v4i32 = m_ir_builder->CreateAShr(vb_v4i32, 16);
auto res_v4i32 = m_ir_builder->CreateMul(va_v4i32, vb_v4i32);
SetVr(vd, res_v4i32);
} }
void Compiler::VMULOUB(u32 vd, u32 va, u32 vb) { void Compiler::VMULOUB(u32 vd, u32 va, u32 vb) {
InterpreterCall("VMULOUB", &PPUInterpreter::VMULOUB, vd, va, vb); auto va_v8i16 = GetVrAsIntVec(va, 16);
auto vb_v8i16 = GetVrAsIntVec(vb, 16);
va_v8i16 = m_ir_builder->CreateShl(va_v8i16, 8);
va_v8i16 = m_ir_builder->CreateLShr(va_v8i16, 8);
vb_v8i16 = m_ir_builder->CreateShl(vb_v8i16, 8);
vb_v8i16 = m_ir_builder->CreateLShr(vb_v8i16, 8);
auto res_v8i16 = m_ir_builder->CreateMul(va_v8i16, vb_v8i16);
SetVr(vd, res_v8i16);
} }
void Compiler::VMULOUH(u32 vd, u32 va, u32 vb) { void Compiler::VMULOUH(u32 vd, u32 va, u32 vb) {
InterpreterCall("VMULOUH", &PPUInterpreter::VMULOUH, vd, va, vb); auto va_v4i32 = GetVrAsIntVec(va, 32);
auto vb_v4i32 = GetVrAsIntVec(vb, 32);
va_v4i32 = m_ir_builder->CreateShl(va_v4i32, 16);
va_v4i32 = m_ir_builder->CreateLShr(va_v4i32, 16);
vb_v4i32 = m_ir_builder->CreateShl(vb_v4i32, 16);
vb_v4i32 = m_ir_builder->CreateLShr(vb_v4i32, 16);
auto res_v4i32 = m_ir_builder->CreateMul(va_v4i32, vb_v4i32);
SetVr(vd, res_v4i32);
} }
void Compiler::VNMSUBFP(u32 vd, u32 va, u32 vc, u32 vb) { void Compiler::VNMSUBFP(u32 vd, u32 va, u32 vc, u32 vb) {

29
rpcs3/Emu/Cell/PPULLVMRecompilerTests.cpp
View file

@ -8,7 +8,7 @@
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include "llvm/MC/MCDisassembler.h" #include "llvm/MC/MCDisassembler.h"
//#define PPU_LLVM_RECOMPILER_UNIT_TESTS 1 #define PPU_LLVM_RECOMPILER_UNIT_TESTS 1
using namespace llvm; using namespace llvm;
using namespace ppu_recompiler_llvm; using namespace ppu_recompiler_llvm;
@ -63,7 +63,7 @@ VerifyInstructionAgainstInterpreter(fmt::Format("%s.%d", #fn, tc).c_str(), &Comp
u64 R_ADDR; u64 R_ADDR;
u64 R_VALUE; u64 R_VALUE;
/// Mmeory block /// Memory block
u32 address; u32 address;
u64 mem_block[64]; u64 mem_block[64];
@ -130,9 +130,9 @@ VerifyInstructionAgainstInterpreter(fmt::Format("%s.%d", #fn, tc).c_str(), &Comp
FPR[i] = (double)rng(); FPR[i] = (double)rng();
GPR[i] = rng(); GPR[i] = rng();
VPR[i]._f[0] = (float)rng(); VPR[i]._f[0] = (float)rng();
VPR[i]._f[1] = (float)rng(); VPR[i]._f[1] = (float)(rng() & 0x7FFFFFFF);
VPR[i]._f[2] = (float)rng(); VPR[i]._f[2] = -(float)(rng() & 0x7FFFFFFF);
VPR[i]._f[3] = (float)rng(); VPR[i]._f[3] = -(float)rng();
if (i < 8) { if (i < 8) {
SPRG[i] = rng(); SPRG[i] = rng();
@ -265,7 +265,7 @@ void Compiler::RunTest(const char * name, std::function<void()> test_case, std::
std::string verify_results; std::string verify_results;
raw_string_ostream verify_results_ostream(verify_results); raw_string_ostream verify_results_ostream(verify_results);
if (verifyFunction(*m_state.function, &verify_results_ostream)) { if (verifyFunction(*m_state.function, &verify_results_ostream)) {
m_recompilation_engine.Log() << "Verification Failed:" << verify_results; m_recompilation_engine.Log() << "Verification Failed:\n" << verify_results;
return; return;
} }
@ -400,6 +400,12 @@ void Compiler::RunAllTests() {
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VCMPGTUW, 5, 5, 0, 1, 1); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VCMPGTUW, 5, 5, 0, 1, 1);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VCMPGTUW_, 0, 5, 0, 1, 2); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VCMPGTUW_, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VCMPGTUW_, 5, 5, 0, 1, 1); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VCMPGTUW_, 5, 5, 0, 1, 1);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VCTSXS, 0, 5, 0, 0, 1);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VCTSXS, 5, 5, 0, 3, 1);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VCTUXS, 0, 5, 0, 0, 1);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VCTUXS, 5, 5, 0, 3, 1);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VEXPTEFP, 0, 5, 0, 1);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VLOGEFP, 0, 5, 0, 1);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMADDFP, 0, 5, 0, 1, 2, 3); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMADDFP, 0, 5, 0, 1, 2, 3);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMAXFP, 0, 5, 0, 1, 2); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMAXFP, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMAXSB, 0, 5, 0, 1, 2); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMAXSB, 0, 5, 0, 1, 2);
@ -408,6 +414,8 @@ void Compiler::RunAllTests() {
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMAXUB, 0, 5, 0, 1, 2); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMAXUB, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMAXUH, 0, 5, 0, 1, 2); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMAXUH, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMAXUW, 0, 5, 0, 1, 2); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMAXUW, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMHADDSHS, 0, 5, 0, 1, 2, 3);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMHRADDSHS, 0, 5, 0, 1, 2, 3);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMINFP, 0, 5, 0, 1, 2); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMINFP, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMINSB, 0, 5, 0, 1, 2); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMINSB, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMINSH, 0, 5, 0, 1, 2); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMINSH, 0, 5, 0, 1, 2);
@ -415,6 +423,7 @@ void Compiler::RunAllTests() {
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMINUB, 0, 5, 0, 1, 2); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMINUB, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMINUH, 0, 5, 0, 1, 2); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMINUH, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMINUW, 0, 5, 0, 1, 2); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMINUW, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMLADDUHM, 0, 5, 0, 1, 2, 3);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMRGHB, 0, 5, 0, 1, 2); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMRGHB, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMRGHH, 0, 5, 0, 1, 2); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMRGHH, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMRGHW, 0, 5, 0, 1, 2); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMRGHW, 0, 5, 0, 1, 2);
@ -426,6 +435,14 @@ void Compiler::RunAllTests() {
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMSUMUBM, 0, 5, 0, 1, 2, 3); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMSUMUBM, 0, 5, 0, 1, 2, 3);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMSUMUHM, 0, 5, 0, 1, 2, 3); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMSUMUHM, 0, 5, 0, 1, 2, 3);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VNMSUBFP, 0, 5, 0, 1, 2, 3); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VNMSUBFP, 0, 5, 0, 1, 2, 3);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMULESB, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMULESH, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMULEUB, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMULEUH, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMULOSB, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMULOSH, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMULOUB, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VMULOUH, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VNOR, 0, 5, 0, 1, 2); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VNOR, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VOR, 0, 5, 0, 1, 2); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VOR, 0, 5, 0, 1, 2);
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VPERM, 0, 5, 0, 1, 2, 3); VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VPERM, 0, 5, 0, 1, 2, 3);