mirror of
https://github.com/RPCS3/rpcs3.git
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SPU LLVM/ASMJIT: fix BRA/BRASL instructions for PIC
Handle absolute branch addressing correctly.
This commit is contained in:
Nekotekina
parent
f95ec8a37c
commit
91897fa69d
3 changed files with 110 additions and 86 deletions
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@ -952,7 +952,7 @@ static void check_state(spu_thread* _spu)
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}
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}
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void spu_recompiler::branch_fixed(u32 target)
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void spu_recompiler::branch_fixed(u32 target, bool absolute)
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{
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using namespace asmjit;
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@ -961,6 +961,15 @@ void spu_recompiler::branch_fixed(u32 target)
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if (local != instr_labels.end() && local->second.isValid())
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{
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Label fail;
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if (absolute)
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{
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fail = c->newLabel();
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c->cmp(pc0->r32(), m_base);
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c->jne(fail);
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}
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c->cmp(SPU_OFF_32(state), 0);
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c->jz(local->second);
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c->lea(addr->r64(), get_pc(target));
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@ -969,14 +978,30 @@ void spu_recompiler::branch_fixed(u32 target)
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c->mov(*arg0, *cpu);
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c->call(imm_ptr(&check_state));
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c->jmp(local->second);
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return;
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if (absolute)
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{
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c->bind(fail);
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}
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else
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{
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return;
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}
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}
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const auto ppptr = !g_cfg.core.spu_verification ? nullptr : m_spurt->make_branch_patchpoint();
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c->lea(addr->r64(), get_pc(target));
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c->and_(*addr, 0x3fffc);
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c->mov(SPU_OFF_32(pc), *addr);
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if (absolute)
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{
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c->mov(SPU_OFF_32(pc), target);
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}
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else
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{
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c->lea(addr->r64(), get_pc(target));
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c->and_(*addr, 0x3fffc);
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c->mov(SPU_OFF_32(pc), *addr);
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}
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c->xor_(rip->r32(), rip->r32());
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c->cmp(SPU_OFF_32(state), 0);
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c->jnz(label_stop);
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@ -4132,11 +4157,8 @@ void spu_recompiler::BRA(spu_opcode_t op)
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{
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const u32 target = spu_branch_target(0, op.i16);
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if (target != m_pos + 4)
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{
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branch_fixed(target);
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m_pos = -1;
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}
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branch_fixed(target, true);
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m_pos = -1;
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}
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void spu_recompiler::LQA(spu_opcode_t op)
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@ -4170,12 +4192,9 @@ void spu_recompiler::BRASL(spu_opcode_t op)
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c->pslldq(vr, 12);
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c->movdqa(SPU_OFF_128(gpr, op.rt), vr);
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if (target != m_pos + 4)
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{
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branch_set_link(m_pos + 4);
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branch_fixed(target);
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m_pos = -1;
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}
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branch_set_link(m_pos + 4);
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branch_fixed(target, true);
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m_pos = -1;
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}
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void spu_recompiler::BR(spu_opcode_t op)
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@ -90,7 +90,7 @@ private:
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asmjit::X86Mem XmmConst(__m128i data);
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asmjit::X86Mem get_pc(u32 addr);
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void branch_fixed(u32 target);
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void branch_fixed(u32 target, bool absolute = false);
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void branch_indirect(spu_opcode_t op, bool jt = false, bool ret = true);
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void branch_set_link(u32 target);
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void fall(spu_opcode_t op);
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@ -1344,14 +1344,7 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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{
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const u32 target = spu_branch_target(av);
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if (target == pos + 4)
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{
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LOG_WARNING(SPU, "[0x%x] At 0x%x: indirect branch to next%s", result[0], pos, op.d ? " (D)" : op.e ? " (E)" : "");
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}
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else
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{
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LOG_WARNING(SPU, "[0x%x] At 0x%x: indirect branch to 0x%x", result[0], pos, target);
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}
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LOG_WARNING(SPU, "[0x%x] At 0x%x: indirect branch to 0x%x%s", result[0], pos, target, op.d ? " (D)" : op.e ? " (E)" : "");
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m_targets[pos].push_back(target);
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@ -1368,11 +1361,7 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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}
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else
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{
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if (op.d || op.e)
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{
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m_entry_info[target / 4] = true;
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}
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m_entry_info[target / 4] = true;
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add_block(target);
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}
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}
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@ -1578,7 +1567,7 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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vflags[op.rt] = +vf::is_const;
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values[op.rt] = pos + 4;
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if (target == pos + 4)
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if (type == spu_itype::BRSL && target == pos + 4)
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{
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// Get next instruction address idiom
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break;
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@ -1616,14 +1605,39 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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break;
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}
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case spu_itype::BR:
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case spu_itype::BRA:
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{
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const u32 target = spu_branch_target(0, op.i16);
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if (g_cfg.core.spu_block_size == spu_block_size_type::giga && !sync)
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{
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m_entry_info[target / 4] = true;
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add_block(target);
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}
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else
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{
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if (g_cfg.core.spu_block_size == spu_block_size_type::giga)
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{
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LOG_NOTICE(SPU, "[0x%x] At 0x%x: ignoring fixed tail call to 0x%x (SYNC)", result[0], pos, target);
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}
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if (target > entry_point)
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{
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limit = std::min<u32>(limit, target);
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}
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}
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next_block();
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break;
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}
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case spu_itype::BR:
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case spu_itype::BRZ:
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case spu_itype::BRNZ:
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case spu_itype::BRHZ:
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case spu_itype::BRHNZ:
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{
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const u32 target = spu_branch_target(type == spu_itype::BRA ? 0 : pos, op.i16);
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const u32 target = spu_branch_target(pos, op.i16);
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if (target == pos + 4)
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{
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@ -1634,7 +1648,7 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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m_targets[pos].push_back(target);
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add_block(target);
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if (type != spu_itype::BR && type != spu_itype::BRA)
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if (type != spu_itype::BR)
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{
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m_targets[pos].push_back(pos + 4);
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add_block(pos + 4);
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@ -2193,6 +2207,10 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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case spu_itype::BRASL:
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is_call = spu_branch_target(0, op.i16) != ia + 4;
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break;
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case spu_itype::BRA:
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is_call = true;
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is_tail = true;
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break;
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case spu_itype::BISL:
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case spu_itype::BISLED:
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is_call = true;
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@ -2779,21 +2797,19 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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switch (last_inst)
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{
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case spu_itype::BR:
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case spu_itype::BRA:
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case spu_itype::BRNZ:
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case spu_itype::BRZ:
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case spu_itype::BRHNZ:
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case spu_itype::BRHZ:
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case spu_itype::BRSL:
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case spu_itype::BRASL:
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{
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const u32 target = spu_branch_target(last_inst == spu_itype::BRA || last_inst == spu_itype::BRASL ? 0 : tia, op.i16);
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const u32 target = spu_branch_target(tia, op.i16);
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if (target == tia + 4)
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{
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bb.terminator = term_type::fallthrough;
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}
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else if (last_inst != spu_itype::BRSL && last_inst != spu_itype::BRASL)
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else if (last_inst != spu_itype::BRSL)
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{
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// No-op terminator or simple branch instruction
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bb.terminator = term_type::br;
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@ -2815,6 +2831,12 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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break;
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}
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case spu_itype::BRA:
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case spu_itype::BRASL:
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{
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bb.terminator = term_type::indirect_call;
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break;
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}
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case spu_itype::BI:
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{
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if (op.d || op.e || bb.targets.size() == 1)
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@ -3449,7 +3471,7 @@ class spu_llvm_recompiler : public spu_recompiler_base, public cpu_translator
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}
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// Add block with current block as a predecessor
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llvm::BasicBlock* add_block(u32 target)
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llvm::BasicBlock* add_block(u32 target, bool absolute = false)
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{
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// Check the predecessor
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const bool pred_found = m_block_info[target / 4] && m_preds[target].find_first_of(m_pos) + 1;
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@ -3497,6 +3519,19 @@ class spu_llvm_recompiler : public spu_recompiler_base, public cpu_translator
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m_ir->SetInsertPoint(result);
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const auto pfinfo = add_function(target);
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if (absolute)
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{
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verify(HERE), !m_finfo->fn;
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const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
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const auto fail = llvm::BasicBlock::Create(m_context, "", m_function);
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m_ir->CreateCondBr(m_ir->CreateICmpEQ(m_base_pc, m_ir->getInt32(m_base)), next, fail);
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m_ir->SetInsertPoint(fail);
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m_ir->CreateStore(m_ir->getInt32(target), spu_ptr<u32>(&spu_thread::pc), true);
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tail_chunk(nullptr);
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m_ir->SetInsertPoint(next);
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}
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if (pfinfo->fn)
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{
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// Tail call to the real function
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@ -3525,12 +3560,25 @@ class spu_llvm_recompiler : public spu_recompiler_base, public cpu_translator
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const auto cblock = m_ir->GetInsertBlock();
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const auto result = llvm::BasicBlock::Create(m_context, "", m_function);
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m_ir->SetInsertPoint(result);
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update_pc(target);
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if (absolute)
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{
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verify(HERE), !m_finfo->fn;
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m_ir->CreateStore(m_ir->getInt32(target), spu_ptr<u32>(&spu_thread::pc), true);
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}
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else
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{
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update_pc(target);
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}
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tail_chunk(nullptr);
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m_ir->SetInsertPoint(cblock);
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return result;
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}
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verify(HERE), !absolute;
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auto& result = m_blocks[target].block;
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if (!result)
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@ -7639,34 +7687,11 @@ public:
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return result;
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}
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// Convert an indirect branch into a static one if possible
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if (const auto _int = llvm::dyn_cast<llvm::ConstantInt>(addr.value); _int && op.opcode)
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if (llvm::isa<llvm::Constant>(addr.value))
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{
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const u32 target = ::narrow<u32>(_int->getZExtValue(), HERE);
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LOG_WARNING(SPU, "[0x%x] Fixed branch to 0x%x", m_pos, target);
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if (!op.e && !op.d)
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{
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return add_block(target);
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}
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if (!m_entry_info[target / 4])
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{
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LOG_ERROR(SPU, "[0x%x] Fixed branch to 0x%x", m_pos, target);
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}
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else
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{
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add_function(target);
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}
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// Fixed branch excludes the possibility it's a function return (TODO)
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ret = false;
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}
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else if (llvm::isa<llvm::Constant>(addr.value) && op.opcode)
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{
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LOG_ERROR(SPU, "[0x%x] Unexpected constant (add_block_indirect)", m_pos);
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}
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if (m_finfo && m_finfo->fn && op.opcode)
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{
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@ -8011,33 +8036,13 @@ public:
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const u32 target = spu_branch_target(0, op.i16);
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if (target != m_pos + 4)
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{
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m_block->block_end = m_ir->GetInsertBlock();
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m_ir->CreateBr(add_block(target));
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}
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m_block->block_end = m_ir->GetInsertBlock();
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m_ir->CreateBr(add_block(target, true));
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}
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void BRASL(spu_opcode_t op) //
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{
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set_link(op);
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const u32 target = spu_branch_target(0, op.i16);
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if (m_finfo && m_finfo->fn && target != m_pos + 4)
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{
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if (auto fn = add_function(target)->fn)
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{
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call_function(fn);
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return;
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}
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else
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{
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LOG_FATAL(SPU, "[0x%x] Can't add function 0x%x", m_pos, target);
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return;
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}
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}
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BRA(op);
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}
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