mirror of
https://github.com/RPCS3/rpcs3.git
synced 2025-07-16 11:48:36 +12:00
- Fixed loading modules in debug mode.
- Improved Lwmutex. - Implemented events syscalls. - Fixed SPU local storage.
This commit is contained in:
DH
parent
991f281bbd
commit
6d7d3acb43
39 changed files with 1639 additions and 902 deletions
|
|
@ -1,29 +1,30 @@
|
|||
#pragma once
|
||||
#include "PPCThread.h"
|
||||
#include "Emu/event.h"
|
||||
|
||||
static const wxString spu_reg_name[128] =
|
||||
{
|
||||
"$LR", "$SP", "$3", "$4", "$5", "$6", "$7", "$8",
|
||||
"$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16",
|
||||
"$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24",
|
||||
"$25", "$26", "$27", "$28", "$29", "$30", "$31", "$32",
|
||||
"$33", "$34", "$35", "$36", "$37", "$38", "$39", "$40",
|
||||
"$41", "$42", "$43", "$44", "$45", "$46", "$47", "$48",
|
||||
"$49", "$50", "$51", "$52", "$53", "$54", "$55", "$56",
|
||||
"$57", "$58", "$59", "$60", "$61", "$62", "$63", "$64",
|
||||
"$65", "$66", "$67", "$68", "$69", "$70", "$71", "$72",
|
||||
"$73", "$74", "$75", "$76", "$77", "$78", "$79", "$80",
|
||||
"$81", "$82", "$83", "$84", "$85", "$86", "$87", "$88",
|
||||
"$89", "$90", "$91", "$92", "$93", "$94", "$95", "$96",
|
||||
"$97", "$98", "$99", "$100", "$101", "$102", "$103", "$104",
|
||||
"$105", "$106", "$107", "$108", "$109", "$110", "$111", "$112",
|
||||
"$113", "$114", "$115", "$116", "$117", "$118", "$119", "$120",
|
||||
"$121", "$122", "$123", "$124", "$125", "$126", "$127",
|
||||
"$LR", "$SP", "$2", "$3", "$4", "$5", "$6", "$7",
|
||||
"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
|
||||
"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
|
||||
"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
|
||||
"$32", "$33", "$34", "$35", "$36", "$37", "$38", "$39",
|
||||
"$40", "$41", "$42", "$43", "$44", "$45", "$46", "$47",
|
||||
"$48", "$49", "$50", "$51", "$52", "$53", "$54", "$55",
|
||||
"$56", "$57", "$58", "$59", "$60", "$61", "$62", "$63",
|
||||
"$64", "$65", "$66", "$67", "$68", "$69", "$70", "$71",
|
||||
"$72", "$73", "$74", "$75", "$76", "$77", "$78", "$79",
|
||||
"$80", "$81", "$82", "$83", "$84", "$85", "$86", "$87",
|
||||
"$88", "$89", "$90", "$91", "$92", "$93", "$94", "$95",
|
||||
"$96", "$97", "$98", "$99", "$100", "$101", "$102", "$103",
|
||||
"$104", "$105", "$106", "$107", "$108", "$109", "$110", "$111",
|
||||
"$112", "$113", "$114", "$115", "$116", "$117", "$118", "$119",
|
||||
"$120", "$121", "$122", "$123", "$124", "$125", "$126", "$127",
|
||||
};
|
||||
|
||||
static const wxString spu_ch_name[128] =
|
||||
{
|
||||
"$SPU_RdEventStat", "$SPU_WrEventMask", "$SPU_RdSigNotify1",
|
||||
"$SPU_RdEventStat", "$SPU_WrEventMask", "$SPU_WrEventAck", "$SPU_RdSigNotify1",
|
||||
"$SPU_RdSigNotify2", "$ch5", "$ch6", "$SPU_WrDec", "$SPU_RdDec",
|
||||
"$MFC_WrMSSyncReq", "$ch10", "$SPU_RdEventMask", "$MFC_RdTagMask", "$SPU_RdMachStat",
|
||||
"$SPU_WrSRR0", "$SPU_RdSRR0", "$MFC_LSA", "$MFC_EAH", "$MFC_EAL", "$MFC_Size",
|
||||
|
|
@ -82,8 +83,6 @@ enum MFCchannels
|
|||
|
||||
union SPU_GPR_hdr
|
||||
{
|
||||
//__m128i _m128i;
|
||||
|
||||
u128 _u128;
|
||||
s128 _i128;
|
||||
u64 _u64[2];
|
||||
|
|
@ -96,19 +95,6 @@ union SPU_GPR_hdr
|
|||
s8 _i8[16];
|
||||
|
||||
SPU_GPR_hdr() {}
|
||||
/*
|
||||
SPU_GPR_hdr(const __m128i val){_u128._u64[0] = val.m128i_u64[0]; _u128._u64[1] = val.m128i_u64[1];}
|
||||
SPU_GPR_hdr(const u128 val) { _u128 = val; }
|
||||
SPU_GPR_hdr(const u64 val) { Reset(); _u64[0] = val; }
|
||||
SPU_GPR_hdr(const u32 val) { Reset(); _u32[0] = val; }
|
||||
SPU_GPR_hdr(const u16 val) { Reset(); _u16[0] = val; }
|
||||
SPU_GPR_hdr(const u8 val) { Reset(); _u8[0] = val; }
|
||||
SPU_GPR_hdr(const s128 val) { _i128 = val; }
|
||||
SPU_GPR_hdr(const s64 val) { Reset(); _i64[0] = val; }
|
||||
SPU_GPR_hdr(const s32 val) { Reset(); _i32[0] = val; }
|
||||
SPU_GPR_hdr(const s16 val) { Reset(); _i16[0] = val; }
|
||||
SPU_GPR_hdr(const s8 val) { Reset(); _i8[0] = val; }
|
||||
*/
|
||||
|
||||
wxString ToString() const
|
||||
{
|
||||
|
|
@ -119,41 +105,17 @@ union SPU_GPR_hdr
|
|||
{
|
||||
memset(this, 0, sizeof(*this));
|
||||
}
|
||||
|
||||
//operator __m128i() { __m128i ret; ret.m128i_u64[0]=_u128._u64[0]; ret.m128i_u64[1]=_u128._u64[1]; return ret; }
|
||||
/*
|
||||
SPU_GPR_hdr operator ^ (__m128i right) { return _mm_xor_si128(*this, right); }
|
||||
SPU_GPR_hdr operator | (__m128i right) { return _mm_or_si128 (*this, right); }
|
||||
SPU_GPR_hdr operator & (__m128i right) { return _mm_and_si128(*this, right); }
|
||||
SPU_GPR_hdr operator << (int right) { return _mm_slli_epi32(*this, right); }
|
||||
SPU_GPR_hdr operator << (__m128i right) { return _mm_sll_epi32(*this, right); }
|
||||
SPU_GPR_hdr operator >> (int right) { return _mm_srai_epi32(*this, right); }
|
||||
SPU_GPR_hdr operator >> (__m128i right) { return _mm_sra_epi32(*this, right); }
|
||||
|
||||
SPU_GPR_hdr operator | (__m128i right) { return _mm_or_si128 (*this, right); }
|
||||
SPU_GPR_hdr operator & (__m128i right) { return _mm_and_si128(*this, right); }
|
||||
SPU_GPR_hdr operator << (int right) { return _mm_slli_epi32(*this, right); }
|
||||
SPU_GPR_hdr operator << (__m128i right) { return _mm_sll_epi32(*this, right); }
|
||||
SPU_GPR_hdr operator >> (int right) { return _mm_srai_epi32(*this, right); }
|
||||
SPU_GPR_hdr operator >> (__m128i right) { return _mm_sra_epi32(*this, right); }
|
||||
|
||||
SPU_GPR_hdr operator ^= (__m128i right) { return *this = *this ^ right; }
|
||||
SPU_GPR_hdr operator |= (__m128i right) { return *this = *this | right; }
|
||||
SPU_GPR_hdr operator &= (__m128i right) { return *this = *this & right; }
|
||||
SPU_GPR_hdr operator <<= (int right) { return *this = *this << right; }
|
||||
SPU_GPR_hdr operator <<= (__m128i right){ return *this = *this << right; }
|
||||
SPU_GPR_hdr operator >>= (int right) { return *this = *this >> right; }
|
||||
SPU_GPR_hdr operator >>= (__m128i right){ return *this = *this >> right; }
|
||||
*/
|
||||
};
|
||||
|
||||
class SPUThread : public PPCThread
|
||||
{
|
||||
public:
|
||||
SPU_GPR_hdr GPR[128]; //General-Purpose Register
|
||||
Stack<u32> Mbox;
|
||||
SizedStack<u32, 1> OutMbox;
|
||||
SizedStack<u32, 1> OutIntrMbox;
|
||||
SizedStack<u32, 4> InMbox;
|
||||
|
||||
u32 LSA; //local storage address
|
||||
u32 LSA;
|
||||
|
||||
union
|
||||
{
|
||||
|
|
@ -165,11 +127,14 @@ public:
|
|||
{
|
||||
switch(ch)
|
||||
{
|
||||
case SPU_WrOutMbox:
|
||||
return OutMbox.GetFreeCount();
|
||||
|
||||
case SPU_RdInMbox:
|
||||
return 1;
|
||||
return InMbox.GetCount();
|
||||
|
||||
case SPU_WrOutIntrMbox:
|
||||
return 0;
|
||||
return 0;//return OutIntrMbox.GetFreeCount();
|
||||
|
||||
default:
|
||||
ConLog.Error("%s error: unknown/illegal channel (%d).", __FUNCTION__, ch);
|
||||
|
|
@ -181,12 +146,24 @@ public:
|
|||
|
||||
void WriteChannel(u32 ch, const SPU_GPR_hdr& r)
|
||||
{
|
||||
const u32 v = r._u32[0];
|
||||
const u32 v = r._u32[3];
|
||||
|
||||
switch(ch)
|
||||
{
|
||||
case SPU_WrOutIntrMbox:
|
||||
Mbox.Push(v);
|
||||
ConLog.Warning("SPU_WrOutIntrMbox = 0x%x", v);
|
||||
if(!OutIntrMbox.Push(v))
|
||||
{
|
||||
ConLog.Warning("Not enought free rooms.");
|
||||
}
|
||||
break;
|
||||
|
||||
case SPU_WrOutMbox:
|
||||
ConLog.Warning("SPU_WrOutMbox = 0x%x", v);
|
||||
if(!OutMbox.Push(v))
|
||||
{
|
||||
ConLog.Warning("Not enought free rooms.");
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
@ -198,12 +175,12 @@ public:
|
|||
void ReadChannel(SPU_GPR_hdr& r, u32 ch)
|
||||
{
|
||||
r.Reset();
|
||||
u32& v = r._u32[0];
|
||||
u32& v = r._u32[3];
|
||||
|
||||
switch(ch)
|
||||
{
|
||||
case SPU_RdInMbox:
|
||||
v = Mbox.Pop();
|
||||
if(!InMbox.Pop(v)) v = 0;
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
@ -212,17 +189,18 @@ public:
|
|||
}
|
||||
}
|
||||
|
||||
u8 ReadLSA8 () { return Memory.Read8 (LSA + m_offset); }
|
||||
u16 ReadLSA16 () { return Memory.Read16 (LSA + m_offset); }
|
||||
u32 ReadLSA32 () { return Memory.Read32 (LSA + m_offset); }
|
||||
u64 ReadLSA64 () { return Memory.Read64 (LSA + m_offset); }
|
||||
u128 ReadLSA128() { return Memory.Read128(LSA + m_offset); }
|
||||
bool IsGoodLSA(const u32 lsa) const { return Memory.IsGoodAddr(lsa); }
|
||||
u8 ReadLS8 (const u32 lsa) const { return Memory.Read8 (lsa + (m_offset & 0x3fffc)); }
|
||||
u16 ReadLS16 (const u32 lsa) const { return Memory.Read16 (lsa + m_offset); }
|
||||
u32 ReadLS32 (const u32 lsa) const { return Memory.Read32 (lsa + m_offset); }
|
||||
u64 ReadLS64 (const u32 lsa) const { return Memory.Read64 (lsa + m_offset); }
|
||||
u128 ReadLS128(const u32 lsa) const { return Memory.Read128(lsa + m_offset); }
|
||||
|
||||
void WriteLSA8 (const u8& data) { Memory.Write8 (LSA + m_offset, data); }
|
||||
void WriteLSA16 (const u16& data) { Memory.Write16 (LSA + m_offset, data); }
|
||||
void WriteLSA32 (const u32& data) { Memory.Write32 (LSA + m_offset, data); }
|
||||
void WriteLSA64 (const u64& data) { Memory.Write64 (LSA + m_offset, data); }
|
||||
void WriteLSA128(const u128& data) { Memory.Write128(LSA + m_offset, data); }
|
||||
void WriteLS8 (const u32 lsa, const u8& data) const { Memory.Write8 (lsa + m_offset, data); }
|
||||
void WriteLS16 (const u32 lsa, const u16& data) const { Memory.Write16 (lsa + m_offset, data); }
|
||||
void WriteLS32 (const u32 lsa, const u32& data) const { Memory.Write32 (lsa + m_offset, data); }
|
||||
void WriteLS64 (const u32 lsa, const u64& data) const { Memory.Write64 (lsa + m_offset, data); }
|
||||
void WriteLS128(const u32 lsa, const u128& data) const { Memory.Write128(lsa + m_offset, data); }
|
||||
|
||||
public:
|
||||
SPUThread();
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue