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Initial Linux Aarch64 support
* Update asmjit dependency (aarch64 branch) * Disable USE_DISCORD_RPC by default * Dump some JIT objects in rpcs3 cache dir * Add SIGILL handler for all platforms * Fix resetting zeroing denormals in thread pool * Refactor most v128:: utils into global gv_** functions * Refactor PPU interpreter (incomplete), remove "precise" * - Instruction specializations with multiple accuracy flags * - Adjust calling convention for speed * - Removed precise/fast setting, replaced with static * - Started refactoring interpreters for building at runtime JIT * (I got tired of poor compiler optimizations) * - Expose some accuracy settings (SAT, NJ, VNAN, FPCC) * - Add exec_bytes PPU thread variable (akin to cycle count) * PPU LLVM: fix VCTUXS+VCTSXS instruction NaN results * SPU interpreter: remove "precise" for now (extremely non-portable) * - As with PPU, settings changed to static/dynamic for interpreters. * - Precise options will be implemented later * Fix termination after fatal error dialog
This commit is contained in:
Nekotekina
parent
d6aa834b5f
commit
580bd2b25e
89 changed files with 20360 additions and 5612 deletions
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@ -30,7 +30,7 @@
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#include "util/vm.hpp"
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#include "util/asm.hpp"
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#include "util/v128.hpp"
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#include "util/v128sse.hpp"
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#include "util/simd.hpp"
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#include "util/sysinfo.hpp"
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using spu_rdata_t = decltype(spu_thread::rdata);
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@ -87,14 +87,13 @@ void fmt_class_string<spu_type>::format(std::string& out, u64 arg)
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// Verify AVX availability for TSX transactions
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static const bool s_tsx_avx = utils::has_avx();
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// For special case
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static const bool s_tsx_haswell = utils::has_rtm() && !utils::has_mpx();
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// Threshold for when rep mosvb is expected to outperform simd copies
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// The threshold will be 0xFFFFFFFF when the performance of rep movsb is expected to be bad
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static const u32 s_rep_movsb_threshold = utils::get_rep_movsb_threshold();
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#ifndef _MSC_VER
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#if defined(_M_X64)
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extern "C" void __movsb(uchar*, const uchar*, size_t);
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#elif defined(ARCH_X64)
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static FORCE_INLINE void __movsb(unsigned char * Dst, const unsigned char * Src, size_t Size)
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{
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__asm__ __volatile__
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@ -104,8 +103,12 @@ static FORCE_INLINE void __movsb(unsigned char * Dst, const unsigned char * Src,
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"[Dst]" (Dst), "[Src]" (Src), "[Size]" (Size)
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);
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}
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#else
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#define s_rep_movsb_threshold umax
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#define __movsb std::memcpy
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#endif
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#if defined(ARCH_X64)
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static FORCE_INLINE bool cmp_rdata_avx(const __m256i* lhs, const __m256i* rhs)
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{
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#if defined(_MSC_VER) || defined(__AVX__)
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@ -145,18 +148,21 @@ static FORCE_INLINE bool cmp_rdata_avx(const __m256i* lhs, const __m256i* rhs)
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return result;
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#endif
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}
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#endif
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#ifdef _MSC_VER
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__forceinline
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#endif
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extern bool cmp_rdata(const spu_rdata_t& _lhs, const spu_rdata_t& _rhs)
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{
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#if defined(ARCH_X64)
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#ifndef __AVX__
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if (s_tsx_avx) [[likely]]
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#endif
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{
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return cmp_rdata_avx(reinterpret_cast<const __m256i*>(_lhs), reinterpret_cast<const __m256i*>(_rhs));
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}
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#endif
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const auto lhs = reinterpret_cast<const v128*>(_lhs);
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const auto rhs = reinterpret_cast<const v128*>(_rhs);
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@ -165,9 +171,10 @@ extern bool cmp_rdata(const spu_rdata_t& _lhs, const spu_rdata_t& _rhs)
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const v128 c = (lhs[4] ^ rhs[4]) | (lhs[5] ^ rhs[5]);
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const v128 d = (lhs[6] ^ rhs[6]) | (lhs[7] ^ rhs[7]);
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const v128 r = (a | b) | (c | d);
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return r == v128{};
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return gv_testz(r);
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}
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#if defined(ARCH_X64)
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static FORCE_INLINE void mov_rdata_avx(__m256i* dst, const __m256i* src)
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{
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#ifdef _MSC_VER
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@ -199,12 +206,14 @@ static FORCE_INLINE void mov_rdata_avx(__m256i* dst, const __m256i* src)
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);
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#endif
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}
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#endif
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#ifdef _MSC_VER
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__forceinline
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#endif
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extern void mov_rdata(spu_rdata_t& _dst, const spu_rdata_t& _src)
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{
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#if defined(ARCH_X64)
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#ifndef __AVX__
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if (s_tsx_avx) [[likely]]
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#endif
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@ -232,8 +241,12 @@ extern void mov_rdata(spu_rdata_t& _dst, const spu_rdata_t& _src)
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_mm_storeu_si128(reinterpret_cast<__m128i*>(_dst + 80), v1);
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_mm_storeu_si128(reinterpret_cast<__m128i*>(_dst + 96), v2);
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_mm_storeu_si128(reinterpret_cast<__m128i*>(_dst + 112), v3);
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#else
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std::memcpy(_dst, _src, 128);
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#endif
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}
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#if defined(ARCH_X64)
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static FORCE_INLINE void mov_rdata_nt_avx(__m256i* dst, const __m256i* src)
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{
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#ifdef _MSC_VER
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@ -265,9 +278,11 @@ static FORCE_INLINE void mov_rdata_nt_avx(__m256i* dst, const __m256i* src)
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);
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#endif
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}
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#endif
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extern void mov_rdata_nt(spu_rdata_t& _dst, const spu_rdata_t& _src)
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{
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#if defined(ARCH_X64)
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#ifndef __AVX__
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if (s_tsx_avx) [[likely]]
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#endif
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@ -295,6 +310,9 @@ extern void mov_rdata_nt(spu_rdata_t& _dst, const spu_rdata_t& _src)
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_mm_stream_si128(reinterpret_cast<__m128i*>(_dst + 80), v1);
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_mm_stream_si128(reinterpret_cast<__m128i*>(_dst + 96), v2);
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_mm_stream_si128(reinterpret_cast<__m128i*>(_dst + 112), v3);
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#else
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std::memcpy(_dst, _src, 128);
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#endif
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}
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void do_cell_atomic_128_store(u32 addr, const void* to_write);
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@ -421,10 +439,11 @@ std::array<u32, 2> op_branch_targets(u32 pc, spu_opcode_t op)
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return res;
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}
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const auto spu_putllc_tx = built_function<u64(*)(u32 raddr, u64 rtime, void* _old, const void* _new)>("spu_putllc_tx", [](asmjit::x86::Assembler& c, auto& args)
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const auto spu_putllc_tx = built_function<u64(*)(u32 raddr, u64 rtime, void* _old, const void* _new)>("spu_putllc_tx", [](native_asm& c, auto& args)
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{
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using namespace asmjit;
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#if defined(ARCH_X64)
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Label fall = c.newLabel();
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Label fail = c.newLabel();
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Label _ret = c.newLabel();
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@ -677,12 +696,16 @@ const auto spu_putllc_tx = built_function<u64(*)(u32 raddr, u64 rtime, void* _ol
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c.bind(ret2);
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#endif
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c.ret();
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#else
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c.ret(a64::x30);
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#endif
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});
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const auto spu_putlluc_tx = built_function<u64(*)(u32 raddr, const void* rdata, u64* _stx, u64* _ftx)>("spu_putlluc_tx", [](asmjit::x86::Assembler& c, auto& args)
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const auto spu_putlluc_tx = built_function<u64(*)(u32 raddr, const void* rdata, u64* _stx, u64* _ftx)>("spu_putlluc_tx", [](native_asm& c, auto& args)
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{
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using namespace asmjit;
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#if defined(ARCH_X64)
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Label fall = c.newLabel();
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Label _ret = c.newLabel();
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@ -803,12 +826,16 @@ const auto spu_putlluc_tx = built_function<u64(*)(u32 raddr, const void* rdata,
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c.bind(ret2);
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#endif
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c.ret();
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#else
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c.ret(a64::x30);
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#endif
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});
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const auto spu_getllar_tx = built_function<u64(*)(u32 raddr, void* rdata, cpu_thread* _cpu, u64 rtime)>("spu_getllar_tx", [](asmjit::x86::Assembler& c, auto& args)
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const auto spu_getllar_tx = built_function<u64(*)(u32 raddr, void* rdata, cpu_thread* _cpu, u64 rtime)>("spu_getllar_tx", [](native_asm& c, auto& args)
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{
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using namespace asmjit;
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#if defined(ARCH_X64)
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Label fall = c.newLabel();
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Label _ret = c.newLabel();
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@ -938,6 +965,9 @@ const auto spu_getllar_tx = built_function<u64(*)(u32 raddr, void* rdata, cpu_th
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c.bind(ret2);
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#endif
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c.ret();
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#else
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c.ret(a64::x30);
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#endif
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});
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void spu_int_ctrl_t::set(u64 ints)
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@ -967,7 +997,7 @@ spu_imm_table_t::scale_table_t::scale_table_t()
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{
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for (s32 i = -155; i < 174; i++)
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{
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m_data[i + 155].vf = _mm_set1_ps(static_cast<float>(std::exp2(i)));
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m_data[i + 155] = v128::fromf32p(static_cast<float>(std::exp2(i)));
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}
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}
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@ -1385,6 +1415,8 @@ void spu_thread::cpu_task()
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std::fesetround(FE_TOWARDZERO);
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gv_set_zeroing_denormals();
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g_tls_log_prefix = []
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{
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const auto cpu = static_cast<spu_thread*>(get_current_cpu_thread());
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@ -1622,7 +1654,7 @@ spu_thread::spu_thread(lv2_spu_group* group, u32 index, std::string_view name, u
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jit = spu_recompiler_base::make_fast_llvm_recompiler();
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}
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if (g_cfg.core.spu_decoder != spu_decoder_type::fast && g_cfg.core.spu_decoder != spu_decoder_type::precise)
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if (g_cfg.core.spu_decoder == spu_decoder_type::asmjit || g_cfg.core.spu_decoder == spu_decoder_type::llvm)
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{
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if (g_cfg.core.spu_block_size != spu_block_size_type::safe)
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{
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@ -2640,7 +2672,7 @@ bool spu_thread::do_putllc(const spu_mfc_cmd& args)
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return false;
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});
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const u64 count2 = __rdtsc() - perf2.get();
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const u64 count2 = utils::get_tsc() - perf2.get();
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if (count2 > 20000 && g_cfg.core.perf_report) [[unlikely]]
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{
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@ -2672,7 +2704,7 @@ bool spu_thread::do_putllc(const spu_mfc_cmd& args)
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utils::prefetch_read(rdata + 64);
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last_faddr = addr;
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last_ftime = res.load() & -128;
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last_ftsc = __rdtsc();
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last_ftsc = utils::get_tsc();
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return false;
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}
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default:
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@ -2854,7 +2886,7 @@ void do_cell_atomic_128_store(u32 addr, const void* to_write)
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});
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vm::reservation_acquire(addr) += 32;
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result = __rdtsc() - perf0.get();
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result = utils::get_tsc() - perf0.get();
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}
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if (result > 20000 && g_cfg.core.perf_report) [[unlikely]]
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@ -3007,7 +3039,7 @@ bool spu_thread::do_mfc(bool can_escape, bool must_finish)
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{
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// Get commands' execution mask
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// Mask bits are always set when mfc_transfers_shuffling is 0
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return static_cast<u16>((0 - (1u << std::min<u32>(g_cfg.core.mfc_transfers_shuffling, size))) | __rdtsc());
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return static_cast<u16>((0 - (1u << std::min<u32>(g_cfg.core.mfc_transfers_shuffling, size))) | utils::get_tsc());
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};
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// Process enqueued commands
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@ -3684,9 +3716,9 @@ void spu_thread::set_interrupt_status(bool enable)
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// Detect enabling interrupts with events masked
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if (auto mask = ch_events.load().mask; mask & SPU_EVENT_INTR_BUSY_CHECK)
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{
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if (g_cfg.core.spu_decoder != spu_decoder_type::precise && g_cfg.core.spu_decoder != spu_decoder_type::fast)
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if (g_cfg.core.spu_decoder != spu_decoder_type::_static)
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{
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fmt::throw_exception("SPU Interrupts not implemented (mask=0x%x): Use interpreterts", mask);
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fmt::throw_exception("SPU Interrupts not implemented (mask=0x%x): Use static interpreter", mask);
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}
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spu_log.trace("SPU Interrupts (mask=0x%x) are using CPU busy checking mode", mask);
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