mirror of
https://github.com/RPCS3/rpcs3.git
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- Improved sc function binder.
- Improved GLGSRender.
This commit is contained in:
DH
parent
3bb7a299ca
commit
5753edf6ef
133 changed files with 13624 additions and 3898 deletions
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@ -1,5 +1,7 @@
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#pragma once
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#include "Emu/Cell/PPCThread.h"
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#include "Emu/SysCalls/SysCalls.h"
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#include "rpcs3.h"
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enum
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{
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@ -215,14 +217,14 @@ union CRhdr
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struct
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{
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u8 cr0 : 4;
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u8 cr1 : 4;
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u8 cr2 : 4;
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u8 cr3 : 4;
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u8 cr4 : 4;
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u8 cr5 : 4;
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u8 cr6 : 4;
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u8 cr7 : 4;
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u8 cr6 : 4;
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u8 cr5 : 4;
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u8 cr4 : 4;
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u8 cr3 : 4;
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u8 cr2 : 4;
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u8 cr1 : 4;
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u8 cr0 : 4;
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};
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};
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@ -239,6 +241,49 @@ union XERhdr
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};
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};
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union VSCRhdr
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{
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u32 VSCR;
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struct
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{
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/*
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Saturation. A sticky status bit indicating that some field in a saturating instruction saturated since the last
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time SAT was cleared. In other words when SAT = ‘1’ it remains set to ‘1’ until it is cleared to ‘0’ by an
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mtvscr instruction.
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1 The vector saturate instruction implicitly sets when saturation has occurred on the results one of
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the vector instructions having saturate in its name:
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Move To VSCR (mtvscr)
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Vector Add Integer with Saturation (vaddubs, vadduhs, vadduws, vaddsbs, vaddshs,
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vaddsws)
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Vector Subtract Integer with Saturation (vsububs, vsubuhs, vsubuws, vsubsbs, vsubshs,
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vsubsws)
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Vector Multiply-Add Integer with Saturation (vmhaddshs, vmhraddshs)
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Vector Multiply-Sum with Saturation (vmsumuhs, vmsumshs, vsumsws)
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Vector Sum-Across with Saturation (vsumsws, vsum2sws, vsum4sbs, vsum4shs,
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vsum4ubs)
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Vector Pack with Saturation (vpkuhus, vpkuwus, vpkshus, vpkswus, vpkshss, vpkswss)
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Vector Convert to Fixed-Point with Saturation (vctuxs, vctsxs)
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0 Indicates no saturation occurred; mtvscr can explicitly clear this bit.
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*/
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u32 SAT : 1;
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u32 X : 15;
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/*
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Non-Java. A mode control bit that determines whether vector floating-point operations will be performed
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in a Java-IEEE-C9X–compliant mode or a possibly faster non-Java/non-IEEE mode.
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0 The Java-IEEE-C9X–compliant mode is selected. Denormalized values are handled as specified
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by Java, IEEE, and C9X standard.
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1 The non-Java/non-IEEE–compliant mode is selected. If an element in a source vector register
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contains a denormalized value, the value ‘0’ is used instead. If an instruction causes an underflow
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exception, the corresponding element in the target VR is cleared to ‘0’. In both cases, the ‘0’
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has the same sign as the denormalized or underflowing value.
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*/
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u32 NJ : 1;
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u32 Y : 15;
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};
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};
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enum FPRType
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{
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FPR_NORM,
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@ -280,35 +325,53 @@ struct PPCdouble
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};
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FPRType type;
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operator double&() { return _double; }
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operator const double&() const { return _double; }
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u32 GetType()
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PPCdouble& operator = (const PPCdouble& r)
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{
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if(exp > 0 && exp < 0x7ff) return sign ? FPR_NN : FPR_PN;
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if(frac)
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{
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if(exp) return FPR_QNAN;
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return sign ? FPR_INF : FPR_PINF;
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}
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return sign ? FPR_NZ : FPR_PZ;
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_u64 = r._u64;
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type = UpdateType();
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return *this;
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}
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u32 To32()
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FPRType UpdateType() const
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{
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if (exp > 896 || (!frac && !exp))
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const int fpc = _fpclass(_double);
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switch(fpc)
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{
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return ((_u64 >> 32) & 0xc0000000) | ((_u64 >> 29) & 0x3fffffff);
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case _FPCLASS_SNAN: return FPR_SNAN;
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case _FPCLASS_QNAN: return FPR_QNAN;
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case _FPCLASS_NINF: return FPR_NINF;
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case _FPCLASS_NN: return FPR_NN;
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case _FPCLASS_ND: return FPR_ND;
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case _FPCLASS_NZ: return FPR_NZ;
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case _FPCLASS_PZ: return FPR_PZ;
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case _FPCLASS_PD: return FPR_PD;
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case _FPCLASS_PN: return FPR_PN;
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case _FPCLASS_PINF: return FPR_PINF;
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}
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if (exp >= 874)
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{
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return ((0x80000000 | (frac >> 21)) >> (905 - exp)) | (_u64 >> 32) & 0x80000000;
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}
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throw wxString::Format("PPCdouble::UpdateType() -> unknown fpclass (0x%04x).", fpc);
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}
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//?
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return ((_u64 >> 32) & 0xc0000000) | ((_u64 >> 29) & 0x3fffffff);
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FPRType GetType() const
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{
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return type;
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}
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u32 To32() const
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{
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float res = _double;
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return (u32&)res;
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}
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u64 To64() const
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{
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return (u64&)_double;
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}
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u32 GetZerosCount()
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@ -369,370 +432,76 @@ struct PPCdouble
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struct FPRdouble
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{
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static PPCdouble ConvertToIntegerMode(const PPCdouble& d, FPSCRhdr& fpscr, bool is_64, u32 round_mode)
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{
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PPCdouble ret;
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if(d.exp == 2047)
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{
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if (d.frac == 0)
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{
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ret.type = FPR_INF;
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fpscr.FI = 0;
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fpscr.FR = 0;
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fpscr.VXCVI = 1;
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if(fpscr.VE == 0)
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{
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if(is_64)
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{
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return d.sign ? 0x8000000000000000 : 0x7FFFFFFFFFFFFFFF;
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}
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else
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{
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return d.sign ? 0x80000000 : 0x7FFFFFFF;
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}
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fpscr.FPRF = 0;
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}
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}
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else if(d.nan == 0)
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{
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ret.type = FPR_SNAN;
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fpscr.FI = 0;
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fpscr.FR = 0;
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fpscr.VXCVI = 1;
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fpscr.VXSNAN = 1;
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if(fpscr.VE == 0)
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{
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return is_64 ? 0x8000000000000000 : 0x80000000;
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fpscr.FPRF = 0;
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}
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}
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else
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{
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ret.type = FPR_QNAN;
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fpscr.FI = 0;
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fpscr.FR = 0;
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fpscr.VXCVI = 1;
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if(fpscr.VE == 0)
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{
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return is_64 ? 0x8000000000000000 : 0x80000000;
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fpscr.FPRF = 0;
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}
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}
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}
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else if(d.exp > 1054)
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{
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fpscr.FI = 0;
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fpscr.FR = 0;
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fpscr.VXCVI = 1;
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if(fpscr.VE == 0)
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{
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if(is_64)
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{
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return d.sign ? 0x8000000000000000 : 0x7FFFFFFFFFFFFFFF;
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}
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else
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{
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return d.sign ? 0x80000000 : 0x7FFFFFFF;
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}
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fpscr.FPRF = 0;
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}
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}
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ret.sign = d.sign;
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if(d.exp > 0)
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{
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ret.exp = d.exp - 1023;
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ret.frac = 1 | d.frac;
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}
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else if(d.exp == 0)
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{
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ret.exp = -1022;
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ret.frac = d.frac;
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}
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/*
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if(d.exp == 0)
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{
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if (d.frac == 0)
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{
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d.type = FPR_ZERO;
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}
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else
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{
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const u32 z = d.GetZerosCount() - 8;
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d.frac <<= z + 3;
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d.exp -= 1023 - 1 + z;
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d.type = FPR_NORM;
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}
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}
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else
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{
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d.exp -= 1023;
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d.type = FPR_NORM;
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d.nan = 1;
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d.frac <<= 3;
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}
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*/
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return ret;
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}
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static u32 ConvertToFloatMode(PPCdouble& d, u32 RN)
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{
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/*
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u32 fpscr = 0;
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switch (d.type)
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{
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case FPR_NORM:
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d.exp += 1023;
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if (d.exp > 0)
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{
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fpscr |= Round(d, RN);
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if(d.nan)
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{
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d.exp++;
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d.frac >>= 4;
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}
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else
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{
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d.frac >>= 3;
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}
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if(d.exp >= 2047)
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{
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d.exp = 2047;
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d.frac = 0;
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fpscr |= FPSCR_OX;
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}
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}
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else
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{
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d.exp = -(s64)d.exp + 1;
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if(d.exp <= 56)
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{
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d.frac >>= d.exp;
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fpscr |= Round(d, RN);
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d.frac <<= 1;
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if(d.nan)
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{
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d.exp = 1;
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d.frac = 0;
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}
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else
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{
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d.exp = 0;
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d.frac >>= 4;
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fpscr |= FPSCR_UX;
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}
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}
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else
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{
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d.exp = 0;
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d.frac = 0;
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fpscr |= FPSCR_UX;
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}
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}
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break;
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case FPR_ZERO:
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d.exp = 0;
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d.frac = 0;
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break;
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case FPR_NAN:
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d.exp = 2047;
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d.frac = 1;
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break;
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case FPR_INF:
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d.exp = 2047;
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d.frac = 0;
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break;
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}
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return fpscr;
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*/
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return 0;
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}
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static u32 Round(PPCdouble& d, u32 RN)
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{
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switch(RN)
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{
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case FPSCR_RN_NEAR:
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if(d.frac & 0x7)
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{
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if((d.frac & 0x7) != 4 || d.frac & 0x8)
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{
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d.frac += 4;
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}
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return FPSCR_XX;
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}
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return 0;
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case FPSCR_RN_ZERO:
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if(d.frac & 0x7) return FPSCR_XX;
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return 0;
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case FPSCR_RN_PINF:
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if(!d.sign && (d.frac & 0x7))
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{
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d.frac += 8;
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return FPSCR_XX;
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}
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return 0;
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case FPSCR_RN_MINF:
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if(d.sign && (d.frac & 0x7))
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{
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d.frac += 8;
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return FPSCR_XX;
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}
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return 0;
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}
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return 0;
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}
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static const u64 double_sign = 0x8000000000000000ULL;
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static const u64 double_frac = 0x000FFFFFFFFFFFFFULL;
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static bool IsINF(double d);
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static bool IsNaN(double d);
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static bool IsQNaN(double d);
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static bool IsSNaN(double d);
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static int Cmp(double a, double b);
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static bool IsINF(PPCdouble d);
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static bool IsNaN(PPCdouble d);
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static bool IsQNaN(PPCdouble d);
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static bool IsSNaN(PPCdouble d);
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static int Cmp(PPCdouble a, PPCdouble b);
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};
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union VPR_reg
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{
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//__m128i _m128i;
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u128 _u128;
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s128 _i128;
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s128 _s128;
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u64 _u64[2];
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s64 _i64[2];
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s64 _s64[2];
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u32 _u32[4];
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s32 _i32[4];
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s32 _s32[4];
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u16 _u16[8];
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s16 _i16[8];
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s16 _s16[8];
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u8 _u8[16];
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s8 _i8[16];
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//struct { float x, y, z, w; };
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s8 _s8[16];
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float _f[4];
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double _d[2];
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VPR_reg() { Clear(); }
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VPR_reg(const __m128i val){_u128._u64[0] = val.m128i_u64[0]; _u128._u64[1] = val.m128i_u64[1];}
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VPR_reg(const u128 val) { _u128 = val; }
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VPR_reg(const u64 val) { Clear(); _u64[0] = val; }
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VPR_reg(const u32 val) { Clear(); _u32[0] = val; }
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VPR_reg(const u16 val) { Clear(); _u16[0] = val; }
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VPR_reg(const u8 val) { Clear(); _u8[0] = val; }
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VPR_reg(const s128 val) { _i128 = val; }
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VPR_reg(const s64 val) { Clear(); _i64[0] = val; }
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VPR_reg(const s32 val) { Clear(); _i32[0] = val; }
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VPR_reg(const s16 val) { Clear(); _i16[0] = val; }
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VPR_reg(const s8 val) { Clear(); _i8[0] = val; }
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operator u128() const { return _u128; }
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operator s128() const { return _i128; }
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operator u64() const { return _u64[0]; }
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operator s64() const { return _i64[0]; }
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operator u32() const { return _u32[0]; }
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operator s32() const { return _i32[0]; }
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operator u16() const { return _u16[0]; }
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operator s16() const { return _i16[0]; }
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operator u8() const { return _u8[0]; }
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operator s8() const { return _i8[0]; }
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operator __m128i() { __m128i ret; ret.m128i_u64[0]=_u128._u64[0]; ret.m128i_u64[1]=_u128._u64[1]; return ret; }
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operator bool() const { return _u64[0] != 0 || _u64[1] != 0; }
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wxString ToString() const
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wxString ToString(bool hex=false) const
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{
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return wxString::Format("%08x%08x%08x%08x", _u32[3], _u32[2], _u32[1], _u32[0]);
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if(hex) return wxString::Format("%08x%08x%08x%08x", _u32[3], _u32[2], _u32[1], _u32[0]);
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return wxString::Format("x: %g y: %g z: %g w: %g", _f[3], _f[2], _f[1], _f[0]);
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}
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VPR_reg operator ^ (VPR_reg right) { return _mm_xor_si128(*this, right); }
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VPR_reg operator | (VPR_reg right) { return _mm_or_si128 (*this, right); }
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VPR_reg operator & (VPR_reg right) { return _mm_and_si128(*this, right); }
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u8 GetBit(u8 bit)
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{
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if(bit < 64) return (_u64[0] >> bit) & 0x1;
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VPR_reg operator ^ (__m128i right) { return _mm_xor_si128(*this, right); }
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VPR_reg operator | (__m128i right) { return _mm_or_si128 (*this, right); }
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VPR_reg operator & (__m128i right) { return _mm_and_si128(*this, right); }
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return (_u64[1] >> (bit - 64)) & 0x1;
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}
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bool operator == (const VPR_reg& right){ return _u64[0] == right._u64[0] && _u64[1] == right._u64[1]; }
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void SetBit(u8 bit, u8 value)
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{
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if(bit < 64)
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{
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_u64[0] &= ~(1 << bit);
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_u64[0] |= (value & 0x1) << bit;
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bool operator == (const u128 right) { return _u64[0] == right._u64[0] && _u64[1] == right._u64[1]; }
|
||||
bool operator == (const s128 right) { return _i64[0] == right._i64[0] && _i64[1] == right._i64[1]; }
|
||||
bool operator == (const u64 right) { return _u64[0] == (u64)right && _u64[1] == 0; }
|
||||
bool operator == (const s64 right) { return _i64[0] == (s64)right && _i64[1] == 0; }
|
||||
bool operator == (const u32 right) { return _u64[0] == (u64)right && _u64[1] == 0; }
|
||||
bool operator == (const s32 right) { return _i64[0] == (s64)right && _i64[1] == 0; }
|
||||
bool operator == (const u16 right) { return _u64[0] == (u64)right && _u64[1] == 0; }
|
||||
bool operator == (const s16 right) { return _i64[0] == (s64)right && _i64[1] == 0; }
|
||||
bool operator == (const u8 right) { return _u64[0] == (u64)right && _u64[1] == 0; }
|
||||
bool operator == (const s8 right) { return _i64[0] == (s64)right && _i64[1] == 0; }
|
||||
return;
|
||||
}
|
||||
|
||||
bool operator != (const VPR_reg& right){ return !(*this == right); }
|
||||
bool operator != (const u128 right) { return !(*this == right); }
|
||||
bool operator != (const u64 right) { return !(*this == right); }
|
||||
bool operator != (const u32 right) { return !(*this == right); }
|
||||
bool operator != (const u16 right) { return !(*this == right); }
|
||||
bool operator != (const u8 right) { return !(*this == right); }
|
||||
bool operator != (const s128 right) { return !(*this == right); }
|
||||
bool operator != (const s64 right) { return !(*this == right); }
|
||||
bool operator != (const s32 right) { return !(*this == right); }
|
||||
bool operator != (const s16 right) { return !(*this == right); }
|
||||
bool operator != (const s8 right) { return !(*this == right); }
|
||||
bit -= 64;
|
||||
|
||||
s64& d(const u32 c) { return _i64[1 - c]; }
|
||||
u64& ud(const u32 c) { return _u64[1 - c]; }
|
||||
|
||||
s32& w(const u32 c) { return _i32[3 - c]; }
|
||||
u32& uw(const u32 c) { return _u32[3 - c]; }
|
||||
|
||||
s16& h(const u32 c) { return _i16[7 - c]; }
|
||||
u16& uh(const u32 c) { return _u16[7 - c]; }
|
||||
|
||||
s8& b(const u32 c) { return _i8[15 - c]; }
|
||||
u8& ub(const u32 c) { return _u8[15 - c]; }
|
||||
_u64[1] &= ~(1 << bit);
|
||||
_u64[1] |= (value & 0x1) << bit;
|
||||
}
|
||||
|
||||
void Clear() { memset(this, 0, sizeof(*this)); }
|
||||
};
|
||||
|
||||
/*
|
||||
struct VPR_table
|
||||
{
|
||||
VPR_reg t[32];
|
||||
|
||||
operator VPR_reg*() { return t; }
|
||||
|
||||
VPR_reg& operator [] (int index)
|
||||
{
|
||||
return t[index];
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
static const s32 MAX_INT_VALUE = 0x7fffffff;
|
||||
|
||||
class PPUThread : public PPCThread
|
||||
class PPUThread
|
||||
: public PPCThread
|
||||
, public SysCalls
|
||||
{
|
||||
public:
|
||||
double FPR[32]; //Floating Point Register
|
||||
PPCdouble FPR[32]; //Floating Point Register
|
||||
FPSCRhdr FPSCR; //Floating Point Status and Control Register
|
||||
u64 GPR[32]; //General-Purpose Register
|
||||
VPR_reg VPR[32];
|
||||
|
|
@ -786,12 +555,16 @@ public:
|
|||
MSRhdr MSR; //Machine State Register
|
||||
PVRhdr PVR; //Processor Version Register
|
||||
|
||||
VSCRhdr VSCR; // Vector Status and Control Register
|
||||
|
||||
u64 LR; //SPR 0x008 : Link Register
|
||||
u64 CTR; //SPR 0x009 : Count Register
|
||||
|
||||
s32 USPRG; //SPR 0x100 : User-SPR General-Purpose Registers
|
||||
|
||||
s32 SPRG[8]; //SPR 0x100 - 0x107 : SPR General-Purpose Registers
|
||||
union
|
||||
{
|
||||
u64 USPRG0; //SPR 0x100 : User-SPR General-Purpose Register 0
|
||||
u64 SPRG[8]; //SPR 0x100 - 0x107 : SPR General-Purpose Registers
|
||||
};
|
||||
|
||||
//TBR : Time-Base Registers
|
||||
union
|
||||
|
|
@ -818,14 +591,14 @@ public:
|
|||
{
|
||||
switch(n)
|
||||
{
|
||||
case 7: return CR.cr0;
|
||||
case 6: return CR.cr1;
|
||||
case 5: return CR.cr2;
|
||||
case 4: return CR.cr3;
|
||||
case 3: return CR.cr4;
|
||||
case 2: return CR.cr5;
|
||||
case 1: return CR.cr6;
|
||||
case 0: return CR.cr7;
|
||||
case 0: return CR.cr0;
|
||||
case 1: return CR.cr1;
|
||||
case 2: return CR.cr2;
|
||||
case 3: return CR.cr3;
|
||||
case 4: return CR.cr4;
|
||||
case 5: return CR.cr5;
|
||||
case 6: return CR.cr6;
|
||||
case 7: return CR.cr7;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -835,14 +608,14 @@ public:
|
|||
{
|
||||
switch(n)
|
||||
{
|
||||
case 7: CR.cr0 = value; break;
|
||||
case 6: CR.cr1 = value; break;
|
||||
case 5: CR.cr2 = value; break;
|
||||
case 4: CR.cr3 = value; break;
|
||||
case 3: CR.cr4 = value; break;
|
||||
case 2: CR.cr5 = value; break;
|
||||
case 1: CR.cr6 = value; break;
|
||||
case 0: CR.cr7 = value; break;
|
||||
case 0: CR.cr0 = value; break;
|
||||
case 1: CR.cr1 = value; break;
|
||||
case 2: CR.cr2 = value; break;
|
||||
case 3: CR.cr3 = value; break;
|
||||
case 4: CR.cr4 = value; break;
|
||||
case 5: CR.cr5 = value; break;
|
||||
case 6: CR.cr6 = value; break;
|
||||
case 7: CR.cr7 = value; break;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -850,14 +623,14 @@ public:
|
|||
{
|
||||
switch(n)
|
||||
{
|
||||
case 7: value ? CR.cr0 |= bit : CR.cr0 &= ~bit; break;
|
||||
case 6: value ? CR.cr1 |= bit : CR.cr1 &= ~bit; break;
|
||||
case 5: value ? CR.cr2 |= bit : CR.cr2 &= ~bit; break;
|
||||
case 4: value ? CR.cr3 |= bit : CR.cr3 &= ~bit; break;
|
||||
case 3: value ? CR.cr4 |= bit : CR.cr4 &= ~bit; break;
|
||||
case 2: value ? CR.cr5 |= bit : CR.cr5 &= ~bit; break;
|
||||
case 1: value ? CR.cr6 |= bit : CR.cr6 &= ~bit; break;
|
||||
case 0: value ? CR.cr7 |= bit : CR.cr7 &= ~bit; break;
|
||||
case 0: value ? CR.cr0 |= bit : CR.cr0 &= ~bit; break;
|
||||
case 1: value ? CR.cr1 |= bit : CR.cr1 &= ~bit; break;
|
||||
case 2: value ? CR.cr2 |= bit : CR.cr2 &= ~bit; break;
|
||||
case 3: value ? CR.cr3 |= bit : CR.cr3 &= ~bit; break;
|
||||
case 4: value ? CR.cr4 |= bit : CR.cr4 &= ~bit; break;
|
||||
case 5: value ? CR.cr5 |= bit : CR.cr5 &= ~bit; break;
|
||||
case 6: value ? CR.cr6 |= bit : CR.cr6 &= ~bit; break;
|
||||
case 7: value ? CR.cr7 |= bit : CR.cr7 &= ~bit; break;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -916,17 +689,31 @@ public:
|
|||
virtual wxString RegsToString()
|
||||
{
|
||||
wxString ret = PPCThread::RegsToString();
|
||||
|
||||
for(uint i=0; i<32; ++i) ret += wxString::Format("GPR[%d] = 0x%llx\n", i, GPR[i]);
|
||||
for(uint i=0; i<32; ++i) ret += wxString::Format("FPR[%d] = %.6G\n", i, FPR[i]);
|
||||
for(uint i=0; i<32; ++i) ret += wxString::Format("VPR[%d] = 0x%s [%s]\n", i, VPR[i].ToString(true), VPR[i].ToString());
|
||||
ret += wxString::Format("CR = 0x%08x\n", CR);
|
||||
ret += wxString::Format("LR = 0x%llx\n", LR);
|
||||
ret += wxString::Format("CTR = 0x%llx\n", CTR);
|
||||
ret += wxString::Format("XER = 0x%llx\n", XER);
|
||||
ret += wxString::Format("FPSCR = 0x%x\n", FPSCR);
|
||||
ret += wxString::Format("XER = 0x%llx [CA=%lld | OV=%lld | SO=%lld]\n", XER, XER.CA, XER.OV, XER.SO);
|
||||
ret += wxString::Format("FPSCR = 0x%x "
|
||||
"[RN=%d | NI=%d | XE=%d | ZE=%d | UE=%d | OE=%d | VE=%d | "
|
||||
"VXCVI=%d | VXSQRT=%d | VXSOFT=%d | FPRF=%d | "
|
||||
"FI=%d | FR=%d | VXVC=%d | VXIMZ=%d | "
|
||||
"VXZDZ=%d | VXIDI=%d | VXISI=%d | VXSNAN=%d | "
|
||||
"XX=%d | ZX=%d | UX=%d | OX=%d | VX=%d | FEX=%d | FX=%d]\n",
|
||||
FPSCR,
|
||||
FPSCR.RN,
|
||||
FPSCR.NI, FPSCR.XE, FPSCR.ZE, FPSCR.UE, FPSCR.OE, FPSCR.VE,
|
||||
FPSCR.VXCVI, FPSCR.VXSQRT, FPSCR.VXSOFT, FPSCR.FPRF,
|
||||
FPSCR.FI, FPSCR.FR, FPSCR.VXVC, FPSCR.VXIMZ,
|
||||
FPSCR.VXZDZ, FPSCR.VXIDI, FPSCR.VXISI, FPSCR.VXSNAN,
|
||||
FPSCR.XX, FPSCR.ZX, FPSCR.UX, FPSCR.OX, FPSCR.VX, FPSCR.FEX, FPSCR.FX);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void SetBranch(const u64 pc);
|
||||
virtual void AddArgv(const wxString& arg);
|
||||
|
||||
public:
|
||||
|
|
@ -940,6 +727,8 @@ protected:
|
|||
virtual void DoResume();
|
||||
virtual void DoStop();
|
||||
|
||||
private:
|
||||
public:
|
||||
virtual void DoCode(const s32 code);
|
||||
};
|
||||
};
|
||||
|
||||
PPUThread& GetCurrentPPUThread();
|
||||
Loading…
Add table
Add a link
Reference in a new issue