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rsx: Optimizations for program management
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parent
a52ea7f870
commit
440a31ef18
5 changed files with 81 additions and 39 deletions
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@ -357,9 +357,21 @@ namespace rsx
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static void impl(thread* rsx, u32 _reg, u32 arg)
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{
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method_registers.commit_4_transform_program_instructions(index);
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rsx->m_vertex_program_dirty = true;
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}
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};
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void set_transform_program_start(thread* rsx, u32, u32)
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{
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rsx->m_vertex_program_dirty = true;
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}
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void set_vertex_attribute_output_mask(thread* rsx, u32, u32)
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{
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rsx->m_vertex_program_dirty = true;
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rsx->m_fragment_program_dirty = true;
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}
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void set_begin_end(thread* rsxthr, u32 _reg, u32 arg)
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{
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if (arg)
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@ -521,6 +533,11 @@ namespace rsx
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rsx->sync();
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}
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void invalidate_L2(thread* rsx, u32, u32)
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{
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rsx->m_fragment_program_dirty = true;
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}
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void set_surface_dirty_bit(thread* rsx, u32, u32)
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{
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rsx->m_rtts_dirty = true;
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@ -539,6 +556,7 @@ namespace rsx
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static void impl(thread* rsx, u32 _reg, u32 arg)
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{
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rsx->m_textures_dirty[index] = true;
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rsx->m_fragment_program_dirty = true;
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}
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};
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@ -565,6 +583,8 @@ namespace rsx
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const u32 pixel_offset = (method_registers.blit_engine_output_pitch_nv3062() * y) + (x << 2);
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u32 address = get_address(method_registers.blit_engine_output_offset_nv3062() + pixel_offset + index * 4, method_registers.blit_engine_output_location_nv3062());
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vm::write32(address, arg);
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rsx->m_fragment_program_dirty = true;
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}
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};
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}
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@ -1711,6 +1731,9 @@ namespace rsx
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bind<NV4097_WAIT_FOR_IDLE, nv4097::sync>();
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bind<NV4097_ZCULL_SYNC, nv4097::sync>();
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bind<NV4097_SET_CONTEXT_DMA_REPORT, nv4097::sync>();
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bind<NV4097_INVALIDATE_L2, nv4097::invalidate_L2>();
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bind<NV4097_SET_TRANSFORM_PROGRAM_START, nv4097::set_transform_program_start>();
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bind<NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK, nv4097::set_vertex_attribute_output_mask>();
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//NV308A
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bind_range<NV308A_COLOR, 1, 256, nv308a::color>();
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