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Fixup after #6143 (#6146)

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vm::spu max address was overflowing resulting in issues, so cast to u64 where needed. Fixes #6145.
    Use vm::get_addr instead of manually substructing vm::base(0) from pointer in texture cache code.
    Prefer std::atomic_thread_fence over _mm_?fence(), adjust usage to be more correct.
    Used sequantially consistent ordering in semaphore_release for TSX path as well.
    Improved memory ordering for sys_rsx_context_iounmap/map.
    Fixed sync bugs in HLE gcm because of not using atomic instructions.
    Use release memory barrier in lwsync for PPU LLVM, according to this xbox360 programming guide lwsync is a hw release memory barrier.
    Also use release barrier where lwsync was originally used in liblv2 sys_lwmutex and cellSync.
    Use acquire barrier for isync instruction, see https://devblogs.microsoft.com/oldnewthing/20180814-00/?p=99485
This commit is contained in:
Eladash 2019-06-29 18:48:42 +03:00 • committed by Ivan
parent 1ee7b91646
commit 43f919c04b
20 changed files with 85 additions and 65 deletions
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7
rpcs3/Emu/Cell/PPUInterpreter.cpp
View file

@ -8,6 +8,7 @@
#include "Emu/Cell/Common.h"
#include <cmath>
#include <atomic>
#if !defined(_MSC_VER) && !defined(__SSSE3__)
#define _mm_shuffle_epi8(opa, opb) opb
@ -2966,7 +2967,7 @@ bool ppu_interpreter::CRANDC(ppu_thread& ppu, ppu_opcode_t op)
bool ppu_interpreter::ISYNC(ppu_thread& ppu, ppu_opcode_t op)
{
_mm_mfence();
std::atomic_thread_fence(std::memory_order_acquire);
return true;
}
@ -4046,7 +4047,7 @@ bool ppu_interpreter::LFSUX(ppu_thread& ppu, ppu_opcode_t op)
bool ppu_interpreter::SYNC(ppu_thread& ppu, ppu_opcode_t op)
{
_mm_mfence();
std::atomic_thread_fence(std::memory_order_seq_cst);
return true;
}
@ -4280,7 +4281,7 @@ bool ppu_interpreter::SRADI(ppu_thread& ppu, ppu_opcode_t op)
bool ppu_interpreter::EIEIO(ppu_thread& ppu, ppu_opcode_t op)
{
_mm_mfence();
std::atomic_thread_fence(std::memory_order_seq_cst);
return true;
}