archive/rpcs3
1
0
Fork 0
mirror of https://github.com/RPCS3/rpcs3.git synced 2025-07-06 23:11:25 +12:00
Code Issues Projects Releases Packages Wiki Activity Actions

PPU/SPU transactions: ease cache line interference (TSX path)

Browse source 
Touch memory on the same memory page, but different cache lines.
This commit is contained in:
Nekotekina 2019-04-02 13:12:05 +03:00
parent 12dc3c1872
commit 3354f068fc
2 changed files with 20 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

8
rpcs3/Emu/Cell/PPUThread.cpp
View file

@ -1054,8 +1054,12 @@ const auto ppu_stwcx_tx = build_function_asm<bool(*)(u32 raddr, u64 rtime, u64 r
c.jz(fail);
c.sar(x86::eax, 24);
c.js(fail);
c.xor_(x86::r11, 0xf80);
c.xor_(x86::r10, 0xf80);
c.lock().add(x86::dword_ptr(x86::r11), 0);
c.lock().add(x86::qword_ptr(x86::r10), 0);
c.xor_(x86::r11, 0xf80);
c.xor_(x86::r10, 0xf80);
c.jmp(begin);
c.bind(fail);
@ -1148,8 +1152,12 @@ const auto ppu_stdcx_tx = build_function_asm<bool(*)(u32 raddr, u64 rtime, u64 r
c.jz(fail);
c.sar(x86::eax, 24);
c.js(fail);
c.xor_(x86::r11, 0xf80);
c.xor_(x86::r10, 0xf80);
c.lock().add(x86::qword_ptr(x86::r11), 0);
c.lock().add(x86::qword_ptr(x86::r10), 0);
c.xor_(x86::r11, 0xf80);
c.xor_(x86::r10, 0xf80);
c.jmp(begin);
c.bind(fail);