archive/rpcs3
1
0
Fork 0
mirror of https://github.com/RPCS3/rpcs3.git synced 2025-07-05 06:21:26 +12:00
Code Issues Projects Releases Packages Wiki Activity Actions

Some warnings fixed, some code removed

Browse source
This commit is contained in:
Nekotekina 2014-08-30 21:51:00 +04:00
parent 8dfe7138df
commit 3269c88d02
21 changed files with 166 additions and 400 deletions
Download patch file Download diff file Expand all files Collapse all files

2
asmjit

@ -1 +1 @@
Subproject commit 3363e4138b003be36dfb63cf8c63cf360f04276f Subproject commit d7fc62d9e905859579f5965eee6f7f99b65c2246

4
rpcs3/Emu/ARMv7/ARMv7Decoder.h
View file

@ -21,8 +21,8 @@ public:
virtual u8 DecodeMemory(const u64 address) virtual u8 DecodeMemory(const u64 address)
{ {
using namespace ARMv7_opcodes; using namespace ARMv7_opcodes;
const u16 code0 = Memory.PSV.Read16(address); const u16 code0 = Memory.PSV.Read16((u32)address);
const u16 code1 = Memory.PSV.Read16(address + 2); const u16 code1 = Memory.PSV.Read16((u32)address + 2);
switch(code0 >> 12) //15 - 12 switch(code0 >> 12) //15 - 12
{ {

2
rpcs3/Emu/ARMv7/ARMv7DisAsm.h
View file

@ -22,7 +22,7 @@ public:
protected: protected:
virtual u32 DisAsmBranchTarget(const s32 imm) virtual u32 DisAsmBranchTarget(const s32 imm)
{ {
return dump_pc + imm; return (u32)dump_pc + imm;
} }
std::string GetRegsListString(u16 regs_list) std::string GetRegsListString(u16 regs_list)

2
rpcs3/Emu/ARMv7/ARMv7Interpreter.h
View file

@ -310,7 +310,7 @@ protected:
void BL(u32 imm, u8 intstr_size) void BL(u32 imm, u8 intstr_size)
{ {
CPU.LR = (CPU.PC + intstr_size) | 1; CPU.LR = ((u32)CPU.PC + intstr_size) | 1;
CPU.SetBranch(CPU.PC + intstr_size + imm); CPU.SetBranch(CPU.PC + intstr_size + imm);
} }

2
rpcs3/Emu/ARMv7/ARMv7Thread.cpp
View file

@ -18,7 +18,7 @@ void ARMv7Thread::InitRegs()
memset(GPR, 0, sizeof(GPR[0]) * 15); memset(GPR, 0, sizeof(GPR[0]) * 15);
APSR.APSR = 0; APSR.APSR = 0;
IPSR.IPSR = 0; IPSR.IPSR = 0;
SP = m_stack_point; SP = (u32)m_stack_point;
} }
void ARMv7Thread::InitStack() void ARMv7Thread::InitStack()

6
rpcs3/Emu/ARMv7/ARMv7Thread.h
View file

@ -51,7 +51,7 @@ public:
u32 IPSR; u32 IPSR;
} IPSR; } IPSR;
void write_gpr(u8 n, u32 value) void write_gpr(u32 n, u32 value)
{ {
assert(n < 16); assert(n < 16);
@ -65,7 +65,7 @@ public:
} }
} }
u32 read_gpr(u8 n) u32 read_gpr(u32 n)
{ {
assert(n < 16); assert(n < 16);
@ -74,7 +74,7 @@ public:
return GPR[n]; return GPR[n];
} }
return PC; return (u32)PC;
} }
public: public:

2
rpcs3/Emu/CPU/CPUThread.cpp
View file

@ -287,7 +287,7 @@ void _se_translator(unsigned int u, EXCEPTION_POINTERS* pExp)
{ {
// TODO: allow recovering from a page fault // TODO: allow recovering from a page fault
throw fmt::Format("Access violation: addr = 0x%x (last_syscall=0x%llx (%s))", throw fmt::Format("Access violation: addr = 0x%x (last_syscall=0x%llx (%s))",
(u32)addr, (u64)GetCurrentCPUThread()->m_last_syscall, SysCalls::GetHLEFuncName((u64)GetCurrentCPUThread()->m_last_syscall).c_str()); (u32)addr, (u64)GetCurrentCPUThread()->m_last_syscall, SysCalls::GetHLEFuncName((u32)GetCurrentCPUThread()->m_last_syscall).c_str());
} }
else else
{ {

6
rpcs3/Emu/CPU/CPUThread.h
View file

@ -37,7 +37,7 @@ protected:
bool m_is_step; bool m_is_step;
u64 m_stack_addr; u64 m_stack_addr;
u64 m_stack_size; u32 m_stack_size;
u64 m_stack_point; u64 m_stack_point;
u64 m_exit_status; u64 m_exit_status;
@ -51,11 +51,11 @@ public:
virtual void CloseStack(); virtual void CloseStack();
u64 GetStackAddr() const { return m_stack_addr; } u64 GetStackAddr() const { return m_stack_addr; }
u64 GetStackSize() const { return m_stack_size; } u32 GetStackSize() const { return m_stack_size; }
virtual u64 GetFreeStackSize() const=0; virtual u64 GetFreeStackSize() const=0;
void SetStackAddr(u64 stack_addr) { m_stack_addr = stack_addr; } void SetStackAddr(u64 stack_addr) { m_stack_addr = stack_addr; }
void SetStackSize(u64 stack_size) { m_stack_size = stack_size; } void SetStackSize(u32 stack_size) { m_stack_size = stack_size; }
virtual void SetArg(const uint pos, const u64 arg) = 0; virtual void SetArg(const uint pos, const u64 arg) = 0;

146
rpcs3/Emu/Cell/PPUInterpreter.h
View file

@ -68,12 +68,12 @@ private:
const u64 old_sc = CPU.m_last_syscall; const u64 old_sc = CPU.m_last_syscall;
CPU.m_last_syscall = sc; CPU.m_last_syscall = sc;
SysCalls::DoSyscall(sc); SysCalls::DoSyscall((u32)sc);
if(Ini.HLELogging.GetValue()) if(Ini.HLELogging.GetValue())
{ {
LOG_WARNING(PPU, "SysCall[0x%llx ('%s')] done with code [0x%llx]! #pc: 0x%llx", LOG_WARNING(PPU, "SysCall[0x%llx ('%s')] done with code [0x%llx]! #pc: 0x%llx",
sc, SysCalls::GetHLEFuncName(sc).c_str(), CPU.GPR[3], CPU.PC); sc, SysCalls::GetHLEFuncName((u32)sc).c_str(), CPU.GPR[3], CPU.PC);
} }
#ifdef HLE_CALL_DEBUG #ifdef HLE_CALL_DEBUG
LOG_NOTICE(PPU, "SysCall[%lld] done with code [0x%llx]! #pc: 0x%llx", sc, CPU.GPR[3], CPU.PC); LOG_NOTICE(PPU, "SysCall[%lld] done with code [0x%llx]! #pc: 0x%llx", sc, CPU.GPR[3], CPU.PC);
@ -155,7 +155,7 @@ private:
void TWI(u32 to, u32 ra, s32 simm16) void TWI(u32 to, u32 ra, s32 simm16)
{ {
s32 a = CPU.GPR[ra]; s32 a = (s32)CPU.GPR[ra];
if( (a < simm16 && (to & 0x10)) || if( (a < simm16 && (to & 0x10)) ||
(a > simm16 && (to & 0x8)) || (a > simm16 && (to & 0x8)) ||
@ -208,7 +208,7 @@ private:
CPU.VSCR.SAT = 1; CPU.VSCR.SAT = 1;
} }
else else
CPU.VPR[vd]._s8[b] = result; CPU.VPR[vd]._s8[b] = (s8)result;
} }
} }
void VADDSHS(u32 vd, u32 va, u32 vb) void VADDSHS(u32 vd, u32 va, u32 vb)
@ -248,7 +248,7 @@ private:
CPU.VSCR.SAT = 1; CPU.VSCR.SAT = 1;
} }
else else
CPU.VPR[vd]._s32[w] = result; CPU.VPR[vd]._s32[w] = (s32)result;
} }
} }
void VADDUBM(u32 vd, u32 va, u32 vb) void VADDUBM(u32 vd, u32 va, u32 vb)
@ -270,7 +270,7 @@ private:
CPU.VSCR.SAT = 1; CPU.VSCR.SAT = 1;
} }
else else
CPU.VPR[vd]._u8[b] = result; CPU.VPR[vd]._u8[b] = (u8)result;
} }
} }
void VADDUHM(u32 vd, u32 va, u32 vb) void VADDUHM(u32 vd, u32 va, u32 vb)
@ -314,7 +314,7 @@ private:
CPU.VSCR.SAT = 1; CPU.VSCR.SAT = 1;
} }
else else
CPU.VPR[vd]._u32[w] = result; CPU.VPR[vd]._u32[w] = (u32)result;
} }
} }
void VAND(u32 vd, u32 va, u32 vb) void VAND(u32 vd, u32 va, u32 vb)
@ -1256,7 +1256,7 @@ private:
CPU.VSCR.SAT = 1; CPU.VSCR.SAT = 1;
} }
CPU.VPR[vd]._s8[b+8] = result; CPU.VPR[vd]._s8[b+8] = (s8)result;
result = CPU.VPR[vb]._s16[b]; result = CPU.VPR[vb]._s16[b];
@ -1271,7 +1271,7 @@ private:
CPU.VSCR.SAT = 1; CPU.VSCR.SAT = 1;
} }
CPU.VPR[vd]._s8[b] = result; CPU.VPR[vd]._s8[b] = (s8)result;
} }
} }
void VPKSHUS(u32 vd, u32 va, u32 vb) void VPKSHUS(u32 vd, u32 va, u32 vb)
@ -1291,7 +1291,7 @@ private:
CPU.VSCR.SAT = 1; CPU.VSCR.SAT = 1;
} }
CPU.VPR[vd]._u8[b+8] = result; CPU.VPR[vd]._u8[b+8] = (u8)result;
result = CPU.VPR[vb]._s16[b]; result = CPU.VPR[vb]._s16[b];
@ -1306,7 +1306,7 @@ private:
CPU.VSCR.SAT = 1; CPU.VSCR.SAT = 1;
} }
CPU.VPR[vd]._u8[b] = result; CPU.VPR[vd]._u8[b] = (u8)result;
} }
} }
void VPKSWSS(u32 vd, u32 va, u32 vb) void VPKSWSS(u32 vd, u32 va, u32 vb)
@ -1399,7 +1399,7 @@ private:
CPU.VSCR.SAT = 1; CPU.VSCR.SAT = 1;
} }
CPU.VPR[vd]._u8[b+8] = result; CPU.VPR[vd]._u8[b+8] = (u8)result;
result = CPU.VPR[vb]._u16[b]; result = CPU.VPR[vb]._u16[b];
@ -1409,7 +1409,7 @@ private:
CPU.VSCR.SAT = 1; CPU.VSCR.SAT = 1;
} }
CPU.VPR[vd]._u8[b] = result; CPU.VPR[vd]._u8[b] = (u8)result;
} }
} }
void VPKUWUM(u32 vd, u32 va, u32 vb) void VPKUWUM(u32 vd, u32 va, u32 vb)
@ -1502,7 +1502,7 @@ private:
{ {
for (uint w = 0; w < 4; w++) for (uint w = 0; w < 4; w++)
{ {
CPU.VPR[vd]._u32[w] = rotl32(CPU.VPR[va]._u32[w], CPU.VPR[vb]._u8[w*4] & 0x1f); CPU.VPR[vd]._u32[w] = (u32)rotl32(CPU.VPR[va]._u32[w], CPU.VPR[vb]._u8[w*4] & 0x1f);
} }
} }
void VRSQRTEFP(u32 vd, u32 vb) void VRSQRTEFP(u32 vd, u32 vb)
@ -2093,7 +2093,7 @@ private:
case 0x1: UNK(fmt::Format("HyperCall %d", CPU.GPR[0])); break; case 0x1: UNK(fmt::Format("HyperCall %d", CPU.GPR[0])); break;
case 0x2: SysCall(); break; case 0x2: SysCall(); break;
case 0x3: case 0x3:
Emu.GetSFuncManager().StaticExecute(CPU.GPR[11]); Emu.GetSFuncManager().StaticExecute((u32)CPU.GPR[11]);
if (Ini.HLELogging.GetValue()) if (Ini.HLELogging.GetValue())
{ {
LOG_NOTICE(PPU, "'%s' done with code[0x%llx]! #pc: 0x%llx", LOG_NOTICE(PPU, "'%s' done with code[0x%llx]! #pc: 0x%llx",
@ -2244,11 +2244,11 @@ private:
{ {
if (is_r) // rldcr if (is_r) // rldcr
{ {
RLDICR(ra, rs, CPU.GPR[rb], m_eb, rc); RLDICR(ra, rs, (u32)CPU.GPR[rb], m_eb, rc);
} }
else // rldcl else // rldcl
{ {
RLDICL(ra, rs, CPU.GPR[rb], m_eb, rc); RLDICL(ra, rs, (u32)CPU.GPR[rb], m_eb, rc);
} }
} }
void CMP(u32 crfd, u32 l, u32 ra, u32 rb) void CMP(u32 crfd, u32 l, u32 ra, u32 rb)
@ -2257,8 +2257,8 @@ private:
} }
void TW(u32 to, u32 ra, u32 rb) void TW(u32 to, u32 ra, u32 rb)
{ {
s32 a = CPU.GPR[ra]; s32 a = (s32)CPU.GPR[ra];
s32 b = CPU.GPR[rb]; s32 b = (s32)CPU.GPR[rb];
if( (a < b && (to & 0x10)) || if( (a < b && (to & 0x10)) ||
(a > b && (to & 0x8)) || (a > b && (to & 0x8)) ||
@ -2328,8 +2328,8 @@ private:
} }
void MULHWU(u32 rd, u32 ra, u32 rb, bool rc) void MULHWU(u32 rd, u32 ra, u32 rb, bool rc)
{ {
u32 a = CPU.GPR[ra]; u32 a = (u32)CPU.GPR[ra];
u32 b = CPU.GPR[rb]; u32 b = (u32)CPU.GPR[rb];
CPU.GPR[rd] = ((u64)a * (u64)b) >> 32; CPU.GPR[rd] = ((u64)a * (u64)b) >> 32;
if(rc) CPU.UpdateCR0<s64>(CPU.GPR[rd]); if(rc) CPU.UpdateCR0<s64>(CPU.GPR[rd]);
} }
@ -2380,8 +2380,8 @@ private:
void SLW(u32 ra, u32 rs, u32 rb, bool rc) void SLW(u32 ra, u32 rs, u32 rb, bool rc)
{ {
u32 n = CPU.GPR[rb] & 0x1f; u32 n = CPU.GPR[rb] & 0x1f;
u32 r = rotl32((u32)CPU.GPR[rs], n); u32 r = (u32)rotl32((u32)CPU.GPR[rs], n);
u32 m = (CPU.GPR[rb] & 0x20) ? 0 : rotate_mask[32][63 - n]; u32 m = ((u32)CPU.GPR[rb] & 0x20) ? 0 : (u32)rotate_mask[32][63 - n];
CPU.GPR[ra] = r & m; CPU.GPR[ra] = r & m;
@ -2509,8 +2509,8 @@ private:
} }
void MULHW(u32 rd, u32 ra, u32 rb, bool rc) void MULHW(u32 rd, u32 ra, u32 rb, bool rc)
{ {
s32 a = CPU.GPR[ra]; s32 a = (s32)CPU.GPR[ra];
s32 b = CPU.GPR[rb]; s32 b = (s32)CPU.GPR[rb];
CPU.GPR[rd] = ((s64)a * (s64)b) >> 32; CPU.GPR[rd] = ((s64)a * (s64)b) >> 32;
if(rc) CPU.UpdateCR0<s64>(CPU.GPR[rd]); if(rc) CPU.UpdateCR0<s64>(CPU.GPR[rd]);
} }
@ -2644,7 +2644,7 @@ private:
} }
void STWX(u32 rs, u32 ra, u32 rb) void STWX(u32 rs, u32 ra, u32 rb)
{ {
Memory.Write32((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), CPU.GPR[rs]); Memory.Write32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb], (u32)CPU.GPR[rs]);
} }
void STVEHX(u32 vs, u32 ra, u32 rb) void STVEHX(u32 vs, u32 ra, u32 rb)
{ {
@ -2661,7 +2661,7 @@ private:
void STWUX(u32 rs, u32 ra, u32 rb) void STWUX(u32 rs, u32 ra, u32 rb)
{ {
const u64 addr = CPU.GPR[ra] + CPU.GPR[rb]; const u64 addr = CPU.GPR[ra] + CPU.GPR[rb];
Memory.Write32(addr, CPU.GPR[rs]); Memory.Write32(addr, (u32)CPU.GPR[rs]);
CPU.GPR[ra] = addr; CPU.GPR[ra] = addr;
} }
void STVEWX(u32 vs, u32 ra, u32 rb) void STVEWX(u32 vs, u32 ra, u32 rb)
@ -2701,7 +2701,7 @@ private:
} }
void STBX(u32 rs, u32 ra, u32 rb) void STBX(u32 rs, u32 ra, u32 rb)
{ {
Memory.Write8((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), CPU.GPR[rs]); Memory.Write8((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), (u8)CPU.GPR[rs]);
} }
void STVX(u32 vs, u32 ra, u32 rb) void STVX(u32 vs, u32 ra, u32 rb)
{ {
@ -2744,7 +2744,7 @@ private:
void STBUX(u32 rs, u32 ra, u32 rb) void STBUX(u32 rs, u32 ra, u32 rb)
{ {
const u64 addr = CPU.GPR[ra] + CPU.GPR[rb]; const u64 addr = CPU.GPR[ra] + CPU.GPR[rb];
Memory.Write8(addr, CPU.GPR[rs]); Memory.Write8(addr, (u8)CPU.GPR[rs]);
CPU.GPR[ra] = addr; CPU.GPR[ra] = addr;
} }
void ADD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) void ADD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc)
@ -2834,7 +2834,7 @@ private:
} }
void STHX(u32 rs, u32 ra, u32 rb) void STHX(u32 rs, u32 ra, u32 rb)
{ {
Memory.Write16(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb], CPU.GPR[rs]); Memory.Write16(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb], (u16)CPU.GPR[rs]);
} }
void ORC(u32 ra, u32 rs, u32 rb, bool rc) void ORC(u32 ra, u32 rs, u32 rb, bool rc)
{ {
@ -2844,12 +2844,12 @@ private:
void ECOWX(u32 rs, u32 ra, u32 rb) void ECOWX(u32 rs, u32 ra, u32 rb)
{ {
//HACK! //HACK!
Memory.Write32((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), CPU.GPR[rs]); Memory.Write32((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), (u32)CPU.GPR[rs]);
} }
void STHUX(u32 rs, u32 ra, u32 rb) void STHUX(u32 rs, u32 ra, u32 rb)
{ {
const u64 addr = CPU.GPR[ra] + CPU.GPR[rb]; const u64 addr = CPU.GPR[ra] + CPU.GPR[rb];
Memory.Write16(addr, CPU.GPR[rs]); Memory.Write16(addr, (u16)CPU.GPR[rs]);
CPU.GPR[ra] = addr; CPU.GPR[ra] = addr;
} }
void OR(u32 ra, u32 rs, u32 rb, bool rc) void OR(u32 ra, u32 rs, u32 rb, bool rc)
@ -2876,8 +2876,8 @@ private:
} }
void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc)
{ {
const u32 RA = CPU.GPR[ra]; const u32 RA = (u32)CPU.GPR[ra];
const u32 RB = CPU.GPR[rb]; const u32 RB = (u32)CPU.GPR[rb];
if(RB == 0) if(RB == 0)
{ {
@ -2925,8 +2925,8 @@ private:
} }
void DIVW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) void DIVW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc)
{ {
const s32 RA = CPU.GPR[ra]; const s32 RA = (s32)CPU.GPR[ra];
const s32 RB = CPU.GPR[rb]; const s32 RB = (s32)CPU.GPR[rb];
if (RB == 0 || ((u32)RA == (1 << 31) && RB == -1)) if (RB == 0 || ((u32)RA == (1 << 31) && RB == -1))
{ {
@ -2967,8 +2967,8 @@ private:
void SRW(u32 ra, u32 rs, u32 rb, bool rc) void SRW(u32 ra, u32 rs, u32 rb, bool rc)
{ {
u32 n = CPU.GPR[rb] & 0x1f; u32 n = CPU.GPR[rb] & 0x1f;
u32 r = rotl32((u32)CPU.GPR[rs], 64 - n); u32 r = (u32)rotl32((u32)CPU.GPR[rs], 64 - n);
u32 m = (CPU.GPR[rb] & 0x20) ? 0 : rotate_mask[32 + n][63]; u32 m = ((u32)CPU.GPR[rb] & 0x20) ? 0 : (u32)rotate_mask[32 + n][63];
CPU.GPR[ra] = r & m; CPU.GPR[ra] = r & m;
if(rc) CPU.UpdateCR0<s64>(CPU.GPR[ra]); if(rc) CPU.UpdateCR0<s64>(CPU.GPR[ra]);
@ -2993,7 +2993,7 @@ private:
{ {
u64 EA = ra ? CPU.GPR[ra] : 0; u64 EA = ra ? CPU.GPR[ra] : 0;
u64 N = nb ? nb : 32; u64 N = nb ? nb : 32;
u8 reg = CPU.GPR[rd]; u8 reg = (u8)CPU.GPR[rd];
while (N > 0) while (N > 0)
{ {
@ -3051,7 +3051,7 @@ private:
} }
void STWBRX(u32 rs, u32 ra, u32 rb) void STWBRX(u32 rs, u32 ra, u32 rb)
{ {
(u32&)Memory[ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]] = CPU.GPR[rs]; (u32&)Memory[ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]] = (u32)CPU.GPR[rs];
} }
void STFSX(u32 frs, u32 ra, u32 rb) void STFSX(u32 frs, u32 ra, u32 rb)
{ {
@ -3072,31 +3072,31 @@ private:
} }
void STSWI(u32 rd, u32 ra, u32 nb) void STSWI(u32 rd, u32 ra, u32 nb)
{ {
u64 EA = ra ? CPU.GPR[ra] : 0; u64 EA = ra ? CPU.GPR[ra] : 0;
u64 N = nb ? nb : 32; u64 N = nb ? nb : 32;
u8 reg = CPU.GPR[rd]; u8 reg = (u8)CPU.GPR[rd];
while (N > 0) while (N > 0)
{
if (N > 3)
{ {
if (N > 3) Memory.Write32(EA, (u32)CPU.GPR[reg]);
{ EA += 4;
Memory.Write32(EA, CPU.GPR[reg]); N -= 4;
EA += 4;
N -= 4;
}
else
{
u32 buf = CPU.GPR[reg];
while (N > 0)
{
N = N - 1;
Memory.Write8(EA, (0xFF000000 & buf) >> 24);
buf <<= 8;
EA = EA + 1;
}
}
reg = (reg + 1) % 32;
} }
else
{
u32 buf = (u32)CPU.GPR[reg];
while (N > 0)
{
N = N - 1;
Memory.Write8(EA, (0xFF000000 & buf) >> 24);
buf <<= 8;
EA = EA + 1;
}
}
reg = (reg + 1) % 32;
}
} }
void STFDX(u32 frs, u32 ra, u32 rb) void STFDX(u32 frs, u32 ra, u32 rb)
{ {
@ -3121,7 +3121,7 @@ private:
} }
void SRAW(u32 ra, u32 rs, u32 rb, bool rc) void SRAW(u32 ra, u32 rs, u32 rb, bool rc)
{ {
s32 RS = CPU.GPR[rs]; s32 RS = (s32)CPU.GPR[rs];
u8 shift = CPU.GPR[rb] & 63; u8 shift = CPU.GPR[rb] & 63;
if (shift > 31) if (shift > 31)
{ {
@ -3197,7 +3197,7 @@ private:
} }
void STHBRX(u32 rs, u32 ra, u32 rb) void STHBRX(u32 rs, u32 ra, u32 rb)
{ {
(u16&)Memory[ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]] = CPU.GPR[rs]; (u16&)Memory[ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]] = (u16)CPU.GPR[rs];
} }
void EXTSH(u32 ra, u32 rs, bool rc) void EXTSH(u32 ra, u32 rs, bool rc)
{ {
@ -3259,22 +3259,22 @@ private:
} }
void STW(u32 rs, u32 ra, s32 d) void STW(u32 rs, u32 ra, s32 d)
{ {
Memory.Write32(ra ? CPU.GPR[ra] + d : d, CPU.GPR[rs]); Memory.Write32(ra ? CPU.GPR[ra] + d : d, (u32)CPU.GPR[rs]);
} }
void STWU(u32 rs, u32 ra, s32 d) void STWU(u32 rs, u32 ra, s32 d)
{ {
const u64 addr = CPU.GPR[ra] + d; const u64 addr = CPU.GPR[ra] + d;
Memory.Write32(addr, CPU.GPR[rs]); Memory.Write32(addr, (u32)CPU.GPR[rs]);
CPU.GPR[ra] = addr; CPU.GPR[ra] = addr;
} }
void STB(u32 rs, u32 ra, s32 d) void STB(u32 rs, u32 ra, s32 d)
{ {
Memory.Write8(ra ? CPU.GPR[ra] + d : d, CPU.GPR[rs]); Memory.Write8(ra ? CPU.GPR[ra] + d : d, (u8)CPU.GPR[rs]);
} }
void STBU(u32 rs, u32 ra, s32 d) void STBU(u32 rs, u32 ra, s32 d)
{ {
const u64 addr = CPU.GPR[ra] + d; const u64 addr = CPU.GPR[ra] + d;
Memory.Write8(addr, CPU.GPR[rs]); Memory.Write8(addr, (u8)CPU.GPR[rs]);
CPU.GPR[ra] = addr; CPU.GPR[ra] = addr;
} }
void LHZ(u32 rd, u32 ra, s32 d) void LHZ(u32 rd, u32 ra, s32 d)
@ -3299,12 +3299,12 @@ private:
} }
void STH(u32 rs, u32 ra, s32 d) void STH(u32 rs, u32 ra, s32 d)
{ {
Memory.Write16(ra ? CPU.GPR[ra] + d : d, CPU.GPR[rs]); Memory.Write16(ra ? CPU.GPR[ra] + d : d, (u16)CPU.GPR[rs]);
} }
void STHU(u32 rs, u32 ra, s32 d) void STHU(u32 rs, u32 ra, s32 d)
{ {
const u64 addr = CPU.GPR[ra] + d; const u64 addr = CPU.GPR[ra] + d;
Memory.Write16(addr, CPU.GPR[rs]); Memory.Write16(addr, (u16)CPU.GPR[rs]);
CPU.GPR[ra] = addr; CPU.GPR[ra] = addr;
} }
void LMW(u32 rd, u32 ra, s32 d) void LMW(u32 rd, u32 ra, s32 d)
@ -3320,7 +3320,7 @@ private:
u64 addr = ra ? CPU.GPR[ra] + d : d; u64 addr = ra ? CPU.GPR[ra] + d : d;
for(u32 i=rs; i<32; ++i, addr += 4) for(u32 i=rs; i<32; ++i, addr += 4)
{ {
Memory.Write32(addr, CPU.GPR[i]); Memory.Write32(addr, (u32)CPU.GPR[i]);
} }
} }
void LFS(u32 frd, u32 ra, s32 d) void LFS(u32 frd, u32 ra, s32 d)
@ -3891,7 +3891,7 @@ private:
break; break;
} }
r = (u64)i; r = (u64)i;
double di = i; double di = (double)i;
if (di == b) if (di == b)
{ {
CPU.SetFPSCR_FI(0); CPU.SetFPSCR_FI(0);
@ -3930,7 +3930,7 @@ private:
else else
{ {
s64 i = (s64)b; s64 i = (s64)b;
double di = i; double di = (double)i;
if (di == b) if (di == b)
{ {
CPU.SetFPSCR_FI(0); CPU.SetFPSCR_FI(0);

2
rpcs3/Emu/Cell/PPUThread.cpp
View file

@ -108,7 +108,7 @@ void PPUThread::InitRegs()
m_stack_point -= 0xc + 4 * argc; m_stack_point -= 0xc + 4 * argc;
u64 argv = m_stack_point; u64 argv = m_stack_point;
mem64_ptr_t argv_list(argv); mem64_ptr_t argv_list((u32)argv);
for(int i=0; i<argc; ++i) argv_list += m_argv_addr[i]; for(int i=0; i<argc; ++i) argv_list += m_argv_addr[i];
GPR[3] = argc; GPR[3] = argc;

10
rpcs3/Emu/Cell/PPUThread.h
View file

@ -389,7 +389,7 @@ struct PPCdouble
u32 To32() const u32 To32() const
{ {
float res = _double; float res = (float)_double;
return (u32&)res; return (u32&)res;
} }
@ -686,7 +686,7 @@ public:
} }
else else
{ {
UpdateCRn<u32>(n, a, b); UpdateCRn<u32>(n, (u32)a, (u32)b);
} }
} }
@ -694,11 +694,11 @@ public:
{ {
if(l) if(l)
{ {
UpdateCRn<s64>(n, a, b); UpdateCRn<s64>(n, (s64)a, (s64)b);
} }
else else
{ {
UpdateCRn<s32>(n, a, b); UpdateCRn<s32>(n, (s32)a, (s32)b);
} }
} }
@ -822,7 +822,7 @@ public:
} }
if (reg == "CR" || reg == "FPSCR") if (reg == "CR" || reg == "FPSCR")
{ {
unsigned long reg_value; unsigned long long reg_value;
reg_value = std::stoull(value.substr(24, 31), 0, 16); reg_value = std::stoull(value.substr(24, 31), 0, 16);
if (reg == "CR") CR.CR = (u32)reg_value; if (reg == "CR") CR.CR = (u32)reg_value;
if (reg == "FPSCR") FPSCR.FPSCR = (u32)reg_value; if (reg == "FPSCR") FPSCR.FPSCR = (u32)reg_value;

8
rpcs3/Emu/Cell/RawSPUThread.cpp
View file

@ -155,6 +155,12 @@ bool RawSPUThread::Write32(const u64 addr, const u32 value)
case SPU_NPC_offs: case SPU_NPC_offs:
{ {
if (value & 3)
{
// least significant bit contains some interrupt flag
LOG_ERROR(Log::SPU, "RawSPUThread[%d]: Write32(SPU_NPC_offs, 0x%x): lowest bits set", m_index, value);
return false;
}
SPU.NPC.SetValue(value); SPU.NPC.SetValue(value);
break; break;
} }
@ -199,5 +205,5 @@ void RawSPUThread::Task()
SPUThread::Task(); SPUThread::Task();
SPU.NPC.SetValue(PC); SPU.NPC.SetValue((u32)PC);
} }

4
rpcs3/Emu/Cell/RawSPUThread.h
View file

@ -16,9 +16,9 @@ public:
RawSPUThread(CPUThreadType type = CPU_THREAD_RAW_SPU); RawSPUThread(CPUThreadType type = CPU_THREAD_RAW_SPU);
virtual ~RawSPUThread(); virtual ~RawSPUThread();
virtual bool Read32(const u64 addr, u32* value) override; bool Read32(const u64 addr, u32* value);
virtual bool Write32(const u64 addr, const u32 value) override; bool Write32(const u64 addr, const u32 value);
public: public:
virtual void InitRegs(); virtual void InitRegs();

10
rpcs3/Emu/Cell/SPUInterpreter.h
View file

@ -357,7 +357,7 @@ private:
u64 target = branchTarget(CPU.GPR[ra]._u32[3], 0); u64 target = branchTarget(CPU.GPR[ra]._u32[3], 0);
CPU.GPR[rt].Reset(); CPU.GPR[rt].Reset();
CPU.GPR[rt]._u32[3] = CPU.PC + 4; CPU.GPR[rt]._u32[3] = (u32)CPU.PC + 4;
LOG5_OPCODE("branch (0x%llx)", target); LOG5_OPCODE("branch (0x%llx)", target);
CPU.SetBranch(target); CPU.SetBranch(target);
} }
@ -1063,7 +1063,7 @@ private:
if (CPU.GPR[rt]._f[i] > 0xffffffff) //if big, result = max if (CPU.GPR[rt]._f[i] > 0xffffffff) //if big, result = max
CPU.GPR[rt]._u32[i] = 0xffffffff; CPU.GPR[rt]._u32[i] = 0xffffffff;
else else
CPU.GPR[rt]._u32[i] = floor(CPU.GPR[rt]._f[i]); CPU.GPR[rt]._u32[i] = (u32)floor(CPU.GPR[rt]._f[i]);
} }
} }
} }
@ -1072,7 +1072,7 @@ private:
const u32 scale = 155 - (i8 & 0xff); //unsigned immediate const u32 scale = 155 - (i8 & 0xff); //unsigned immediate
for (int i = 0; i < 4; i++) for (int i = 0; i < 4; i++)
{ {
CPU.GPR[rt]._f[i] = (s32)CPU.GPR[ra]._i32[i]; CPU.GPR[rt]._f[i] = (float)CPU.GPR[ra]._i32[i];
u32 exp = ((CPU.GPR[rt]._u32[i] >> 23) & 0xff) - scale; u32 exp = ((CPU.GPR[rt]._u32[i] >> 23) & 0xff) - scale;
@ -1178,7 +1178,7 @@ private:
{ {
u64 target = branchTarget(0, i16); u64 target = branchTarget(0, i16);
CPU.GPR[rt].Reset(); CPU.GPR[rt].Reset();
CPU.GPR[rt]._u32[3] = CPU.PC + 4; CPU.GPR[rt]._u32[3] = (u32)CPU.PC + 4;
LOG5_OPCODE("branch (0x%llx)", target); LOG5_OPCODE("branch (0x%llx)", target);
CPU.SetBranch(target); CPU.SetBranch(target);
} }
@ -1208,7 +1208,7 @@ private:
{ {
u64 target = branchTarget(CPU.PC, i16); u64 target = branchTarget(CPU.PC, i16);
CPU.GPR[rt].Reset(); CPU.GPR[rt].Reset();
CPU.GPR[rt]._u32[3] = CPU.PC + 4; CPU.GPR[rt]._u32[3] = (u32)CPU.PC + 4;
LOG5_OPCODE("branch (0x%llx)", target); LOG5_OPCODE("branch (0x%llx)", target);
CPU.SetBranch(target); CPU.SetBranch(target);
} }

58
rpcs3/Emu/Cell/SPURecompiler.h
View file

@ -108,14 +108,14 @@ public:
#define c (*compiler) #define c (*compiler)
#ifdef _WIN32 #ifdef _WIN32
#define cpu_xmm(x) oword_ptr(*cpu_var, (sizeof((*(SPUThread*)nullptr).x) == 16) ? offsetof(SPUThread, x) : throw "sizeof("#x") != 16") #define cpu_xmm(x) oword_ptr(*cpu_var, (sizeof((*(SPUThread*)nullptr).x) == 16) ? (s32)offsetof(SPUThread, x) : throw "sizeof("#x") != 16")
#define cpu_qword(x) qword_ptr(*cpu_var, (sizeof((*(SPUThread*)nullptr).x) == 8) ? offsetof(SPUThread, x) : throw "sizeof("#x") != 8") #define cpu_qword(x) qword_ptr(*cpu_var, (sizeof((*(SPUThread*)nullptr).x) == 8) ? (s32)offsetof(SPUThread, x) : throw "sizeof("#x") != 8")
#define cpu_dword(x) dword_ptr(*cpu_var, (sizeof((*(SPUThread*)nullptr).x) == 4) ? offsetof(SPUThread, x) : throw "sizeof("#x") != 4") #define cpu_dword(x) dword_ptr(*cpu_var, (sizeof((*(SPUThread*)nullptr).x) == 4) ? (s32)offsetof(SPUThread, x) : throw "sizeof("#x") != 4")
#define cpu_word(x) word_ptr(*cpu_var, (sizeof((*(SPUThread*)nullptr).x) == 2) ? offsetof(SPUThread, x) : throw "sizeof("#x") != 2") #define cpu_word(x) word_ptr(*cpu_var, (sizeof((*(SPUThread*)nullptr).x) == 2) ? (s32)offsetof(SPUThread, x) : throw "sizeof("#x") != 2")
#define cpu_byte(x) byte_ptr(*cpu_var, (sizeof((*(SPUThread*)nullptr).x) == 1) ? offsetof(SPUThread, x) : throw "sizeof("#x") != 1") #define cpu_byte(x) byte_ptr(*cpu_var, (sizeof((*(SPUThread*)nullptr).x) == 1) ? (s32)offsetof(SPUThread, x) : throw "sizeof("#x") != 1")
#define g_imm_xmm(x) oword_ptr(*g_imm_var, offsetof(g_imm_table_struct, x)) #define g_imm_xmm(x) oword_ptr(*g_imm_var, (s32)offsetof(g_imm_table_struct, x))
#define g_imm2_xmm(x, y) oword_ptr(*g_imm_var, y, 0, offsetof(g_imm_table_struct, x)) #define g_imm2_xmm(x, y) oword_ptr(*g_imm_var, y, 0, (s32)offsetof(g_imm_table_struct, x))
#else #else
#define cpu_xmm(x) oword_ptr(*cpu_var, reinterpret_cast<uintptr_t>(&(((SPUThread*)0)->x)) ) #define cpu_xmm(x) oword_ptr(*cpu_var, reinterpret_cast<uintptr_t>(&(((SPUThread*)0)->x)) )
#define cpu_qword(x) qword_ptr(*cpu_var, reinterpret_cast<uintptr_t>(&(((SPUThread*)0)->x)) ) #define cpu_qword(x) qword_ptr(*cpu_var, reinterpret_cast<uintptr_t>(&(((SPUThread*)0)->x)) )
@ -418,9 +418,9 @@ public:
return oword_ptr(*imm_var, i * sizeof(__m128i)); return oword_ptr(*imm_var, i * sizeof(__m128i));
} }
} }
const int shift = rec.imm_table.size() * sizeof(__m128i); const size_t shift = rec.imm_table.size() * sizeof(__m128i);
rec.imm_table.push_back(data); rec.imm_table.push_back(data);
return oword_ptr(*imm_var, shift); return oword_ptr(*imm_var, (s32)shift);
} }
Mem XmmConst(const __m128& data) Mem XmmConst(const __m128& data)
@ -1439,7 +1439,7 @@ private:
c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))); c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
XmmFinalize(vr, rt); XmmFinalize(vr, rt);
XmmInvalidate(rt); XmmInvalidate(rt);
c.mov(byte_ptr(*cpu_var, *addr, 0, offsetof(SPUThread, GPR[rt]._u8[0])), 0x03); c.mov(byte_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u8[0])), 0x03);
LOG_OPCODE(); LOG_OPCODE();
} }
void CHX(u32 rt, u32 ra, u32 rb) void CHX(u32 rt, u32 ra, u32 rb)
@ -1460,7 +1460,7 @@ private:
c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))); c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
XmmFinalize(vr, rt); XmmFinalize(vr, rt);
XmmInvalidate(rt); XmmInvalidate(rt);
c.mov(word_ptr(*cpu_var, *addr, 0, offsetof(SPUThread, GPR[rt]._u16[0])), 0x0203); c.mov(word_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u16[0])), 0x0203);
LOG_OPCODE(); LOG_OPCODE();
} }
void CWX(u32 rt, u32 ra, u32 rb) void CWX(u32 rt, u32 ra, u32 rb)
@ -1481,7 +1481,7 @@ private:
c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))); c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
XmmFinalize(vr, rt); XmmFinalize(vr, rt);
XmmInvalidate(rt); XmmInvalidate(rt);
c.mov(dword_ptr(*cpu_var, *addr, 0, offsetof(SPUThread, GPR[rt]._u32[0])), 0x00010203); c.mov(dword_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u32[0])), 0x00010203);
LOG_OPCODE(); LOG_OPCODE();
} }
void CDX(u32 rt, u32 ra, u32 rb) void CDX(u32 rt, u32 ra, u32 rb)
@ -1502,8 +1502,8 @@ private:
c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))); c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
XmmFinalize(vr, rt); XmmFinalize(vr, rt);
XmmInvalidate(rt); XmmInvalidate(rt);
c.mov(dword_ptr(*cpu_var, *addr, 0, offsetof(SPUThread, GPR[rt]._u32[0])), 0x04050607); c.mov(dword_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u32[0])), 0x04050607);
c.mov(dword_ptr(*cpu_var, *addr, 0, offsetof(SPUThread, GPR[rt]._u32[1])), 0x00010203); c.mov(dword_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u32[1])), 0x00010203);
LOG_OPCODE(); LOG_OPCODE();
} }
void ROTQBI(u32 rt, u32 ra, u32 rb) void ROTQBI(u32 rt, u32 ra, u32 rb)
@ -1603,7 +1603,7 @@ private:
c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))); c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
XmmFinalize(vr, rt); XmmFinalize(vr, rt);
XmmInvalidate(rt); XmmInvalidate(rt);
c.mov(byte_ptr(*cpu_var, *addr, 0, offsetof(SPUThread, GPR[rt]._u8[0])), 0x03); c.mov(byte_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u8[0])), 0x03);
LOG_OPCODE(); LOG_OPCODE();
} }
void CHD(u32 rt, u32 ra, s32 i7) void CHD(u32 rt, u32 ra, s32 i7)
@ -1617,7 +1617,7 @@ private:
c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))); c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
XmmFinalize(vr, rt); XmmFinalize(vr, rt);
XmmInvalidate(rt); XmmInvalidate(rt);
c.mov(word_ptr(*cpu_var, *addr, 0, offsetof(SPUThread, GPR[rt]._u16[0])), 0x0203); c.mov(word_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u16[0])), 0x0203);
LOG_OPCODE(); LOG_OPCODE();
} }
void CWD(u32 rt, u32 ra, s32 i7) void CWD(u32 rt, u32 ra, s32 i7)
@ -1631,7 +1631,7 @@ private:
c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))); c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
XmmFinalize(vr, rt); XmmFinalize(vr, rt);
XmmInvalidate(rt); XmmInvalidate(rt);
c.mov(dword_ptr(*cpu_var, *addr, 0, offsetof(SPUThread, GPR[rt]._u32[0])), 0x00010203); c.mov(dword_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u32[0])), 0x00010203);
LOG_OPCODE(); LOG_OPCODE();
} }
void CDD(u32 rt, u32 ra, s32 i7) void CDD(u32 rt, u32 ra, s32 i7)
@ -1645,8 +1645,8 @@ private:
c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f))); c.movdqa(vr.get(), XmmConst(_mm_set_epi32(0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f)));
XmmFinalize(vr, rt); XmmFinalize(vr, rt);
XmmInvalidate(rt); XmmInvalidate(rt);
c.mov(dword_ptr(*cpu_var, *addr, 0, offsetof(SPUThread, GPR[rt]._u32[0])), 0x04050607); c.mov(dword_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u32[0])), 0x04050607);
c.mov(dword_ptr(*cpu_var, *addr, 0, offsetof(SPUThread, GPR[rt]._u32[1])), 0x00010203); c.mov(dword_ptr(*cpu_var, *addr, 0, (s32)offsetof(SPUThread, GPR[rt]._u32[1])), 0x00010203);
LOG_OPCODE(); LOG_OPCODE();
} }
void ROTQBII(u32 rt, u32 ra, s32 i7) void ROTQBII(u32 rt, u32 ra, s32 i7)
@ -1961,7 +1961,7 @@ private:
for (u32 i = 0; i < 4; i++) for (u32 i = 0; i < 4; i++)
{ {
c.bsr(*addr, cpu_dword(GPR[ra]._u32[i])); c.bsr(*addr, cpu_dword(GPR[ra]._u32[i]));
c.cmovz(*addr, dword_ptr(*g_imm_var, offsetof(g_imm_table_struct, fsmb_table[0xffff]))); // load 0xffffffff c.cmovz(*addr, dword_ptr(*g_imm_var, (s32)offsetof(g_imm_table_struct, fsmb_table[0xffff]))); // load 0xffffffff
c.neg(*addr); c.neg(*addr);
c.add(*addr, 31); c.add(*addr, 31);
c.mov(cpu_dword(GPR[rt]._u32[i]), *addr); c.mov(cpu_dword(GPR[rt]._u32[i]), *addr);
@ -1991,7 +1991,7 @@ private:
for (u32 i = 0; i < 8; i++) for (u32 i = 0; i < 8; i++)
{ {
c.movzx(*addr, cpu_word(GPR[ra]._u16[i])); c.movzx(*addr, cpu_word(GPR[ra]._u16[i]));
c.movzx(*addr, word_ptr(*g_imm_var, *addr, 1, offsetof(g_imm_table_struct, cntb_table[0]))); c.movzx(*addr, word_ptr(*g_imm_var, *addr, 1, (s32)offsetof(g_imm_table_struct, cntb_table[0])));
c.mov(cpu_word(GPR[rt]._u16[i]), addr->r16()); c.mov(cpu_word(GPR[rt]._u16[i]), addr->r16());
}*/ }*/
const XmmLink& va = XmmGet(ra, rt); const XmmLink& va = XmmGet(ra, rt);
@ -2677,9 +2677,9 @@ private:
const XmmLink& va = XmmGet(ra, rt); const XmmLink& va = XmmGet(ra, rt);
if (i8 != 173) if (i8 != 173)
{ {
c.mulps(va.get(), XmmConst(_mm_set1_ps(pow(2, 173 - (i8 & 0xff))))); // scale c.mulps(va.get(), XmmConst(_mm_set1_ps((float)pow(2, 173 - (i8 & 0xff))))); // scale
} }
c.maxps(va.get(), XmmConst(_mm_set1_ps(-pow(2, 31)))); // saturate c.maxps(va.get(), XmmConst(_mm_set1_ps((float)-pow(2, 31)))); // saturate
c.minps(va.get(), XmmConst(_mm_set1_ps((float)0x7fffffff))); c.minps(va.get(), XmmConst(_mm_set1_ps((float)0x7fffffff)));
c.cvttps2dq(va.get(), va.get()); // convert to ints with truncation c.cvttps2dq(va.get(), va.get()); // convert to ints with truncation
XmmFinalize(va, rt); XmmFinalize(va, rt);
@ -2690,13 +2690,13 @@ private:
const XmmLink& va = XmmGet(ra, rt); const XmmLink& va = XmmGet(ra, rt);
if (i8 != 173) if (i8 != 173)
{ {
c.mulps(va.get(), XmmConst(_mm_set1_ps(pow(2, 173 - (i8 & 0xff))))); // scale c.mulps(va.get(), XmmConst(_mm_set1_ps((float)pow(2, 173 - (i8 & 0xff))))); // scale
} }
c.maxps(va.get(), XmmConst(_mm_set1_ps(0.0f))); // saturate c.maxps(va.get(), XmmConst(_mm_set1_ps(0.0f))); // saturate
c.minps(va.get(), XmmConst(_mm_set1_ps((float)0xffffffff))); c.minps(va.get(), XmmConst(_mm_set1_ps((float)0xffffffff)));
const XmmLink& v1 = XmmCopy(va); const XmmLink& v1 = XmmCopy(va);
c.cmpps(v1.get(), XmmConst(_mm_set1_ps(pow(2, 31))), 5); // generate mask of big values c.cmpps(v1.get(), XmmConst(_mm_set1_ps((float)pow(2, 31))), 5); // generate mask of big values
c.andps(v1.get(), XmmConst(_mm_set1_ps(pow(2, 32)))); // generate correction component c.andps(v1.get(), XmmConst(_mm_set1_ps((float)pow(2, 32)))); // generate correction component
c.subps(va.get(), v1.get()); // subtract correction component c.subps(va.get(), v1.get()); // subtract correction component
c.cvttps2dq(va.get(), va.get()); // convert to ints with truncation c.cvttps2dq(va.get(), va.get()); // convert to ints with truncation
XmmFinalize(va, rt); XmmFinalize(va, rt);
@ -2709,7 +2709,7 @@ private:
c.cvtdq2ps(va.get(), va.get()); // convert to floats c.cvtdq2ps(va.get(), va.get()); // convert to floats
if (i8 != 155) if (i8 != 155)
{ {
c.mulps(va.get(), XmmConst(_mm_set1_ps(pow(2, (i8 & 0xff) - 155)))); // scale c.mulps(va.get(), XmmConst(_mm_set1_ps((float)pow(2, (i8 & 0xff) - 155)))); // scale
} }
XmmFinalize(va, rt); XmmFinalize(va, rt);
LOG_OPCODE(); LOG_OPCODE();
@ -2720,11 +2720,11 @@ private:
const XmmLink& v1 = XmmCopy(va); const XmmLink& v1 = XmmCopy(va);
c.cvtdq2ps(va.get(), va.get()); // convert to floats c.cvtdq2ps(va.get(), va.get()); // convert to floats
c.psrad(v1.get(), 32); // generate mask from sign bit c.psrad(v1.get(), 32); // generate mask from sign bit
c.andps(v1.get(), XmmConst(_mm_set1_ps(pow(2, 32)))); // generate correction component c.andps(v1.get(), XmmConst(_mm_set1_ps((float)pow(2, 32)))); // generate correction component
c.addps(va.get(), v1.get()); // add correction component c.addps(va.get(), v1.get()); // add correction component
if (i8 != 155) if (i8 != 155)
{ {
c.mulps(va.get(), XmmConst(_mm_set1_ps(pow(2, (i8 & 0xff) - 155)))); // scale c.mulps(va.get(), XmmConst(_mm_set1_ps((float)pow(2, (i8 & 0xff) - 155)))); // scale
} }
XmmFinalize(va, rt); XmmFinalize(va, rt);
XmmFinalize(v1); XmmFinalize(v1);

2
rpcs3/Emu/Cell/SPURecompilerCore.cpp
View file

@ -183,7 +183,7 @@ u8 SPURecompilerCore::DecodeMemory(const u64 address)
{ {
assert(CPU.dmac.ls_offset == address - CPU.PC); assert(CPU.dmac.ls_offset == address - CPU.PC);
const u64 m_offset = CPU.dmac.ls_offset; const u64 m_offset = CPU.dmac.ls_offset;
const u16 pos = (CPU.PC >> 2); const u16 pos = (u16)(CPU.PC >> 2);
//ConLog.Write("DecodeMemory: pos=%d", pos); //ConLog.Write("DecodeMemory: pos=%d", pos);
u32* ls = (u32*)&Memory[m_offset]; u32* ls = (u32*)&Memory[m_offset];

20
rpcs3/Emu/Cell/SPUThread.h
View file

@ -522,17 +522,17 @@ public:
void StopAndSignal(u32 code); void StopAndSignal(u32 code);
virtual u8 ReadLS8 (const u32 lsa) const { return Memory.Read8 (lsa + m_offset); } u8 ReadLS8 (const u32 lsa) const { return Memory.Read8 (lsa + m_offset); }
virtual u16 ReadLS16 (const u32 lsa) const { return Memory.Read16 (lsa + m_offset); } u16 ReadLS16 (const u32 lsa) const { return Memory.Read16 (lsa + m_offset); }
virtual u32 ReadLS32 (const u32 lsa) const { return Memory.Read32 (lsa + m_offset); } u32 ReadLS32 (const u32 lsa) const { return Memory.Read32 (lsa + m_offset); }
virtual u64 ReadLS64 (const u32 lsa) const { return Memory.Read64 (lsa + m_offset); } u64 ReadLS64 (const u32 lsa) const { return Memory.Read64 (lsa + m_offset); }
virtual u128 ReadLS128(const u32 lsa) const { return Memory.Read128(lsa + m_offset); } u128 ReadLS128(const u32 lsa) const { return Memory.Read128(lsa + m_offset); }
virtual void WriteLS8 (const u32 lsa, const u8& data) const { Memory.Write8 (lsa + m_offset, data); } void WriteLS8 (const u32 lsa, const u8& data) const { Memory.Write8 (lsa + m_offset, data); }
virtual void WriteLS16 (const u32 lsa, const u16& data) const { Memory.Write16 (lsa + m_offset, data); } void WriteLS16 (const u32 lsa, const u16& data) const { Memory.Write16 (lsa + m_offset, data); }
virtual void WriteLS32 (const u32 lsa, const u32& data) const { Memory.Write32 (lsa + m_offset, data); } void WriteLS32 (const u32 lsa, const u32& data) const { Memory.Write32 (lsa + m_offset, data); }
virtual void WriteLS64 (const u32 lsa, const u64& data) const { Memory.Write64 (lsa + m_offset, data); } void WriteLS64 (const u32 lsa, const u64& data) const { Memory.Write64 (lsa + m_offset, data); }
virtual void WriteLS128(const u32 lsa, const u128& data) const { Memory.Write128(lsa + m_offset, data); } void WriteLS128(const u32 lsa, const u128& data) const { Memory.Write128(lsa + m_offset, data); }
public: public:
SPUThread(CPUThreadType type = CPU_THREAD_SPU); SPUThread(CPUThreadType type = CPU_THREAD_SPU);

4
rpcs3/Emu/IdManager.h
View file

@ -177,7 +177,7 @@ public:
return true; return true;
} }
bool HasID(const s64 id) bool HasID(const u32 id)
{ {
{ {
std::lock_guard<std::mutex> lock(m_mtx_main); std::lock_guard<std::mutex> lock(m_mtx_main);
@ -211,7 +211,7 @@ public:
u32 GetTypeCount(IDType type) u32 GetTypeCount(IDType type)
{ {
if (type < TYPE_OTHER) { if (type < TYPE_OTHER) {
return m_types[type].size(); return (u32)m_types[type].size();
} }
return 1; return 1;
} }

217
rpcs3/Emu/Memory/Memory.cpp
View file

@ -2,6 +2,7 @@
#include "Utilities/Log.h" #include "Utilities/Log.h"
#include "Emu/System.h" #include "Emu/System.h"
#include "Memory.h" #include "Memory.h"
#include "Emu/Cell/RawSPUThread.h"
#ifndef _WIN32 #ifndef _WIN32
#include <sys/mman.h> #include <sys/mman.h>
@ -191,7 +192,7 @@ void MemoryBase::WriteMMIO32(u32 addr, const u32 data)
std::lock_guard<std::recursive_mutex> lock(m_mutex); std::lock_guard<std::recursive_mutex> lock(m_mutex);
if (RawSPUMem[(addr - RAW_SPU_BASE_ADDR) / RAW_SPU_OFFSET] && if (RawSPUMem[(addr - RAW_SPU_BASE_ADDR) / RAW_SPU_OFFSET] &&
RawSPUMem[(addr - RAW_SPU_BASE_ADDR) / RAW_SPU_OFFSET]->Write32(addr, data)) ((RawSPUThread*)RawSPUMem[(addr - RAW_SPU_BASE_ADDR) / RAW_SPU_OFFSET])->Write32(addr, data))
{ {
return; return;
} }
@ -207,7 +208,7 @@ u32 MemoryBase::ReadMMIO32(u32 addr)
std::lock_guard<std::recursive_mutex> lock(m_mutex); std::lock_guard<std::recursive_mutex> lock(m_mutex);
if (RawSPUMem[(addr - RAW_SPU_BASE_ADDR) / RAW_SPU_OFFSET] && if (RawSPUMem[(addr - RAW_SPU_BASE_ADDR) / RAW_SPU_OFFSET] &&
RawSPUMem[(addr - RAW_SPU_BASE_ADDR) / RAW_SPU_OFFSET]->Read32(addr, &res)) ((RawSPUThread*)RawSPUMem[(addr - RAW_SPU_BASE_ADDR) / RAW_SPU_OFFSET])->Read32(addr, &res))
{ {
return res; return res;
} }
@ -365,218 +366,6 @@ bool MemoryBlock::IsMyAddress(const u64 addr)
return mem && addr >= GetStartAddr() && addr < GetEndAddr(); return mem && addr >= GetStartAddr() && addr < GetEndAddr();
} }
template <typename T>
__forceinline const T MemoryBlock::FastRead(const u64 addr) const
{
volatile const T data = *(const T *)GetMem(addr);
return re(data);
}
template <>
__forceinline const u128 MemoryBlock::FastRead<u128>(const u64 addr) const
{
volatile const u128 data = *(const u128 *)GetMem(addr);
u128 ret;
ret.lo = re(data.hi);
ret.hi = re(data.lo);
return ret;
}
bool MemoryBlock::Read8(const u64 addr, u8* value)
{
if(!IsMyAddress(addr))
{
*value = 0;
return false;
}
*value = FastRead<u8>(FixAddr(addr));
return true;
}
bool MemoryBlock::Read16(const u64 addr, u16* value)
{
if(!IsMyAddress(addr))
{
*value = 0;
return false;
}
*value = FastRead<u16>(FixAddr(addr));
return true;
}
bool MemoryBlock::Read32(const u64 addr, u32* value)
{
if(!IsMyAddress(addr))
{
*value = 0;
return false;
}
*value = FastRead<u32>(FixAddr(addr));
return true;
}
bool MemoryBlock::Read64(const u64 addr, u64* value)
{
if(!IsMyAddress(addr))
{
*value = 0;
return false;
}
*value = FastRead<u64>(FixAddr(addr));
return true;
}
bool MemoryBlock::Read128(const u64 addr, u128* value)
{
if(!IsMyAddress(addr))
{
*value = u128::From32(0);
return false;
}
*value = FastRead<u128>(FixAddr(addr));
return true;
}
template <typename T>
__forceinline void MemoryBlock::FastWrite(const u64 addr, const T value)
{
*(T *)GetMem(addr) = re(value);
}
template <>
__forceinline void MemoryBlock::FastWrite<u128>(const u64 addr, const u128 value)
{
u128 res;
res.lo = re(value.hi);
res.hi = re(value.lo);
*(u128*)GetMem(addr) = res;
}
bool MemoryBlock::Write8(const u64 addr, const u8 value)
{
if(!IsMyAddress(addr) || IsLocked(addr)) return false;
FastWrite<u8>(FixAddr(addr), value);
return true;
}
bool MemoryBlock::Write16(const u64 addr, const u16 value)
{
if(!IsMyAddress(addr) || IsLocked(addr)) return false;
FastWrite<u16>(FixAddr(addr), value);
return true;
}
bool MemoryBlock::Write32(const u64 addr, const u32 value)
{
if(!IsMyAddress(addr) || IsLocked(addr)) return false;
FastWrite<u32>(FixAddr(addr), value);
return true;
}
bool MemoryBlock::Write64(const u64 addr, const u64 value)
{
if(!IsMyAddress(addr) || IsLocked(addr)) return false;
FastWrite<u64>(FixAddr(addr), value);
return true;
}
bool MemoryBlock::Write128(const u64 addr, const u128 value)
{
if(!IsMyAddress(addr) || IsLocked(addr)) return false;
FastWrite<u128>(FixAddr(addr), value);
return true;
}
bool MemoryBlockLE::Read8(const u64 addr, u8* value)
{
if(!IsMyAddress(addr)) return false;
*value = *(u8*)GetMem(FixAddr(addr));
return true;
}
bool MemoryBlockLE::Read16(const u64 addr, u16* value)
{
if(!IsMyAddress(addr)) return false;
*value = *(u16*)GetMem(FixAddr(addr));
return true;
}
bool MemoryBlockLE::Read32(const u64 addr, u32* value)
{
if(!IsMyAddress(addr)) return false;
*value = *(u32*)GetMem(FixAddr(addr));
return true;
}
bool MemoryBlockLE::Read64(const u64 addr, u64* value)
{
if(!IsMyAddress(addr)) return false;
*value = *(u64*)GetMem(FixAddr(addr));
return true;
}
bool MemoryBlockLE::Read128(const u64 addr, u128* value)
{
if(!IsMyAddress(addr)) return false;
*value = *(u128*)GetMem(FixAddr(addr));
return true;
}
bool MemoryBlockLE::Write8(const u64 addr, const u8 value)
{
if(!IsMyAddress(addr)) return false;
*(u8*)GetMem(FixAddr(addr)) = value;
return true;
}
bool MemoryBlockLE::Write16(const u64 addr, const u16 value)
{
if(!IsMyAddress(addr)) return false;
*(u16*)GetMem(FixAddr(addr)) = value;
return true;
}
bool MemoryBlockLE::Write32(const u64 addr, const u32 value)
{
if(!IsMyAddress(addr)) return false;
*(u32*)GetMem(FixAddr(addr)) = value;
return true;
}
bool MemoryBlockLE::Write64(const u64 addr, const u64 value)
{
if(!IsMyAddress(addr)) return false;
*(u64*)GetMem(FixAddr(addr)) = value;
return true;
}
bool MemoryBlockLE::Write128(const u64 addr, const u128 value)
{
if(!IsMyAddress(addr)) return false;
*(u128*)GetMem(FixAddr(addr)) = value;
return true;
}
VirtualMemoryBlock::VirtualMemoryBlock() : MemoryBlock(), m_reserve_size(0) VirtualMemoryBlock::VirtualMemoryBlock() : MemoryBlock(), m_reserve_size(0)
{ {
} }

8
rpcs3/Emu/Memory/Memory.h
View file

@ -125,9 +125,9 @@ public:
{ {
const u64 res = (u64)addr - (u64)GetBaseAddr(); const u64 res = (u64)addr - (u64)GetBaseAddr();
if (res < 0x100000000) if ((u32)res == res)
{ {
return res; return (u32)res;
} }
else else
{ {
@ -211,7 +211,7 @@ public:
} }
else else
{ {
WriteMMIO32(addr, data); WriteMMIO32((u32)addr, data);
} }
} }
else else
@ -285,7 +285,7 @@ public:
} }
else else
{ {
return ReadMMIO32(addr); return ReadMMIO32((u32)addr);
} }
} }
else else

51
rpcs3/Emu/Memory/MemoryBlock.h
View file

@ -78,7 +78,7 @@ class MemoryBlock
protected: protected:
u8* mem; u8* mem;
u64 range_start; u64 range_start;
u64 range_size; u32 range_size;
public: public:
MemoryBlock(); MemoryBlock();
@ -102,24 +102,6 @@ public:
virtual bool IsMyAddress(const u64 addr); virtual bool IsMyAddress(const u64 addr);
virtual bool IsLocked(const u64 addr) { return false; } virtual bool IsLocked(const u64 addr) { return false; }
template <typename T>
__forceinline const T FastRead(const u64 addr) const;
virtual bool Read8(const u64 addr, u8* value);
virtual bool Read16(const u64 addr, u16* value);
virtual bool Read32(const u64 addr, u32* value);
virtual bool Read64(const u64 addr, u64* value);
virtual bool Read128(const u64 addr, u128* value);
template <typename T>
__forceinline void FastWrite(const u64 addr, const T value);
virtual bool Write8(const u64 addr, const u8 value);
virtual bool Write16(const u64 addr, const u16 value);
virtual bool Write32(const u64 addr, const u32 value);
virtual bool Write64(const u64 addr, const u64 value);
virtual bool Write128(const u64 addr, const u128 value);
const u64 GetStartAddr() const { return range_start; } const u64 GetStartAddr() const { return range_start; }
const u64 GetEndAddr() const { return GetStartAddr() + GetSize() - 1; } const u64 GetEndAddr() const { return GetStartAddr() + GetSize() - 1; }
virtual const u32 GetSize() const { return range_size; } virtual const u32 GetSize() const { return range_size; }
@ -137,18 +119,7 @@ public:
class MemoryBlockLE : public MemoryBlock class MemoryBlockLE : public MemoryBlock
{ {
public:
virtual bool Read8(const u64 addr, u8* value) override;
virtual bool Read16(const u64 addr, u16* value) override;
virtual bool Read32(const u64 addr, u32* value) override;
virtual bool Read64(const u64 addr, u64* value) override;
virtual bool Read128(const u64 addr, u128* value) override;
virtual bool Write8(const u64 addr, const u8 value) override;
virtual bool Write16(const u64 addr, const u16 value) override;
virtual bool Write32(const u64 addr, const u32 value) override;
virtual bool Write64(const u64 addr, const u64 value) override;
virtual bool Write128(const u64 addr, const u128 value) override;
}; };
class MemoryMirror : public MemoryBlock class MemoryMirror : public MemoryBlock
@ -244,17 +215,17 @@ public:
// Return the total amount of reserved memory // Return the total amount of reserved memory
virtual u32 GetReservedAmount(); virtual u32 GetReservedAmount();
virtual bool Read8(const u64 addr, u8* value); bool Read8(const u64 addr, u8* value);
virtual bool Read16(const u64 addr, u16* value); bool Read16(const u64 addr, u16* value);
virtual bool Read32(const u64 addr, u32* value); bool Read32(const u64 addr, u32* value);
virtual bool Read64(const u64 addr, u64* value); bool Read64(const u64 addr, u64* value);
virtual bool Read128(const u64 addr, u128* value); bool Read128(const u64 addr, u128* value);
virtual bool Write8(const u64 addr, const u8 value); bool Write8(const u64 addr, const u8 value);
virtual bool Write16(const u64 addr, const u16 value); bool Write16(const u64 addr, const u16 value);
virtual bool Write32(const u64 addr, const u32 value); bool Write32(const u64 addr, const u32 value);
virtual bool Write64(const u64 addr, const u64 value); bool Write64(const u64 addr, const u64 value);
virtual bool Write128(const u64 addr, const u128 value); bool Write128(const u64 addr, const u128 value);
// try to get the real address given a mapped address // try to get the real address given a mapped address
// return true for success // return true for success