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rsx: Restructure programs
- Also re-enable pipeline optimizations
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b0a6b72ce8
commit
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21 changed files with 777 additions and 439 deletions
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@ -584,18 +584,48 @@ namespace rsx
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rsx->m_graphics_state |= rsx::pipeline_state::fragment_program_dirty;
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}
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void set_surface_dirty_bit(thread* rsx, u32, u32)
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void set_surface_dirty_bit(thread* rsx, u32 reg, u32 arg)
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{
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if (reg == NV4097_SET_SURFACE_CLIP_VERTICAL ||
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reg == NV4097_SET_SURFACE_CLIP_HORIZONTAL)
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{
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if (arg != method_registers.register_previous_value)
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{
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rsx->m_graphics_state |= rsx::pipeline_state::vertex_state_dirty;
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}
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}
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rsx->m_rtts_dirty = true;
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rsx->m_framebuffer_state_contested = false;
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}
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void set_surface_format(thread* rsx, u32 reg, u32 arg)
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{
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// Special consideration - antialiasing control can affect ROP state
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const auto aa_mask = (0xF << 12);
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if ((arg & aa_mask) != (method_registers.register_previous_value & aa_mask))
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{
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// Antialias control has changed, update ROP parameters
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rsx->m_graphics_state |= rsx::pipeline_state::fragment_state_dirty;
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}
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set_surface_dirty_bit(rsx, reg, arg);
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}
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void set_surface_options_dirty_bit(thread* rsx, u32, u32)
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{
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if (rsx->m_framebuffer_state_contested)
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rsx->m_rtts_dirty = true;
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}
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void set_ROP_state_dirty_bit(thread* rsx, u32, u32 arg)
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{
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if (arg != method_registers.register_previous_value)
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{
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rsx->m_graphics_state |= rsx::fragment_state_dirty;
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}
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}
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void set_vertex_base_offset(thread* rsx, u32 reg, u32 arg)
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{
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if (rsx->in_begin_end)
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@ -620,6 +650,22 @@ namespace rsx
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}
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}
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void set_vertex_env_dirty_bit(thread* rsx, u32 reg, u32 arg)
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{
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if (arg != method_registers.register_previous_value)
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{
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rsx->m_graphics_state |= rsx::pipeline_state::vertex_state_dirty;
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}
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}
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void set_fragment_env_dirty_bit(thread* rsx, u32 reg, u32 arg)
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{
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if (arg != method_registers.register_previous_value)
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{
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rsx->m_graphics_state |= rsx::pipeline_state::fragment_state_dirty;
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}
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}
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template<u32 index>
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struct set_texture_dirty_bit
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{
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@ -647,6 +693,18 @@ namespace rsx
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}
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}
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};
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template<u32 index>
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struct set_viewport_dirty_bit
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{
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static void impl(thread* rsx, u32 _reg, u32 arg)
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{
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if (arg != method_registers.register_previous_value)
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{
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rsx->m_graphics_state |= rsx::pipeline_state::vertex_state_dirty;
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}
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}
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};
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}
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namespace nv308a
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@ -2619,7 +2677,7 @@ namespace rsx
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bind<NV4097_SET_CONTEXT_DMA_COLOR_C, nv4097::set_surface_dirty_bit>();
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bind<NV4097_SET_CONTEXT_DMA_COLOR_D, nv4097::set_surface_dirty_bit>();
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bind<NV4097_SET_CONTEXT_DMA_ZETA, nv4097::set_surface_dirty_bit>();
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bind<NV4097_SET_SURFACE_FORMAT, nv4097::set_surface_dirty_bit>();
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bind<NV4097_SET_SURFACE_FORMAT, nv4097::set_surface_format>();
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bind<NV4097_SET_SURFACE_PITCH_A, nv4097::set_surface_dirty_bit>();
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bind<NV4097_SET_SURFACE_PITCH_B, nv4097::set_surface_dirty_bit>();
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bind<NV4097_SET_SURFACE_PITCH_C, nv4097::set_surface_dirty_bit>();
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@ -2660,6 +2718,20 @@ namespace rsx
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bind<NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK, nv4097::set_vertex_attribute_output_mask>();
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bind<NV4097_SET_VERTEX_DATA_BASE_OFFSET, nv4097::set_vertex_base_offset>();
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bind<NV4097_SET_VERTEX_DATA_BASE_INDEX, nv4097::set_index_base_offset>();
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bind<NV4097_SET_USER_CLIP_PLANE_CONTROL, nv4097::set_vertex_env_dirty_bit>();
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bind<NV4097_SET_TRANSFORM_BRANCH_BITS, nv4097::set_vertex_env_dirty_bit>();
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bind<NV4097_SET_CLIP_MIN, nv4097::set_vertex_env_dirty_bit>();
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bind<NV4097_SET_CLIP_MAX, nv4097::set_vertex_env_dirty_bit>();
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bind<NV4097_SET_ALPHA_FUNC, nv4097::set_ROP_state_dirty_bit>();
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bind<NV4097_SET_ALPHA_REF, nv4097::set_ROP_state_dirty_bit>();
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bind<NV4097_SET_ALPHA_TEST_ENABLE, nv4097::set_ROP_state_dirty_bit>();
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bind<NV4097_SET_ANTI_ALIASING_CONTROL, nv4097::set_ROP_state_dirty_bit>();
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bind<NV4097_SET_SHADER_PACKER, nv4097::set_ROP_state_dirty_bit>();
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bind<NV4097_SET_SHADER_WINDOW, nv4097::set_ROP_state_dirty_bit>();
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bind<NV4097_SET_FOG_MODE, nv4097::set_ROP_state_dirty_bit>();
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bind_array<NV4097_SET_FOG_PARAMS, 1, 2, nv4097::set_ROP_state_dirty_bit>();
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bind_range<NV4097_SET_VIEWPORT_SCALE, 1, 3, nv4097::set_viewport_dirty_bit>();
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bind_range<NV4097_SET_VIEWPORT_OFFSET, 1, 3, nv4097::set_viewport_dirty_bit>();
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//NV308A
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bind_range<NV308A_COLOR, 1, 256, nv308a::color>();
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