archive/rpcs3
1
0
Fork 0
mirror of https://github.com/RPCS3/rpcs3.git synced 2025-07-07 15:31:26 +12:00
Code Issues Projects Releases Packages Wiki Activity Actions

SPU: fix minor UB in STQD/LQD instructions

Browse source
This commit is contained in:
Nekotekina 2019-05-02 17:59:15 +03:00
parent 2b4da18709
commit 15bd3b8724
2 changed files with 4 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

4
rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp
View file

@ -4359,7 +4359,7 @@ void spu_recompiler::AHI(spu_opcode_t op)
void spu_recompiler::STQD(spu_opcode_t op) void spu_recompiler::STQD(spu_opcode_t op)
{ {
c->mov(*addr, SPU_OFF_32(gpr, op.ra, &v128::_u32, 3)); c->mov(*addr, SPU_OFF_32(gpr, op.ra, &v128::_u32, 3));
if (op.si10) c->add(*addr, op.si10 << 4); if (op.si10) c->add(*addr, op.si10 * 16);
c->and_(*addr, 0x3fff0); c->and_(*addr, 0x3fff0);
if (utils::has_ssse3()) if (utils::has_ssse3())
@ -4382,7 +4382,7 @@ void spu_recompiler::STQD(spu_opcode_t op)
void spu_recompiler::LQD(spu_opcode_t op) void spu_recompiler::LQD(spu_opcode_t op)
{ {
c->mov(*addr, SPU_OFF_32(gpr, op.ra, &v128::_u32, 3)); c->mov(*addr, SPU_OFF_32(gpr, op.ra, &v128::_u32, 3));
if (op.si10) c->add(*addr, op.si10 << 4); if (op.si10) c->add(*addr, op.si10 * 16);
c->and_(*addr, 0x3fff0); c->and_(*addr, 0x3fff0);
if (utils::has_ssse3()) if (utils::has_ssse3())

4
rpcs3/Emu/Cell/SPUInterpreter.cpp
View file

@ -1516,13 +1516,13 @@ bool spu_interpreter::AHI(spu_thread& spu, spu_opcode_t op)
bool spu_interpreter::STQD(spu_thread& spu, spu_opcode_t op) bool spu_interpreter::STQD(spu_thread& spu, spu_opcode_t op)
{ {
spu._ref<v128>((spu.gpr[op.ra]._s32[3] + (op.si10 << 4)) & 0x3fff0) = spu.gpr[op.rt]; spu._ref<v128>((spu.gpr[op.ra]._s32[3] + (op.si10 * 16)) & 0x3fff0) = spu.gpr[op.rt];
return true; return true;
} }
bool spu_interpreter::LQD(spu_thread& spu, spu_opcode_t op) bool spu_interpreter::LQD(spu_thread& spu, spu_opcode_t op)
{ {
spu.gpr[op.rt] = spu._ref<v128>((spu.gpr[op.ra]._s32[3] + (op.si10 << 4)) & 0x3fff0); spu.gpr[op.rt] = spu._ref<v128>((spu.gpr[op.ra]._s32[3] + (op.si10 * 16)) & 0x3fff0);
return true; return true;
} }