mirror of
https://github.com/RPCS3/rpcs3.git
synced 2025-07-06 06:51:26 +12:00
Implemented ANDC and also added support for TB and TBH in MFSPR
This commit is contained in:
parent
e8582c8655
commit
13acb06d1a
2 changed files with 20 additions and 2 deletions
|
@ -147,7 +147,8 @@ private:
|
||||||
case 0x008: return CPU.LR;
|
case 0x008: return CPU.LR;
|
||||||
case 0x009: return CPU.CTR;
|
case 0x009: return CPU.CTR;
|
||||||
case 0x100: return CPU.USPRG0;
|
case 0x100: return CPU.USPRG0;
|
||||||
case 0x10C: return get_time();
|
case 0x10C: CPU.TB = get_time(); return CPU.TB;
|
||||||
|
case 0x10D: CPU.TB = get_time(); return CPU.TBH;
|
||||||
}
|
}
|
||||||
|
|
||||||
UNK(fmt::Format("ReadSPR error: Unknown SPR 0x%x!", n));
|
UNK(fmt::Format("ReadSPR error: Unknown SPR 0x%x!", n));
|
||||||
|
@ -165,6 +166,7 @@ private:
|
||||||
case 0x009: CPU.CTR = value; return;
|
case 0x009: CPU.CTR = value; return;
|
||||||
case 0x100: CPU.USPRG0 = value; return;
|
case 0x100: CPU.USPRG0 = value; return;
|
||||||
case 0x10C: UNK("WriteSPR: Write to time-based SPR. Report this to a developer!"); return;
|
case 0x10C: UNK("WriteSPR: Write to time-based SPR. Report this to a developer!"); return;
|
||||||
|
case 0x10D: UNK("WriteSPR: Write to time-based SPR upper. Report this to a developer!"); return;
|
||||||
}
|
}
|
||||||
|
|
||||||
UNK(fmt::Format("WriteSPR error: Unknown SPR 0x%x!", n));
|
UNK(fmt::Format("WriteSPR error: Unknown SPR 0x%x!", n));
|
||||||
|
|
|
@ -2325,7 +2325,16 @@ void Compiler::CNTLZD(u32 ra, u32 rs, bool rc) {
|
||||||
}
|
}
|
||||||
|
|
||||||
void Compiler::ANDC(u32 ra, u32 rs, u32 rb, bool rc) {
|
void Compiler::ANDC(u32 ra, u32 rs, u32 rb, bool rc) {
|
||||||
InterpreterCall("ANDC", &PPUInterpreter::ANDC, ra, rs, rb, rc);
|
auto rs_i64 = GetGpr(rs);
|
||||||
|
auto rb_i64 = GetGpr(rb);
|
||||||
|
rb_i64 = m_ir_builder->CreateNot(rb_i64);
|
||||||
|
auto res_i64 = m_ir_builder->CreateAnd(rs_i64, rb_i64);
|
||||||
|
SetGpr(ra, res_i64);
|
||||||
|
|
||||||
|
if (rc) {
|
||||||
|
SetCrFieldSignedCmp(0, res_i64, m_ir_builder->getInt64(0));
|
||||||
|
}
|
||||||
|
//InterpreterCall("ANDC", &PPUInterpreter::ANDC, ra, rs, rb, rc);
|
||||||
}
|
}
|
||||||
|
|
||||||
void Compiler::TD(u32 to, u32 ra, u32 rb) {
|
void Compiler::TD(u32 to, u32 ra, u32 rb) {
|
||||||
|
@ -2784,6 +2793,13 @@ void Compiler::MFSPR(u32 rd, u32 spr) {
|
||||||
case 0x100:
|
case 0x100:
|
||||||
rd_i64 = GetUsprg0();
|
rd_i64 = GetUsprg0();
|
||||||
break;
|
break;
|
||||||
|
case 0x10C:
|
||||||
|
rd_i64 = Call<u64>("get_time", get_time);
|
||||||
|
break;
|
||||||
|
case 0x10D:
|
||||||
|
rd_i64 = Call<u64>("get_time", get_time);
|
||||||
|
rd_i64 = m_ir_builder->CreateLShr(rd_i64, 32);
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
assert(0);
|
assert(0);
|
||||||
break;
|
break;
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue