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Implement the SRR0 register.

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This commit is contained in:
Andrew Church 2015-01-19 03:18:03 +09:00
parent a87de1b565
commit 03b059c1d5
2 changed files with 10 additions and 1 deletions
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8
rpcs3/Emu/Cell/SPUThread.cpp
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@ -558,6 +558,8 @@ u32 SPUThread::GetChannelCount(u32 ch)
switch (ch) switch (ch)
{ {
case SPU_WrSRR0: res = 1; break;
case SPU_RdSRR0: res = 1; break;
case SPU_WrOutMbox: res = SPU.Out_MBox.GetFreeCount(); break; case SPU_WrOutMbox: res = SPU.Out_MBox.GetFreeCount(); break;
case SPU_WrOutIntrMbox: res = SPU.Out_IntrMBox.GetFreeCount(); break; case SPU_WrOutIntrMbox: res = SPU.Out_IntrMBox.GetFreeCount(); break;
case SPU_RdInMbox: res = SPU.In_MBox.GetCount(); break; case SPU_RdInMbox: res = SPU.In_MBox.GetCount(); break;
@ -589,6 +591,9 @@ void SPUThread::WriteChannel(u32 ch, const u128& r)
switch (ch) switch (ch)
{ {
case SPU_WrSRR0:
SRR0 = v & 0x3FFFC; //LSLR & ~3
break;
case SPU_WrOutIntrMbox: case SPU_WrOutIntrMbox:
{ {
if (!group) // if RawSPU if (!group) // if RawSPU
@ -910,6 +915,9 @@ void SPUThread::ReadChannel(u128& r, u32 ch)
switch (ch) switch (ch)
{ {
case SPU_RdSRR0:
v = SRR0;
break;
case SPU_RdInMbox: case SPU_RdInMbox:
{ {
while (!SPU.In_MBox.Pop(v) && !Emu.IsStopped()) while (!SPU.In_MBox.Pop(v) && !Emu.IsStopped())

1
rpcs3/Emu/Cell/SPUThread.h
View file

@ -276,6 +276,7 @@ class SPUThread : public PPCThread
public: public:
u128 GPR[128]; // General-Purpose Registers u128 GPR[128]; // General-Purpose Registers
SPU_FPSCR FPSCR; SPU_FPSCR FPSCR;
u32 SRR0;
SPU_SNRConfig_hdr cfg; // Signal Notification Registers Configuration (OR-mode enabled: 0x1 for SNR1, 0x2 for SNR2) SPU_SNRConfig_hdr cfg; // Signal Notification Registers Configuration (OR-mode enabled: 0x1 for SNR1, 0x2 for SNR2)
u64 R_ADDR; // reservation address u64 R_ADDR; // reservation address