mirror of
https://github.com/cemu-project/Cemu.git
synced 2025-07-03 13:31:18 +12:00
7db2b77983
All of the changes are verified against real hardware, except for the byte string instructions
78 lines
1.9 KiB
C++
78 lines
1.9 KiB
C++
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static void PPCInterpreter_MFSPR(PPCInterpreter_t* hCPU, uint32 opcode)
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{
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uint32 rD, spr1, spr2, spr;
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PPC_OPC_TEMPL_XO(opcode, rD, spr1, spr2);
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spr = spr1 | (spr2 << 5);
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// copy SPR
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hCPU->gpr[rD] = PPCSpr_get(hCPU, spr);
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// next instruction
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PPCInterpreter_nextInstruction(hCPU);
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}
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static void PPCInterpreter_MTSPR(PPCInterpreter_t* hCPU, uint32 opcode)
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{
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uint32 rD, spr1, spr2, spr;
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PPC_OPC_TEMPL_XO(opcode, rD, spr1, spr2);
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spr = spr1 | (spr2 << 5);
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PPCSpr_set(hCPU, spr, hCPU->gpr[rD]);
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// next instruction
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PPCInterpreter_nextInstruction(hCPU);
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}
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static void PPCInterpreter_MFSR(PPCInterpreter_t* hCPU, uint32 opcode)
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{
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uint32 rD, SR, rB;
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PPC_OPC_TEMPL_X(opcode, rD, SR, rB);
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hCPU->gpr[rD] = getSR(hCPU, SR & 0xF);
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// next instruction
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PPCInterpreter_nextInstruction(hCPU);
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}
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static void PPCInterpreter_MTSR(PPCInterpreter_t* hCPU, uint32 opcode)
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{
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uint32 rS, SR, rB;
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PPC_OPC_TEMPL_X(opcode, rS, SR, rB);
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setSR(hCPU, SR&0xF, hCPU->gpr[rS]);
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// next instruction
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PPCInterpreter_nextInstruction(hCPU);
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}
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static void PPCInterpreter_MFTB(PPCInterpreter_t* hCPU, uint32 opcode)
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{
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uint32 rD, spr1, spr2, spr;
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// get SPR ID
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PPC_OPC_TEMPL_XO(opcode, rD, spr1, spr2);
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spr = spr1 | (spr2 << 5);
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// get core cycle counter
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uint64 coreTime = ppcItpCtrl::getTB(hCPU);
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switch (spr)
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{
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case 268: // TBL
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hCPU->gpr[rD] = (uint32)(coreTime & 0xFFFFFFFF);
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break;
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case 269: // TBU
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hCPU->gpr[rD] = (uint32)((coreTime >> 32) & 0xFFFFFFFF);
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break;
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default:
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assert_dbg();
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}
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// next instruction
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PPCInterpreter_nextInstruction(hCPU);
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}
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static void PPCInterpreter_TW(PPCInterpreter_t* hCPU, uint32 opcode)
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{
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sint32 to, rA, rB;
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PPC_OPC_TEMPL_X(opcode, to, rA, rB);
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cemu_assert_debug(to == 0);
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if(to != 0)
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PPCInterpreter_nextInstruction(hCPU);
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if (rA == DEBUGGER_BP_T_DEBUGGER)
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debugger_enterTW(hCPU);
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else if (rA == DEBUGGER_BP_T_GDBSTUB)
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g_gdbstub->HandleTrapInstruction(hCPU);
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}
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