mirror of
https://github.com/cemu-project/Cemu.git
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846 lines
29 KiB
C++
846 lines
29 KiB
C++
#include "IMLInstruction.h"
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#include "IML.h"
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#include "../PPCRecompiler.h"
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#include "../PPCRecompilerIml.h"
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void IMLInstruction::CheckRegisterUsage(IMLUsedRegisters* registersUsed) const
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{
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registersUsed->readNamedReg1 = -1;
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registersUsed->readNamedReg2 = -1;
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registersUsed->readNamedReg3 = -1;
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registersUsed->writtenNamedReg1 = -1;
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registersUsed->readFPR1 = -1;
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registersUsed->readFPR2 = -1;
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registersUsed->readFPR3 = -1;
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registersUsed->readFPR4 = -1;
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registersUsed->writtenFPR1 = -1;
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if (type == PPCREC_IML_TYPE_R_NAME)
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{
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registersUsed->writtenNamedReg1 = op_r_name.registerIndex;
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}
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else if (type == PPCREC_IML_TYPE_NAME_R)
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{
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registersUsed->readNamedReg1 = op_r_name.registerIndex;
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}
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else if (type == PPCREC_IML_TYPE_R_R)
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{
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if (operation == PPCREC_IML_OP_COMPARE_SIGNED || operation == PPCREC_IML_OP_COMPARE_UNSIGNED || operation == PPCREC_IML_OP_DCBZ)
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{
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// both operands are read only
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registersUsed->readNamedReg1 = op_r_r.registerResult;
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registersUsed->readNamedReg2 = op_r_r.registerA;
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}
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else if (
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operation == PPCREC_IML_OP_OR ||
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operation == PPCREC_IML_OP_AND ||
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operation == PPCREC_IML_OP_XOR ||
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operation == PPCREC_IML_OP_ADD ||
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operation == PPCREC_IML_OP_ADD_CARRY ||
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operation == PPCREC_IML_OP_ADD_CARRY_ME ||
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operation == PPCREC_IML_OP_SUB_CARRY_UPDATE_CARRY)
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{
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// result is read and written, operand is read
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registersUsed->writtenNamedReg1 = op_r_r.registerResult;
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registersUsed->readNamedReg1 = op_r_r.registerResult;
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registersUsed->readNamedReg2 = op_r_r.registerA;
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}
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else if (
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operation == PPCREC_IML_OP_ASSIGN ||
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operation == PPCREC_IML_OP_ENDIAN_SWAP ||
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operation == PPCREC_IML_OP_CNTLZW ||
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operation == PPCREC_IML_OP_NOT ||
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operation == PPCREC_IML_OP_NEG ||
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operation == PPCREC_IML_OP_ASSIGN_S16_TO_S32 ||
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operation == PPCREC_IML_OP_ASSIGN_S8_TO_S32)
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{
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// result is written, operand is read
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registersUsed->writtenNamedReg1 = op_r_r.registerResult;
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registersUsed->readNamedReg1 = op_r_r.registerA;
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}
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else
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cemu_assert_unimplemented();
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}
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else if (type == PPCREC_IML_TYPE_R_S32)
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{
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if (operation == PPCREC_IML_OP_COMPARE_SIGNED || operation == PPCREC_IML_OP_COMPARE_UNSIGNED || operation == PPCREC_IML_OP_MTCRF)
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{
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// operand register is read only
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registersUsed->readNamedReg1 = op_r_immS32.registerIndex;
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}
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else if (operation == PPCREC_IML_OP_ADD ||
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operation == PPCREC_IML_OP_SUB ||
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operation == PPCREC_IML_OP_AND ||
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operation == PPCREC_IML_OP_OR ||
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operation == PPCREC_IML_OP_XOR ||
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operation == PPCREC_IML_OP_LEFT_ROTATE)
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{
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// operand register is read and write
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registersUsed->readNamedReg1 = op_r_immS32.registerIndex;
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registersUsed->writtenNamedReg1 = op_r_immS32.registerIndex;
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}
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else
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{
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// operand register is write only
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// todo - use explicit lists, avoid default cases
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registersUsed->writtenNamedReg1 = op_r_immS32.registerIndex;
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}
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}
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else if (type == PPCREC_IML_TYPE_CONDITIONAL_R_S32)
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{
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if (operation == PPCREC_IML_OP_ASSIGN)
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{
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// result is written, but also considered read (in case the condition fails)
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registersUsed->readNamedReg1 = op_conditional_r_s32.registerIndex;
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registersUsed->writtenNamedReg1 = op_conditional_r_s32.registerIndex;
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}
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else
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cemu_assert_unimplemented();
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}
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else if (type == PPCREC_IML_TYPE_R_R_S32)
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{
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if (operation == PPCREC_IML_OP_RLWIMI)
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{
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// result and operand register are both read, result is written
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registersUsed->writtenNamedReg1 = op_r_r_s32.registerResult;
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registersUsed->readNamedReg1 = op_r_r_s32.registerResult;
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registersUsed->readNamedReg2 = op_r_r_s32.registerA;
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}
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else
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{
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// result is write only and operand is read only
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registersUsed->writtenNamedReg1 = op_r_r_s32.registerResult;
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registersUsed->readNamedReg1 = op_r_r_s32.registerA;
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}
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}
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else if (type == PPCREC_IML_TYPE_R_R_R)
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{
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// in all cases result is written and other operands are read only
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registersUsed->writtenNamedReg1 = op_r_r_r.registerResult;
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registersUsed->readNamedReg1 = op_r_r_r.registerA;
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registersUsed->readNamedReg2 = op_r_r_r.registerB;
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}
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else if (type == PPCREC_IML_TYPE_CJUMP || type == PPCREC_IML_TYPE_CJUMP_CYCLE_CHECK)
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{
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// no effect on registers
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}
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else if (type == PPCREC_IML_TYPE_NO_OP)
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{
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// no effect on registers
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}
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else if (type == PPCREC_IML_TYPE_MACRO)
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{
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if (operation == PPCREC_IML_MACRO_BL || operation == PPCREC_IML_MACRO_B_FAR || operation == PPCREC_IML_MACRO_BLR || operation == PPCREC_IML_MACRO_BLRL || operation == PPCREC_IML_MACRO_BCTR || operation == PPCREC_IML_MACRO_BCTRL || operation == PPCREC_IML_MACRO_LEAVE || operation == PPCREC_IML_MACRO_DEBUGBREAK || operation == PPCREC_IML_MACRO_COUNT_CYCLES || operation == PPCREC_IML_MACRO_HLE || operation == PPCREC_IML_MACRO_MFTB)
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{
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// no effect on registers
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}
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else
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cemu_assert_unimplemented();
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}
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else if (type == PPCREC_IML_TYPE_LOAD)
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{
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registersUsed->writtenNamedReg1 = op_storeLoad.registerData;
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if (op_storeLoad.registerMem != PPC_REC_INVALID_REGISTER)
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registersUsed->readNamedReg1 = op_storeLoad.registerMem;
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}
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else if (type == PPCREC_IML_TYPE_LOAD_INDEXED)
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{
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registersUsed->writtenNamedReg1 = op_storeLoad.registerData;
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if (op_storeLoad.registerMem != PPC_REC_INVALID_REGISTER)
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registersUsed->readNamedReg1 = op_storeLoad.registerMem;
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if (op_storeLoad.registerMem2 != PPC_REC_INVALID_REGISTER)
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registersUsed->readNamedReg2 = op_storeLoad.registerMem2;
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}
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else if (type == PPCREC_IML_TYPE_STORE)
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{
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registersUsed->readNamedReg1 = op_storeLoad.registerData;
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if (op_storeLoad.registerMem != PPC_REC_INVALID_REGISTER)
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registersUsed->readNamedReg2 = op_storeLoad.registerMem;
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}
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else if (type == PPCREC_IML_TYPE_STORE_INDEXED)
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{
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registersUsed->readNamedReg1 = op_storeLoad.registerData;
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if (op_storeLoad.registerMem != PPC_REC_INVALID_REGISTER)
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registersUsed->readNamedReg2 = op_storeLoad.registerMem;
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if (op_storeLoad.registerMem2 != PPC_REC_INVALID_REGISTER)
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registersUsed->readNamedReg3 = op_storeLoad.registerMem2;
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}
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else if (type == PPCREC_IML_TYPE_CR)
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{
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// only affects cr register
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}
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else if (type == PPCREC_IML_TYPE_JUMPMARK)
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{
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// no effect on registers
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}
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else if (type == PPCREC_IML_TYPE_PPC_ENTER)
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{
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// no op
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}
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else if (type == PPCREC_IML_TYPE_FPR_R_NAME)
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{
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// fpr operation
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registersUsed->writtenFPR1 = op_r_name.registerIndex;
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}
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else if (type == PPCREC_IML_TYPE_FPR_NAME_R)
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{
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// fpr operation
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registersUsed->readFPR1 = op_r_name.registerIndex;
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}
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else if (type == PPCREC_IML_TYPE_FPR_LOAD)
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{
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// fpr load operation
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registersUsed->writtenFPR1 = op_storeLoad.registerData;
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// address is in gpr register
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if (op_storeLoad.registerMem != PPC_REC_INVALID_REGISTER)
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registersUsed->readNamedReg1 = op_storeLoad.registerMem;
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// determine partially written result
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switch (op_storeLoad.mode)
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{
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case PPCREC_FPR_LD_MODE_PSQ_GENERIC_PS0:
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case PPCREC_FPR_LD_MODE_PSQ_GENERIC_PS0_PS1:
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cemu_assert_debug(op_storeLoad.registerGQR != PPC_REC_INVALID_REGISTER);
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registersUsed->readNamedReg2 = op_storeLoad.registerGQR;
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break;
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case PPCREC_FPR_LD_MODE_DOUBLE_INTO_PS0:
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// PS1 remains the same
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registersUsed->readFPR4 = op_storeLoad.registerData;
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break;
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case PPCREC_FPR_LD_MODE_SINGLE_INTO_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_FLOAT_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_FLOAT_PS0:
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case PPCREC_FPR_LD_MODE_PSQ_S16_PS0:
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case PPCREC_FPR_LD_MODE_PSQ_S16_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_U16_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_U16_PS0:
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case PPCREC_FPR_LD_MODE_PSQ_S8_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_U8_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_U8_PS0:
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case PPCREC_FPR_LD_MODE_PSQ_S8_PS0:
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break;
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default:
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cemu_assert_unimplemented();
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}
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}
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else if (type == PPCREC_IML_TYPE_FPR_LOAD_INDEXED)
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{
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// fpr load operation
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registersUsed->writtenFPR1 = op_storeLoad.registerData;
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// address is in gpr registers
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if (op_storeLoad.registerMem != PPC_REC_INVALID_REGISTER)
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registersUsed->readNamedReg1 = op_storeLoad.registerMem;
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if (op_storeLoad.registerMem2 != PPC_REC_INVALID_REGISTER)
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registersUsed->readNamedReg2 = op_storeLoad.registerMem2;
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// determine partially written result
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switch (op_storeLoad.mode)
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{
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case PPCREC_FPR_LD_MODE_PSQ_GENERIC_PS0:
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case PPCREC_FPR_LD_MODE_PSQ_GENERIC_PS0_PS1:
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cemu_assert_debug(op_storeLoad.registerGQR != PPC_REC_INVALID_REGISTER);
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registersUsed->readNamedReg3 = op_storeLoad.registerGQR;
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break;
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case PPCREC_FPR_LD_MODE_DOUBLE_INTO_PS0:
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// PS1 remains the same
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registersUsed->readFPR4 = op_storeLoad.registerData;
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break;
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case PPCREC_FPR_LD_MODE_SINGLE_INTO_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_FLOAT_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_FLOAT_PS0:
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case PPCREC_FPR_LD_MODE_PSQ_S16_PS0:
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case PPCREC_FPR_LD_MODE_PSQ_S16_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_U16_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_U16_PS0:
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case PPCREC_FPR_LD_MODE_PSQ_S8_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_U8_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_U8_PS0:
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break;
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default:
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cemu_assert_unimplemented();
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}
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}
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else if (type == PPCREC_IML_TYPE_FPR_STORE)
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{
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// fpr store operation
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registersUsed->readFPR1 = op_storeLoad.registerData;
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if (op_storeLoad.registerMem != PPC_REC_INVALID_REGISTER)
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registersUsed->readNamedReg1 = op_storeLoad.registerMem;
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// PSQ generic stores also access GQR
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switch (op_storeLoad.mode)
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{
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case PPCREC_FPR_ST_MODE_PSQ_GENERIC_PS0:
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case PPCREC_FPR_ST_MODE_PSQ_GENERIC_PS0_PS1:
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cemu_assert_debug(op_storeLoad.registerGQR != PPC_REC_INVALID_REGISTER);
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registersUsed->readNamedReg2 = op_storeLoad.registerGQR;
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break;
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default:
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break;
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}
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}
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else if (type == PPCREC_IML_TYPE_FPR_STORE_INDEXED)
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{
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// fpr store operation
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registersUsed->readFPR1 = op_storeLoad.registerData;
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// address is in gpr registers
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if (op_storeLoad.registerMem != PPC_REC_INVALID_REGISTER)
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registersUsed->readNamedReg1 = op_storeLoad.registerMem;
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if (op_storeLoad.registerMem2 != PPC_REC_INVALID_REGISTER)
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registersUsed->readNamedReg2 = op_storeLoad.registerMem2;
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// PSQ generic stores also access GQR
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switch (op_storeLoad.mode)
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{
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case PPCREC_FPR_ST_MODE_PSQ_GENERIC_PS0:
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case PPCREC_FPR_ST_MODE_PSQ_GENERIC_PS0_PS1:
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cemu_assert_debug(op_storeLoad.registerGQR != PPC_REC_INVALID_REGISTER);
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registersUsed->readNamedReg3 = op_storeLoad.registerGQR;
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break;
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default:
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break;
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}
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}
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else if (type == PPCREC_IML_TYPE_FPR_R_R)
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{
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// fpr operation
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if (operation == PPCREC_IML_OP_FPR_COPY_BOTTOM_TO_BOTTOM_AND_TOP ||
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operation == PPCREC_IML_OP_FPR_COPY_TOP_TO_BOTTOM_AND_TOP ||
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operation == PPCREC_IML_OP_FPR_COPY_BOTTOM_AND_TOP_SWAPPED ||
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operation == PPCREC_IML_OP_ASSIGN ||
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operation == PPCREC_IML_OP_FPR_BOTTOM_FRES_TO_BOTTOM_AND_TOP ||
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operation == PPCREC_IML_OP_FPR_NEGATE_PAIR ||
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operation == PPCREC_IML_OP_FPR_ABS_PAIR ||
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operation == PPCREC_IML_OP_FPR_FRES_PAIR ||
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operation == PPCREC_IML_OP_FPR_FRSQRTE_PAIR)
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{
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// operand read, result written
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registersUsed->readFPR1 = op_fpr_r_r.registerOperand;
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registersUsed->writtenFPR1 = op_fpr_r_r.registerResult;
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}
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else if (
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operation == PPCREC_IML_OP_FPR_COPY_BOTTOM_TO_BOTTOM ||
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operation == PPCREC_IML_OP_FPR_COPY_BOTTOM_TO_TOP ||
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operation == PPCREC_IML_OP_FPR_COPY_TOP_TO_TOP ||
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operation == PPCREC_IML_OP_FPR_COPY_TOP_TO_BOTTOM ||
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operation == PPCREC_IML_OP_FPR_EXPAND_BOTTOM32_TO_BOTTOM64_AND_TOP64 ||
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operation == PPCREC_IML_OP_FPR_BOTTOM_FCTIWZ ||
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operation == PPCREC_IML_OP_FPR_BOTTOM_RECIPROCAL_SQRT
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)
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{
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// operand read, result read and (partially) written
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registersUsed->readFPR1 = op_fpr_r_r.registerOperand;
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registersUsed->readFPR4 = op_fpr_r_r.registerResult;
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registersUsed->writtenFPR1 = op_fpr_r_r.registerResult;
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}
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else if (operation == PPCREC_IML_OP_FPR_MULTIPLY_BOTTOM ||
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operation == PPCREC_IML_OP_FPR_MULTIPLY_PAIR ||
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operation == PPCREC_IML_OP_FPR_DIVIDE_BOTTOM ||
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operation == PPCREC_IML_OP_FPR_DIVIDE_PAIR ||
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operation == PPCREC_IML_OP_FPR_ADD_BOTTOM ||
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operation == PPCREC_IML_OP_FPR_ADD_PAIR ||
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operation == PPCREC_IML_OP_FPR_SUB_PAIR ||
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operation == PPCREC_IML_OP_FPR_SUB_BOTTOM)
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{
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// operand read, result read and written
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registersUsed->readFPR1 = op_fpr_r_r.registerOperand;
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registersUsed->readFPR2 = op_fpr_r_r.registerResult;
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registersUsed->writtenFPR1 = op_fpr_r_r.registerResult;
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}
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else if (operation == PPCREC_IML_OP_FPR_FCMPU_BOTTOM ||
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operation == PPCREC_IML_OP_FPR_FCMPU_TOP ||
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operation == PPCREC_IML_OP_FPR_FCMPO_BOTTOM)
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{
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// operand read, result read
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registersUsed->readFPR1 = op_fpr_r_r.registerOperand;
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registersUsed->readFPR2 = op_fpr_r_r.registerResult;
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}
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else
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cemu_assert_unimplemented();
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}
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else if (type == PPCREC_IML_TYPE_FPR_R_R_R)
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{
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// fpr operation
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registersUsed->readFPR1 = op_fpr_r_r_r.registerOperandA;
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registersUsed->readFPR2 = op_fpr_r_r_r.registerOperandB;
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registersUsed->writtenFPR1 = op_fpr_r_r_r.registerResult;
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// handle partially written result
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switch (operation)
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{
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case PPCREC_IML_OP_FPR_MULTIPLY_BOTTOM:
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case PPCREC_IML_OP_FPR_ADD_BOTTOM:
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case PPCREC_IML_OP_FPR_SUB_BOTTOM:
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registersUsed->readFPR4 = op_fpr_r_r_r.registerResult;
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break;
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case PPCREC_IML_OP_FPR_SUB_PAIR:
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break;
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default:
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cemu_assert_unimplemented();
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}
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}
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else if (type == PPCREC_IML_TYPE_FPR_R_R_R_R)
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{
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// fpr operation
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registersUsed->readFPR1 = op_fpr_r_r_r_r.registerOperandA;
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registersUsed->readFPR2 = op_fpr_r_r_r_r.registerOperandB;
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registersUsed->readFPR3 = op_fpr_r_r_r_r.registerOperandC;
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registersUsed->writtenFPR1 = op_fpr_r_r_r_r.registerResult;
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// handle partially written result
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switch (operation)
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{
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case PPCREC_IML_OP_FPR_SELECT_BOTTOM:
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registersUsed->readFPR4 = op_fpr_r_r_r_r.registerResult;
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break;
|
|
case PPCREC_IML_OP_FPR_SUM0:
|
|
case PPCREC_IML_OP_FPR_SUM1:
|
|
case PPCREC_IML_OP_FPR_SELECT_PAIR:
|
|
break;
|
|
default:
|
|
cemu_assert_unimplemented();
|
|
}
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_R)
|
|
{
|
|
// fpr operation
|
|
if (operation == PPCREC_IML_OP_FPR_NEGATE_BOTTOM ||
|
|
operation == PPCREC_IML_OP_FPR_ABS_BOTTOM ||
|
|
operation == PPCREC_IML_OP_FPR_NEGATIVE_ABS_BOTTOM ||
|
|
operation == PPCREC_IML_OP_FPR_EXPAND_BOTTOM32_TO_BOTTOM64_AND_TOP64 ||
|
|
operation == PPCREC_IML_OP_FPR_ROUND_TO_SINGLE_PRECISION_BOTTOM ||
|
|
operation == PPCREC_IML_OP_FPR_ROUND_TO_SINGLE_PRECISION_PAIR)
|
|
{
|
|
registersUsed->readFPR1 = op_fpr_r.registerResult;
|
|
registersUsed->writtenFPR1 = op_fpr_r.registerResult;
|
|
}
|
|
else
|
|
cemu_assert_unimplemented();
|
|
}
|
|
else
|
|
{
|
|
cemu_assert_unimplemented();
|
|
}
|
|
}
|
|
|
|
#define replaceRegister(__x,__r,__n) (((__x)==(__r))?(__n):(__x))
|
|
|
|
sint32 replaceRegisterMultiple(sint32 reg, sint32 match[4], sint32 replaced[4])
|
|
{
|
|
for (sint32 i = 0; i < 4; i++)
|
|
{
|
|
if (match[i] < 0)
|
|
continue;
|
|
if (reg == match[i])
|
|
{
|
|
return replaced[i];
|
|
}
|
|
}
|
|
return reg;
|
|
}
|
|
|
|
void IMLInstruction::ReplaceGPRRegisterUsageMultiple(sint32 gprRegisterSearched[4], sint32 gprRegisterReplaced[4])
|
|
{
|
|
if (type == PPCREC_IML_TYPE_R_NAME)
|
|
{
|
|
op_r_name.registerIndex = replaceRegisterMultiple(op_r_name.registerIndex, gprRegisterSearched, gprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_NAME_R)
|
|
{
|
|
op_r_name.registerIndex = replaceRegisterMultiple(op_r_name.registerIndex, gprRegisterSearched, gprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_R_R)
|
|
{
|
|
op_r_r.registerResult = replaceRegisterMultiple(op_r_r.registerResult, gprRegisterSearched, gprRegisterReplaced);
|
|
op_r_r.registerA = replaceRegisterMultiple(op_r_r.registerA, gprRegisterSearched, gprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_R_S32)
|
|
{
|
|
op_r_immS32.registerIndex = replaceRegisterMultiple(op_r_immS32.registerIndex, gprRegisterSearched, gprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_CONDITIONAL_R_S32)
|
|
{
|
|
op_conditional_r_s32.registerIndex = replaceRegisterMultiple(op_conditional_r_s32.registerIndex, gprRegisterSearched, gprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_R_R_S32)
|
|
{
|
|
// in all cases result is written and other operand is read only
|
|
op_r_r_s32.registerResult = replaceRegisterMultiple(op_r_r_s32.registerResult, gprRegisterSearched, gprRegisterReplaced);
|
|
op_r_r_s32.registerA = replaceRegisterMultiple(op_r_r_s32.registerA, gprRegisterSearched, gprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_R_R_R)
|
|
{
|
|
// in all cases result is written and other operands are read only
|
|
op_r_r_r.registerResult = replaceRegisterMultiple(op_r_r_r.registerResult, gprRegisterSearched, gprRegisterReplaced);
|
|
op_r_r_r.registerA = replaceRegisterMultiple(op_r_r_r.registerA, gprRegisterSearched, gprRegisterReplaced);
|
|
op_r_r_r.registerB = replaceRegisterMultiple(op_r_r_r.registerB, gprRegisterSearched, gprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_CJUMP || type == PPCREC_IML_TYPE_CJUMP_CYCLE_CHECK)
|
|
{
|
|
// no effect on registers
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_NO_OP)
|
|
{
|
|
// no effect on registers
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_MACRO)
|
|
{
|
|
if (operation == PPCREC_IML_MACRO_BL || operation == PPCREC_IML_MACRO_B_FAR || operation == PPCREC_IML_MACRO_BLR || operation == PPCREC_IML_MACRO_BLRL || operation == PPCREC_IML_MACRO_BCTR || operation == PPCREC_IML_MACRO_BCTRL || operation == PPCREC_IML_MACRO_LEAVE || operation == PPCREC_IML_MACRO_DEBUGBREAK || operation == PPCREC_IML_MACRO_HLE || operation == PPCREC_IML_MACRO_MFTB || operation == PPCREC_IML_MACRO_COUNT_CYCLES)
|
|
{
|
|
// no effect on registers
|
|
}
|
|
else
|
|
{
|
|
cemu_assert_unimplemented();
|
|
}
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_LOAD)
|
|
{
|
|
op_storeLoad.registerData = replaceRegisterMultiple(op_storeLoad.registerData, gprRegisterSearched, gprRegisterReplaced);
|
|
if (op_storeLoad.registerMem != PPC_REC_INVALID_REGISTER)
|
|
{
|
|
op_storeLoad.registerMem = replaceRegisterMultiple(op_storeLoad.registerMem, gprRegisterSearched, gprRegisterReplaced);
|
|
}
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_LOAD_INDEXED)
|
|
{
|
|
op_storeLoad.registerData = replaceRegisterMultiple(op_storeLoad.registerData, gprRegisterSearched, gprRegisterReplaced);
|
|
if (op_storeLoad.registerMem != PPC_REC_INVALID_REGISTER)
|
|
op_storeLoad.registerMem = replaceRegisterMultiple(op_storeLoad.registerMem, gprRegisterSearched, gprRegisterReplaced);
|
|
if (op_storeLoad.registerMem2 != PPC_REC_INVALID_REGISTER)
|
|
op_storeLoad.registerMem2 = replaceRegisterMultiple(op_storeLoad.registerMem2, gprRegisterSearched, gprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_STORE)
|
|
{
|
|
op_storeLoad.registerData = replaceRegisterMultiple(op_storeLoad.registerData, gprRegisterSearched, gprRegisterReplaced);
|
|
if (op_storeLoad.registerMem != PPC_REC_INVALID_REGISTER)
|
|
op_storeLoad.registerMem = replaceRegisterMultiple(op_storeLoad.registerMem, gprRegisterSearched, gprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_STORE_INDEXED)
|
|
{
|
|
op_storeLoad.registerData = replaceRegisterMultiple(op_storeLoad.registerData, gprRegisterSearched, gprRegisterReplaced);
|
|
if (op_storeLoad.registerMem != PPC_REC_INVALID_REGISTER)
|
|
op_storeLoad.registerMem = replaceRegisterMultiple(op_storeLoad.registerMem, gprRegisterSearched, gprRegisterReplaced);
|
|
if (op_storeLoad.registerMem2 != PPC_REC_INVALID_REGISTER)
|
|
op_storeLoad.registerMem2 = replaceRegisterMultiple(op_storeLoad.registerMem2, gprRegisterSearched, gprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_CR)
|
|
{
|
|
// only affects cr register
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_JUMPMARK)
|
|
{
|
|
// no effect on registers
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_PPC_ENTER)
|
|
{
|
|
// no op
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_R_NAME)
|
|
{
|
|
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_NAME_R)
|
|
{
|
|
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_LOAD)
|
|
{
|
|
if (op_storeLoad.registerMem != PPC_REC_INVALID_REGISTER)
|
|
{
|
|
op_storeLoad.registerMem = replaceRegisterMultiple(op_storeLoad.registerMem, gprRegisterSearched, gprRegisterReplaced);
|
|
}
|
|
if (op_storeLoad.registerGQR != PPC_REC_INVALID_REGISTER)
|
|
{
|
|
op_storeLoad.registerGQR = replaceRegisterMultiple(op_storeLoad.registerGQR, gprRegisterSearched, gprRegisterReplaced);
|
|
}
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_LOAD_INDEXED)
|
|
{
|
|
if (op_storeLoad.registerMem != PPC_REC_INVALID_REGISTER)
|
|
{
|
|
op_storeLoad.registerMem = replaceRegisterMultiple(op_storeLoad.registerMem, gprRegisterSearched, gprRegisterReplaced);
|
|
}
|
|
if (op_storeLoad.registerMem2 != PPC_REC_INVALID_REGISTER)
|
|
{
|
|
op_storeLoad.registerMem2 = replaceRegisterMultiple(op_storeLoad.registerMem2, gprRegisterSearched, gprRegisterReplaced);
|
|
}
|
|
if (op_storeLoad.registerGQR != PPC_REC_INVALID_REGISTER)
|
|
{
|
|
op_storeLoad.registerGQR = replaceRegisterMultiple(op_storeLoad.registerGQR, gprRegisterSearched, gprRegisterReplaced);
|
|
}
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_STORE)
|
|
{
|
|
if (op_storeLoad.registerMem != PPC_REC_INVALID_REGISTER)
|
|
{
|
|
op_storeLoad.registerMem = replaceRegisterMultiple(op_storeLoad.registerMem, gprRegisterSearched, gprRegisterReplaced);
|
|
}
|
|
if (op_storeLoad.registerGQR != PPC_REC_INVALID_REGISTER)
|
|
{
|
|
op_storeLoad.registerGQR = replaceRegisterMultiple(op_storeLoad.registerGQR, gprRegisterSearched, gprRegisterReplaced);
|
|
}
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_STORE_INDEXED)
|
|
{
|
|
if (op_storeLoad.registerMem != PPC_REC_INVALID_REGISTER)
|
|
{
|
|
op_storeLoad.registerMem = replaceRegisterMultiple(op_storeLoad.registerMem, gprRegisterSearched, gprRegisterReplaced);
|
|
}
|
|
if (op_storeLoad.registerMem2 != PPC_REC_INVALID_REGISTER)
|
|
{
|
|
op_storeLoad.registerMem2 = replaceRegisterMultiple(op_storeLoad.registerMem2, gprRegisterSearched, gprRegisterReplaced);
|
|
}
|
|
if (op_storeLoad.registerGQR != PPC_REC_INVALID_REGISTER)
|
|
{
|
|
op_storeLoad.registerGQR = replaceRegisterMultiple(op_storeLoad.registerGQR, gprRegisterSearched, gprRegisterReplaced);
|
|
}
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_R_R)
|
|
{
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_R_R_R)
|
|
{
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_R_R_R_R)
|
|
{
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_R)
|
|
{
|
|
}
|
|
else
|
|
{
|
|
cemu_assert_unimplemented();
|
|
}
|
|
}
|
|
|
|
void IMLInstruction::ReplaceFPRRegisterUsageMultiple(sint32 fprRegisterSearched[4], sint32 fprRegisterReplaced[4])
|
|
{
|
|
if (type == PPCREC_IML_TYPE_R_NAME)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_NAME_R)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_R_R)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_R_S32)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_R_R_S32)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_R_R_R)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_CJUMP || type == PPCREC_IML_TYPE_CJUMP_CYCLE_CHECK)
|
|
{
|
|
// no effect on registers
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_NO_OP)
|
|
{
|
|
// no effect on registers
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_MACRO)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_LOAD)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_LOAD_INDEXED)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_STORE)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_STORE_INDEXED)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_CR)
|
|
{
|
|
// only affects cr register
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_JUMPMARK)
|
|
{
|
|
// no effect on registers
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_PPC_ENTER)
|
|
{
|
|
// no op
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_R_NAME)
|
|
{
|
|
op_r_name.registerIndex = replaceRegisterMultiple(op_r_name.registerIndex, fprRegisterSearched, fprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_NAME_R)
|
|
{
|
|
op_r_name.registerIndex = replaceRegisterMultiple(op_r_name.registerIndex, fprRegisterSearched, fprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_LOAD)
|
|
{
|
|
op_storeLoad.registerData = replaceRegisterMultiple(op_storeLoad.registerData, fprRegisterSearched, fprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_LOAD_INDEXED)
|
|
{
|
|
op_storeLoad.registerData = replaceRegisterMultiple(op_storeLoad.registerData, fprRegisterSearched, fprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_STORE)
|
|
{
|
|
op_storeLoad.registerData = replaceRegisterMultiple(op_storeLoad.registerData, fprRegisterSearched, fprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_STORE_INDEXED)
|
|
{
|
|
op_storeLoad.registerData = replaceRegisterMultiple(op_storeLoad.registerData, fprRegisterSearched, fprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_R_R)
|
|
{
|
|
op_fpr_r_r.registerResult = replaceRegisterMultiple(op_fpr_r_r.registerResult, fprRegisterSearched, fprRegisterReplaced);
|
|
op_fpr_r_r.registerOperand = replaceRegisterMultiple(op_fpr_r_r.registerOperand, fprRegisterSearched, fprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_R_R_R)
|
|
{
|
|
op_fpr_r_r_r.registerResult = replaceRegisterMultiple(op_fpr_r_r_r.registerResult, fprRegisterSearched, fprRegisterReplaced);
|
|
op_fpr_r_r_r.registerOperandA = replaceRegisterMultiple(op_fpr_r_r_r.registerOperandA, fprRegisterSearched, fprRegisterReplaced);
|
|
op_fpr_r_r_r.registerOperandB = replaceRegisterMultiple(op_fpr_r_r_r.registerOperandB, fprRegisterSearched, fprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_R_R_R_R)
|
|
{
|
|
op_fpr_r_r_r_r.registerResult = replaceRegisterMultiple(op_fpr_r_r_r_r.registerResult, fprRegisterSearched, fprRegisterReplaced);
|
|
op_fpr_r_r_r_r.registerOperandA = replaceRegisterMultiple(op_fpr_r_r_r_r.registerOperandA, fprRegisterSearched, fprRegisterReplaced);
|
|
op_fpr_r_r_r_r.registerOperandB = replaceRegisterMultiple(op_fpr_r_r_r_r.registerOperandB, fprRegisterSearched, fprRegisterReplaced);
|
|
op_fpr_r_r_r_r.registerOperandC = replaceRegisterMultiple(op_fpr_r_r_r_r.registerOperandC, fprRegisterSearched, fprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_R)
|
|
{
|
|
op_fpr_r.registerResult = replaceRegisterMultiple(op_fpr_r.registerResult, fprRegisterSearched, fprRegisterReplaced);
|
|
}
|
|
else
|
|
{
|
|
cemu_assert_unimplemented();
|
|
}
|
|
}
|
|
|
|
void IMLInstruction::ReplaceFPRRegisterUsage(sint32 fprRegisterSearched, sint32 fprRegisterReplaced)
|
|
{
|
|
if (type == PPCREC_IML_TYPE_R_NAME)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_NAME_R)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_R_R)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_R_S32)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_R_R_S32)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_R_R_R)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_CJUMP || type == PPCREC_IML_TYPE_CJUMP_CYCLE_CHECK)
|
|
{
|
|
// no effect on registers
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_NO_OP)
|
|
{
|
|
// no effect on registers
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_MACRO)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_LOAD)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_LOAD_INDEXED)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_STORE)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_STORE_INDEXED)
|
|
{
|
|
// not affected
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_CR)
|
|
{
|
|
// only affects cr register
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_JUMPMARK)
|
|
{
|
|
// no effect on registers
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_PPC_ENTER)
|
|
{
|
|
// no op
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_R_NAME)
|
|
{
|
|
op_r_name.registerIndex = replaceRegister(op_r_name.registerIndex, fprRegisterSearched, fprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_NAME_R)
|
|
{
|
|
op_r_name.registerIndex = replaceRegister(op_r_name.registerIndex, fprRegisterSearched, fprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_LOAD)
|
|
{
|
|
op_storeLoad.registerData = replaceRegister(op_storeLoad.registerData, fprRegisterSearched, fprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_LOAD_INDEXED)
|
|
{
|
|
op_storeLoad.registerData = replaceRegister(op_storeLoad.registerData, fprRegisterSearched, fprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_STORE)
|
|
{
|
|
op_storeLoad.registerData = replaceRegister(op_storeLoad.registerData, fprRegisterSearched, fprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_STORE_INDEXED)
|
|
{
|
|
op_storeLoad.registerData = replaceRegister(op_storeLoad.registerData, fprRegisterSearched, fprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_R_R)
|
|
{
|
|
op_fpr_r_r.registerResult = replaceRegister(op_fpr_r_r.registerResult, fprRegisterSearched, fprRegisterReplaced);
|
|
op_fpr_r_r.registerOperand = replaceRegister(op_fpr_r_r.registerOperand, fprRegisterSearched, fprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_R_R_R)
|
|
{
|
|
op_fpr_r_r_r.registerResult = replaceRegister(op_fpr_r_r_r.registerResult, fprRegisterSearched, fprRegisterReplaced);
|
|
op_fpr_r_r_r.registerOperandA = replaceRegister(op_fpr_r_r_r.registerOperandA, fprRegisterSearched, fprRegisterReplaced);
|
|
op_fpr_r_r_r.registerOperandB = replaceRegister(op_fpr_r_r_r.registerOperandB, fprRegisterSearched, fprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_R_R_R_R)
|
|
{
|
|
op_fpr_r_r_r_r.registerResult = replaceRegister(op_fpr_r_r_r_r.registerResult, fprRegisterSearched, fprRegisterReplaced);
|
|
op_fpr_r_r_r_r.registerOperandA = replaceRegister(op_fpr_r_r_r_r.registerOperandA, fprRegisterSearched, fprRegisterReplaced);
|
|
op_fpr_r_r_r_r.registerOperandB = replaceRegister(op_fpr_r_r_r_r.registerOperandB, fprRegisterSearched, fprRegisterReplaced);
|
|
op_fpr_r_r_r_r.registerOperandC = replaceRegister(op_fpr_r_r_r_r.registerOperandC, fprRegisterSearched, fprRegisterReplaced);
|
|
}
|
|
else if (type == PPCREC_IML_TYPE_FPR_R)
|
|
{
|
|
op_fpr_r.registerResult = replaceRegister(op_fpr_r.registerResult, fprRegisterSearched, fprRegisterReplaced);
|
|
}
|
|
else
|
|
{
|
|
cemu_assert_unimplemented();
|
|
}
|
|
}
|