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https://github.com/cemu-project/Cemu.git
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PPCRec: Move debug printing + smaller clean up
This commit is contained in:
Exzap
parent
faf6c17438
commit
f95180d0fc
12 changed files with 520 additions and 582 deletions
471
src/Cafe/HW/Espresso/Recompiler/IML/IMLDebug.cpp
Normal file
471
src/Cafe/HW/Espresso/Recompiler/IML/IMLDebug.cpp
Normal file
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@ -0,0 +1,471 @@
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#include "IML.h"
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#include "IMLInstruction.h"
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#include "IMLSegment.h"
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#include "util/helpers/StringBuf.h"
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#include "Cafe/HW/Espresso/Recompiler/PPCRecompilerImlRanges.h"
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const char* IMLDebug_GetOpcodeName(const IMLInstruction* iml)
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{
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static char _tempOpcodename[32];
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uint32 op = iml->operation;
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if (op == PPCREC_IML_OP_ASSIGN)
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return "MOV";
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else if (op == PPCREC_IML_OP_ADD)
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return "ADD";
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else if (op == PPCREC_IML_OP_SUB)
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return "SUB";
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else if (op == PPCREC_IML_OP_ADD_CARRY_UPDATE_CARRY)
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return "ADDCSC";
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else if (op == PPCREC_IML_OP_OR)
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return "OR";
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else if (op == PPCREC_IML_OP_AND)
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return "AND";
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else if (op == PPCREC_IML_OP_XOR)
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return "XOR";
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else if (op == PPCREC_IML_OP_LEFT_SHIFT)
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return "LSH";
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else if (op == PPCREC_IML_OP_RIGHT_SHIFT)
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return "RSH";
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else if (op == PPCREC_IML_OP_MULTIPLY_SIGNED)
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return "MULS";
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else if (op == PPCREC_IML_OP_DIVIDE_SIGNED)
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return "DIVS";
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sprintf(_tempOpcodename, "OP0%02x_T%d", iml->operation, iml->type);
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return _tempOpcodename;
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}
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void IMLDebug_AppendRegisterParam(StringBuf& strOutput, sint32 virtualRegister, bool isLast = false)
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{
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if (isLast)
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{
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if (virtualRegister < 10)
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strOutput.addFmt("t{} ", virtualRegister);
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else
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strOutput.addFmt("t{}", virtualRegister);
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return;
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}
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if (virtualRegister < 10)
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strOutput.addFmt("t{} , ", virtualRegister);
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else
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strOutput.addFmt("t{}, ", virtualRegister);
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}
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void IMLDebug_AppendS32Param(StringBuf& strOutput, sint32 val, bool isLast = false)
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{
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if (isLast)
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{
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strOutput.addFmt("0x{:08x}", val);
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return;
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}
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strOutput.addFmt("0x{:08x}, ", val);
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}
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void IMLDebug_PrintLivenessRangeInfo(StringBuf& currentLineText, IMLSegment* imlSegment, sint32 offset)
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{
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// pad to 70 characters
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sint32 index = currentLineText.getLen();
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while (index < 70)
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{
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debug_printf(" ");
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index++;
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}
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raLivenessSubrange_t* subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
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while (subrangeItr)
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{
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if (offset == subrangeItr->start.index)
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{
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if (false)//subrange->isDirtied && i == subrange->becomesDirtyAtIndex.index)
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{
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debug_printf("*%-2d", subrangeItr->range->virtualRegister);
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}
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else
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{
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debug_printf("|%-2d", subrangeItr->range->virtualRegister);
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}
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}
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else if (false)//subrange->isDirtied && i == subrange->becomesDirtyAtIndex.index )
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{
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debug_printf("* ");
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}
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else if (offset >= subrangeItr->start.index && offset < subrangeItr->end.index)
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{
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debug_printf("| ");
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}
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else
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{
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debug_printf(" ");
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}
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index += 3;
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// next
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subrangeItr = subrangeItr->link_segmentSubrangesGPR.next;
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}
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}
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void IMLDebug_DumpSegment(IMLSegment* imlSegment, sint32 segmentIndex, bool printLivenessRangeInfo)
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{
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StringBuf strOutput(1024);
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strOutput.addFmt("SEGMENT 0x{:04x} 0x{:08x} PPC 0x{:08x} - 0x{:08x} Loop-depth {}", segmentIndex, imlSegment->ppcAddress, imlSegment->ppcAddrMin, imlSegment->ppcAddrMax, imlSegment->loopDepth);
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if (imlSegment->isEnterable)
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{
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strOutput.addFmt(" ENTERABLE (0x{:08x})", imlSegment->enterPPCAddress);
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}
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else if (imlSegment->isJumpDestination)
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{
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strOutput.addFmt(" JUMP-DEST (0x{:08x})", imlSegment->jumpDestinationPPCAddress);
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}
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debug_printf("%s\n", strOutput.c_str());
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strOutput.reset();
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strOutput.addFmt("SEGMENT NAME 0x{:016x}", (uintptr_t)imlSegment);
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debug_printf("%s", strOutput.c_str());
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if (printLivenessRangeInfo)
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{
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IMLDebug_PrintLivenessRangeInfo(strOutput, imlSegment, RA_INTER_RANGE_START);
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}
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debug_printf("\n");
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sint32 lineOffsetParameters = 18;
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for (sint32 i = 0; i < imlSegment->imlList.size(); i++)
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{
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const IMLInstruction& inst = imlSegment->imlList[i];
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// don't log NOP instructions unless they have an associated PPC address
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if (inst.type == PPCREC_IML_TYPE_NO_OP && inst.associatedPPCAddress == MPTR_NULL)
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continue;
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strOutput.reset();
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strOutput.addFmt("{:08x} ", inst.associatedPPCAddress);
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if (inst.type == PPCREC_IML_TYPE_R_NAME || inst.type == PPCREC_IML_TYPE_NAME_R)
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{
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if (inst.type == PPCREC_IML_TYPE_R_NAME)
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strOutput.add("LD_NAME");
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else
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strOutput.add("ST_NAME");
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while ((sint32)strOutput.getLen() < lineOffsetParameters)
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strOutput.add(" ");
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_name.registerIndex);
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strOutput.addFmt("name_{} (", inst.op_r_name.registerIndex, inst.op_r_name.name);
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if (inst.op_r_name.name >= PPCREC_NAME_R0 && inst.op_r_name.name < (PPCREC_NAME_R0 + 999))
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{
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strOutput.addFmt("r{}", inst.op_r_name.name - PPCREC_NAME_R0);
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}
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else if (inst.op_r_name.name >= PPCREC_NAME_SPR0 && inst.op_r_name.name < (PPCREC_NAME_SPR0 + 999))
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{
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strOutput.addFmt("spr{}", inst.op_r_name.name - PPCREC_NAME_SPR0);
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}
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else
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strOutput.add("ukn");
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strOutput.add(")");
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}
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else if (inst.type == PPCREC_IML_TYPE_R_R)
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{
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strOutput.addFmt("{}", IMLDebug_GetOpcodeName(&inst));
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while ((sint32)strOutput.getLen() < lineOffsetParameters)
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strOutput.add(" ");
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_r.registerResult);
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_r.registerA, true);
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if (inst.crRegister != PPC_REC_INVALID_REGISTER)
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{
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strOutput.addFmt(" -> CR{}", inst.crRegister);
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}
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}
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else if (inst.type == PPCREC_IML_TYPE_R_R_R)
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{
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strOutput.addFmt("{}", IMLDebug_GetOpcodeName(&inst));
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while ((sint32)strOutput.getLen() < lineOffsetParameters)
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strOutput.add(" ");
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_r_r.registerResult);
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_r_r.registerA);
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_r_r.registerB, true);
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if (inst.crRegister != PPC_REC_INVALID_REGISTER)
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{
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strOutput.addFmt(" -> CR{}", inst.crRegister);
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}
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}
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else if (inst.type == PPCREC_IML_TYPE_R_R_S32)
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{
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strOutput.addFmt("{}", IMLDebug_GetOpcodeName(&inst));
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while ((sint32)strOutput.getLen() < lineOffsetParameters)
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strOutput.add(" ");
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_r_s32.registerResult);
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_r_s32.registerA);
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IMLDebug_AppendS32Param(strOutput, inst.op_r_r_s32.immS32, true);
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if (inst.crRegister != PPC_REC_INVALID_REGISTER)
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{
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strOutput.addFmt(" -> CR{}", inst.crRegister);
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}
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}
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else if (inst.type == PPCREC_IML_TYPE_R_S32)
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{
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strOutput.addFmt("{}", IMLDebug_GetOpcodeName(&inst));
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while ((sint32)strOutput.getLen() < lineOffsetParameters)
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strOutput.add(" ");
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_immS32.registerIndex);
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IMLDebug_AppendS32Param(strOutput, inst.op_r_immS32.immS32, true);
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if (inst.crRegister != PPC_REC_INVALID_REGISTER)
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{
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strOutput.addFmt(" -> CR{}", inst.crRegister);
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}
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}
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else if (inst.type == PPCREC_IML_TYPE_JUMPMARK)
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{
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strOutput.addFmt("jm_{:08x}:", inst.op_jumpmark.address);
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}
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else if (inst.type == PPCREC_IML_TYPE_PPC_ENTER)
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{
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strOutput.addFmt("ppcEnter_{:08x}:", inst.op_ppcEnter.ppcAddress);
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}
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else if (inst.type == PPCREC_IML_TYPE_LOAD || inst.type == PPCREC_IML_TYPE_STORE ||
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inst.type == PPCREC_IML_TYPE_LOAD_INDEXED || inst.type == PPCREC_IML_TYPE_STORE_INDEXED)
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{
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if (inst.type == PPCREC_IML_TYPE_LOAD || inst.type == PPCREC_IML_TYPE_LOAD_INDEXED)
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strOutput.add("LD_");
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else
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strOutput.add("ST_");
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if (inst.op_storeLoad.flags2.signExtend)
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strOutput.add("S");
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else
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strOutput.add("U");
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strOutput.addFmt("{}", inst.op_storeLoad.copyWidth);
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while ((sint32)strOutput.getLen() < lineOffsetParameters)
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strOutput.add(" ");
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IMLDebug_AppendRegisterParam(strOutput, inst.op_storeLoad.registerData);
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if (inst.type == PPCREC_IML_TYPE_LOAD_INDEXED || inst.type == PPCREC_IML_TYPE_STORE_INDEXED)
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strOutput.addFmt("[t{}+t{}]", inst.op_storeLoad.registerMem, inst.op_storeLoad.registerMem2);
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else
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strOutput.addFmt("[t{}+{}]", inst.op_storeLoad.registerMem, inst.op_storeLoad.immS32);
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}
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else if (inst.type == PPCREC_IML_TYPE_CJUMP)
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{
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if (inst.op_conditionalJump.condition == PPCREC_JUMP_CONDITION_E)
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strOutput.add("JE");
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else if (inst.op_conditionalJump.condition == PPCREC_JUMP_CONDITION_NE)
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strOutput.add("JNE");
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else if (inst.op_conditionalJump.condition == PPCREC_JUMP_CONDITION_G)
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strOutput.add("JG");
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else if (inst.op_conditionalJump.condition == PPCREC_JUMP_CONDITION_GE)
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strOutput.add("JGE");
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else if (inst.op_conditionalJump.condition == PPCREC_JUMP_CONDITION_L)
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strOutput.add("JL");
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else if (inst.op_conditionalJump.condition == PPCREC_JUMP_CONDITION_LE)
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strOutput.add("JLE");
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else if (inst.op_conditionalJump.condition == PPCREC_JUMP_CONDITION_NONE)
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strOutput.add("JALW"); // jump always
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else
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cemu_assert_unimplemented();
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strOutput.addFmt(" jm_{:08x} (cr{})", inst.op_conditionalJump.jumpmarkAddress, inst.crRegister);
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}
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else if (inst.type == PPCREC_IML_TYPE_NO_OP)
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{
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strOutput.add("NOP");
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}
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else if (inst.type == PPCREC_IML_TYPE_MACRO)
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{
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if (inst.operation == PPCREC_IML_MACRO_BLR)
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{
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strOutput.addFmt("MACRO BLR 0x{:08x} cycles (depr): {}", inst.op_macro.param, (sint32)inst.op_macro.paramU16);
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}
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else if (inst.operation == PPCREC_IML_MACRO_BLRL)
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{
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strOutput.addFmt("MACRO BLRL 0x{:08x} cycles (depr): {}", inst.op_macro.param, (sint32)inst.op_macro.paramU16);
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}
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else if (inst.operation == PPCREC_IML_MACRO_BCTR)
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{
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strOutput.addFmt("MACRO BCTR 0x{:08x} cycles (depr): {}", inst.op_macro.param, (sint32)inst.op_macro.paramU16);
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}
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else if (inst.operation == PPCREC_IML_MACRO_BCTRL)
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{
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strOutput.addFmt("MACRO BCTRL 0x{:08x} cycles (depr): {}", inst.op_macro.param, (sint32)inst.op_macro.paramU16);
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}
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else if (inst.operation == PPCREC_IML_MACRO_BL)
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{
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strOutput.addFmt("MACRO BL 0x{:08x} -> 0x{:08x} cycles (depr): {}", inst.op_macro.param, inst.op_macro.param2, (sint32)inst.op_macro.paramU16);
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}
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else if (inst.operation == PPCREC_IML_MACRO_B_FAR)
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{
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strOutput.addFmt("MACRO B_FAR 0x{:08x} -> 0x{:08x} cycles (depr): {}", inst.op_macro.param, inst.op_macro.param2, (sint32)inst.op_macro.paramU16);
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}
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else if (inst.operation == PPCREC_IML_MACRO_LEAVE)
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{
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strOutput.addFmt("MACRO LEAVE ppc: 0x{:08x}", inst.op_macro.param);
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}
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else if (inst.operation == PPCREC_IML_MACRO_HLE)
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{
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strOutput.addFmt("MACRO HLE ppcAddr: 0x{:08x} funcId: 0x{:08x}", inst.op_macro.param, inst.op_macro.param2);
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}
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else if (inst.operation == PPCREC_IML_MACRO_MFTB)
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{
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strOutput.addFmt("MACRO MFTB ppcAddr: 0x{:08x} sprId: 0x{:08x}", inst.op_macro.param, inst.op_macro.param2);
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}
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else if (inst.operation == PPCREC_IML_MACRO_COUNT_CYCLES)
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{
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strOutput.addFmt("MACRO COUNT_CYCLES cycles: {}", inst.op_macro.param);
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}
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else
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{
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strOutput.addFmt("MACRO ukn operation {}", inst.operation);
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}
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}
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else if (inst.type == PPCREC_IML_TYPE_FPR_R_NAME)
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{
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strOutput.addFmt("fpr_t{} = name_{} (", inst.op_r_name.registerIndex, inst.op_r_name.name);
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if (inst.op_r_name.name >= PPCREC_NAME_FPR0 && inst.op_r_name.name < (PPCREC_NAME_FPR0 + 999))
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{
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strOutput.addFmt("fpr{}", inst.op_r_name.name - PPCREC_NAME_FPR0);
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}
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else if (inst.op_r_name.name >= PPCREC_NAME_TEMPORARY_FPR0 && inst.op_r_name.name < (PPCREC_NAME_TEMPORARY_FPR0 + 999))
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{
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strOutput.addFmt("tempFpr{}", inst.op_r_name.name - PPCREC_NAME_TEMPORARY_FPR0);
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}
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else
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strOutput.add("ukn");
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strOutput.add(")");
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}
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else if (inst.type == PPCREC_IML_TYPE_FPR_NAME_R)
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{
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strOutput.addFmt("name_{} (", inst.op_r_name.name);
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if (inst.op_r_name.name >= PPCREC_NAME_FPR0 && inst.op_r_name.name < (PPCREC_NAME_FPR0 + 999))
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{
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strOutput.addFmt("fpr{}", inst.op_r_name.name - PPCREC_NAME_FPR0);
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}
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else if (inst.op_r_name.name >= PPCREC_NAME_TEMPORARY_FPR0 && inst.op_r_name.name < (PPCREC_NAME_TEMPORARY_FPR0 + 999))
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{
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strOutput.addFmt("tempFpr{}", inst.op_r_name.name - PPCREC_NAME_TEMPORARY_FPR0);
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}
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else
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strOutput.add("ukn");
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strOutput.addFmt(") = fpr_t{}", inst.op_r_name.registerIndex);
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}
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else if (inst.type == PPCREC_IML_TYPE_FPR_LOAD)
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{
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strOutput.addFmt("fpr_t{} = ", inst.op_storeLoad.registerData);
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if (inst.op_storeLoad.flags2.signExtend)
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strOutput.add("S");
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else
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strOutput.add("U");
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strOutput.addFmt("{} [t{}+{}] mode {}", inst.op_storeLoad.copyWidth / 8, inst.op_storeLoad.registerMem, inst.op_storeLoad.immS32, inst.op_storeLoad.mode);
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if (inst.op_storeLoad.flags2.notExpanded)
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{
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strOutput.addFmt(" <No expand>");
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}
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}
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else if (inst.type == PPCREC_IML_TYPE_FPR_STORE)
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{
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if (inst.op_storeLoad.flags2.signExtend)
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strOutput.add("S");
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else
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strOutput.add("U");
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strOutput.addFmt("{} [t{}+{}]", inst.op_storeLoad.copyWidth / 8, inst.op_storeLoad.registerMem, inst.op_storeLoad.immS32);
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strOutput.addFmt("= fpr_t{} mode {}\n", inst.op_storeLoad.registerData, inst.op_storeLoad.mode);
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}
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else if (inst.type == PPCREC_IML_TYPE_FPR_R_R)
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{
|
||||
strOutput.addFmt("{:-6} ", IMLDebug_GetOpcodeName(&inst));
|
||||
strOutput.addFmt("fpr{:02d}, fpr{:02d}", inst.op_fpr_r_r.registerResult, inst.op_fpr_r_r.registerOperand);
|
||||
}
|
||||
else if (inst.type == PPCREC_IML_TYPE_FPR_R_R_R_R)
|
||||
{
|
||||
strOutput.addFmt("{:-6} ", IMLDebug_GetOpcodeName(&inst));
|
||||
strOutput.addFmt("fpr{:02d}, fpr{:02d}, fpr{:02d}, fpr{:02d}", inst.op_fpr_r_r_r_r.registerResult, inst.op_fpr_r_r_r_r.registerOperandA, inst.op_fpr_r_r_r_r.registerOperandB, inst.op_fpr_r_r_r_r.registerOperandC);
|
||||
}
|
||||
else if (inst.type == PPCREC_IML_TYPE_FPR_R_R_R)
|
||||
{
|
||||
strOutput.addFmt("{:-6} ", IMLDebug_GetOpcodeName(&inst));
|
||||
strOutput.addFmt("fpr{:02d}, fpr{:02d}, fpr{:02d}", inst.op_fpr_r_r_r.registerResult, inst.op_fpr_r_r_r.registerOperandA, inst.op_fpr_r_r_r.registerOperandB);
|
||||
}
|
||||
else if (inst.type == PPCREC_IML_TYPE_CJUMP_CYCLE_CHECK)
|
||||
{
|
||||
strOutput.addFmt("CYCLE_CHECK jm_{:08x}\n", inst.op_conditionalJump.jumpmarkAddress);
|
||||
}
|
||||
else if (inst.type == PPCREC_IML_TYPE_CONDITIONAL_R_S32)
|
||||
{
|
||||
strOutput.addFmt("t{} ", inst.op_conditional_r_s32.registerIndex);
|
||||
bool displayAsHex = false;
|
||||
if (inst.operation == PPCREC_IML_OP_ASSIGN)
|
||||
{
|
||||
displayAsHex = true;
|
||||
strOutput.add("=");
|
||||
}
|
||||
else
|
||||
strOutput.addFmt("(unknown operation CONDITIONAL_R_S32 {})", inst.operation);
|
||||
if (displayAsHex)
|
||||
strOutput.addFmt(" 0x{:x}", inst.op_conditional_r_s32.immS32);
|
||||
else
|
||||
strOutput.addFmt(" {}", inst.op_conditional_r_s32.immS32);
|
||||
strOutput.add(" (conditional)");
|
||||
if (inst.crRegister != PPC_REC_INVALID_REGISTER)
|
||||
{
|
||||
strOutput.addFmt(" -> and update CR{}", inst.crRegister);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
strOutput.addFmt("Unknown iml type {}", inst.type);
|
||||
}
|
||||
debug_printf("%s", strOutput.c_str());
|
||||
if (printLivenessRangeInfo)
|
||||
{
|
||||
IMLDebug_PrintLivenessRangeInfo(strOutput, imlSegment, i);
|
||||
}
|
||||
debug_printf("\n");
|
||||
}
|
||||
// all ranges
|
||||
if (printLivenessRangeInfo)
|
||||
{
|
||||
debug_printf("Ranges-VirtReg ");
|
||||
raLivenessSubrange_t* subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
|
||||
while (subrangeItr)
|
||||
{
|
||||
debug_printf("v%-2d", subrangeItr->range->virtualRegister);
|
||||
subrangeItr = subrangeItr->link_segmentSubrangesGPR.next;
|
||||
}
|
||||
debug_printf("\n");
|
||||
debug_printf("Ranges-PhysReg ");
|
||||
subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
|
||||
while (subrangeItr)
|
||||
{
|
||||
debug_printf("p%-2d", subrangeItr->range->physicalRegister);
|
||||
subrangeItr = subrangeItr->link_segmentSubrangesGPR.next;
|
||||
}
|
||||
debug_printf("\n");
|
||||
}
|
||||
// branch info
|
||||
debug_printf("Links from: ");
|
||||
for (sint32 i = 0; i < imlSegment->list_prevSegments.size(); i++)
|
||||
{
|
||||
if (i)
|
||||
debug_printf(", ");
|
||||
debug_printf("%p", (void*)imlSegment->list_prevSegments[i]);
|
||||
}
|
||||
debug_printf("\n");
|
||||
debug_printf("Links to: ");
|
||||
if (imlSegment->nextSegmentBranchNotTaken)
|
||||
debug_printf("%p (no branch), ", (void*)imlSegment->nextSegmentBranchNotTaken);
|
||||
if (imlSegment->nextSegmentBranchTaken)
|
||||
debug_printf("%p (branch)", (void*)imlSegment->nextSegmentBranchTaken);
|
||||
debug_printf("\n");
|
||||
}
|
||||
|
||||
void IMLDebug_Dump(ppcImlGenContext_t* ppcImlGenContext)
|
||||
{
|
||||
for (size_t i = 0; i < ppcImlGenContext->segmentList2.size(); i++)
|
||||
{
|
||||
IMLDebug_DumpSegment(ppcImlGenContext->segmentList2[i], i);
|
||||
debug_printf("\n");
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue