From f24fc3ed3307e2dede3458ef1bacb978add2fcf4 Mon Sep 17 00:00:00 2001 From: Exverge Date: Thu, 11 Jul 2024 14:38:34 -0400 Subject: [PATCH] MMU: Make HIGHMEM address conditional --- src/Cafe/HW/MMU/MMU.cpp | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/Cafe/HW/MMU/MMU.cpp b/src/Cafe/HW/MMU/MMU.cpp index b80d639e..ce15600a 100644 --- a/src/Cafe/HW/MMU/MMU.cpp +++ b/src/Cafe/HW/MMU/MMU.cpp @@ -123,7 +123,12 @@ MMURange mmuRange_SHARED_AREA { 0xF8000000, 0x02000000, MMU_MEM_AREA_ID::SHARE MMURange mmuRange_CORE0_LC { 0xFFC00000, 0x00005000, MMU_MEM_AREA_ID::CPU_LC0, "CORE0_LC" }; // locked L2 cache of core 0 MMURange mmuRange_CORE1_LC { 0xFFC40000, 0x00005000, MMU_MEM_AREA_ID::CPU_LC1, "CORE1_LC" }; // locked L2 cache of core 1 MMURange mmuRange_CORE2_LC { 0xFFC80000, 0x00005000, MMU_MEM_AREA_ID::CPU_LC2, "CORE2_LC" }; // locked L2 cache of core 2 -MMURange mmuRange_HIGHMEM { 0xFFFFC000, 0x00004000, MMU_MEM_AREA_ID::CPU_PER_CORE, "PER-CORE" }; // per-core memory? Used by coreinit and PPC kernel to store core context specific data (like current thread ptr). We dont use it but Project Zero has a bug where it writes a byte at 0xfffffffe thus this memory range needs to be writable +#if !defined(__arm64__) || !defined(__APPLE__) +MMURange mmuRange_HIGHMEM { 0xFFFFF000, 0x00001000, MMU_MEM_AREA_ID::CPU_PER_CORE, "PER-CORE" }; // per-core memory? Used by coreinit and PPC kernel to store core context specific data (like current thread ptr). We dont use it but Project Zero has a bug where it writes a byte at 0xfffffffe thus this memory range needs to be writable +#else +// Apple Silicon uses a 16kb pagesize, it can't allocate higher than this +MMURange mmuRange_HIGHMEM { 0xFFFFC000, 0x00004000, MMU_MEM_AREA_ID::CPU_PER_CORE, "PER-CORE" }; +#endif void memory_init() {