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PPCRec: Reworked IML builder to work with basic-blocks
Intermediate commit while I'm still fixing things but I didn't want to pile on too many changes in a single commit. New: Reworked PPC->IML converter to first create a graph of basic blocks and then turn those into IML segment(s). This was mainly done to decouple IML design from having PPC specific knowledge like branch target addresses. The previous design also didn't allow to preserve cycle counting properly in all cases since it was based on IML instruction counting. The new solution supports functions with non-continuous body. A pretty common example for this is when functions end with a trailing B instruction to some other place. Current limitations: - BL inlining not implemented - MFTB not implemented - BCCTR and BCLR are only partially implemented Undo vcpkg change
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0622631868
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18 changed files with 1554 additions and 689 deletions
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@ -74,44 +74,44 @@ void PPCRecRA_identifyLoop(ppcImlGenContext_t* ppcImlGenContext, IMLSegment* iml
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}
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}
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typedef struct
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{
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sint32 name;
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sint32 virtualRegister;
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sint32 physicalRegister;
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bool isDirty;
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}raRegisterState_t;
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//typedef struct
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//{
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// sint32 name;
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// sint32 virtualRegister;
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// sint32 physicalRegister;
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// bool isDirty;
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//}raRegisterState_t;
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const sint32 _raInfo_physicalGPRCount = PPC_X64_GPR_USABLE_REGISTERS;
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raRegisterState_t* PPCRecRA_getRegisterState(raRegisterState_t* regState, sint32 virtualRegister)
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{
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for (sint32 i = 0; i < _raInfo_physicalGPRCount; i++)
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{
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if (regState[i].virtualRegister == virtualRegister)
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{
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#ifdef CEMU_DEBUG_ASSERT
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if (regState[i].physicalRegister < 0)
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assert_dbg();
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#endif
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return regState + i;
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}
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}
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return nullptr;
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}
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raRegisterState_t* PPCRecRA_getFreePhysicalRegister(raRegisterState_t* regState)
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{
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for (sint32 i = 0; i < _raInfo_physicalGPRCount; i++)
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{
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if (regState[i].physicalRegister < 0)
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{
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regState[i].physicalRegister = i;
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return regState + i;
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}
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}
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return nullptr;
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}
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//const sint32 _raInfo_physicalGPRCount = PPC_X64_GPR_USABLE_REGISTERS;
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//
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//raRegisterState_t* PPCRecRA_getRegisterState(raRegisterState_t* regState, sint32 virtualRegister)
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//{
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// for (sint32 i = 0; i < _raInfo_physicalGPRCount; i++)
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// {
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// if (regState[i].virtualRegister == virtualRegister)
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// {
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//#ifdef CEMU_DEBUG_ASSERT
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// if (regState[i].physicalRegister < 0)
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// assert_dbg();
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//#endif
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// return regState + i;
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// }
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// }
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// return nullptr;
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//}
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//
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//raRegisterState_t* PPCRecRA_getFreePhysicalRegister(raRegisterState_t* regState)
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//{
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// for (sint32 i = 0; i < _raInfo_physicalGPRCount; i++)
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// {
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// if (regState[i].physicalRegister < 0)
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// {
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// regState[i].physicalRegister = i;
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// return regState + i;
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// }
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// }
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// return nullptr;
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//}
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typedef struct
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{
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@ -309,18 +309,32 @@ void _sortSegmentAllSubrangesLinkedList(IMLSegment* imlSegment)
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#endif
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}
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void PPCRecRA_HandleFixedRegisters(ppcImlGenContext_t* ppcImlGenContext, IMLSegment* imlSegment)
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{
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// this works as a pre-pass to actual register allocation. Assigning registers in advance based on fixed requirements (e.g. calling conventions and operations with fixed-reg input/output like x86 DIV/MUL)
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// algorithm goes as follows:
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// 1) Iterate all instructions from beginning to end and keep a list of covering ranges
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// 2) If we encounter an instruction with a fixed-register we:
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// 2.0) Check if there are any other ranges already using the same fixed-register and if yes, we split them and unassign the register for any follow-up instructions just prior to the current instruction
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// 2.1) For inputs: Split the range that needs to be assigned a phys reg on the current instruction. Basically creating a 1-instruction long subrange that we can assign the physical register. RA will then schedule register allocation around that and avoid moves
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// 2.2) For outputs: Split the range that needs to be assigned a phys reg on the current instruction
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// Q: What if a specific fixed-register is used both for input and output and thus is destructive? A: Create temporary range
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// Q: What if we have 3 different inputs that are all the same virtual register? A: Create temporary range
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// Q: Assuming the above is implemented, do we even support overlapping two ranges of separate virtual regs on the same phys register? In theory the RA shouldn't care
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// assume imlSegment->raInfo.linkedList_allSubranges is ordered ascending by start index already
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// todo
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}
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bool PPCRecRA_assignSegmentRegisters(ppcImlGenContext_t* ppcImlGenContext, IMLSegment* imlSegment)
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{
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// sort subranges ascending by start index
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//std::sort(imlSegment->raInfo.list_subranges.begin(), imlSegment->raInfo.list_subranges.end(), _sortSubrangesByStartIndexDepr);
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_sortSegmentAllSubrangesLinkedList(imlSegment);
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PPCRecRA_HandleFixedRegisters(ppcImlGenContext, imlSegment);
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raLiveRangeInfo_t liveInfo;
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liveInfo.liveRangesCount = 0;
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//sint32 subrangeIndex = 0;
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//for (auto& subrange : imlSegment->raInfo.list_subranges)
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raLivenessSubrange_t* subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
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while(subrangeItr)
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{
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@ -365,7 +379,7 @@ bool PPCRecRA_assignSegmentRegisters(ppcImlGenContext_t* ppcImlGenContext, IMLSe
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subrangeItr = subrangeItr->link_segmentSubrangesGPR.next;
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continue;
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}
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// find free register
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// find free register for this segment
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uint32 physRegisterMask = (1<<PPC_X64_GPR_USABLE_REGISTERS)-1;
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for (sint32 f = 0; f < liveInfo.liveRangesCount; f++)
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{
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@ -379,6 +393,7 @@ bool PPCRecRA_assignSegmentRegisters(ppcImlGenContext_t* ppcImlGenContext, IMLSe
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uint32 unusedRegisterMask = physRegisterMask; // mask of registers that are currently not used (does not include range checks)
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if (physRegisterMask != 0)
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{
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// check globally
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allowedPhysRegisterMask = PPCRecRA_getAllowedRegisterMaskForFullRange(subrangeItr->range);
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physRegisterMask &= allowedPhysRegisterMask;
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}
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@ -761,7 +776,6 @@ void PPCRecRA_generateSegmentInstructions(ppcImlGenContext_t* ppcImlGenContext,
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sint32 suffixInstructionCount = imlSegment->HasSuffixInstruction() ? 1 : 0;
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// load register ranges that are supplied from previous segments
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raLivenessSubrange_t* subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
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//for (auto& subrange : imlSegment->raInfo.list_subranges)
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while(subrangeItr)
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{
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if (subrangeItr->start.index == RA_INTER_RANGE_START)
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@ -933,7 +947,7 @@ void PPCRecRA_calculateLivenessRangesV2(ppcImlGenContext_t* ppcImlGenContext);
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void PPCRecRA_processFlowAndCalculateLivenessRangesV2(ppcImlGenContext_t* ppcImlGenContext);
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void PPCRecRA_analyzeRangeDataFlowV2(ppcImlGenContext_t* ppcImlGenContext);
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void PPCRecompilerImm_prepareForRegisterAllocation(ppcImlGenContext_t* ppcImlGenContext)
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void PPCRecompilerImm_reshapeForRegisterAllocation(ppcImlGenContext_t* ppcImlGenContext)
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{
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// insert empty segments after every non-taken branch if the linked segment has more than one input
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// this gives the register allocator more room to create efficient spill code
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@ -985,7 +999,7 @@ void PPCRecompilerImm_prepareForRegisterAllocation(ppcImlGenContext_t* ppcImlGen
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void IMLRegisterAllocator_AllocateRegisters(ppcImlGenContext_t* ppcImlGenContext)
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{
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PPCRecompilerImm_prepareForRegisterAllocation(ppcImlGenContext);
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PPCRecompilerImm_reshapeForRegisterAllocation(ppcImlGenContext);
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ppcImlGenContext->raInfo.list_ranges = std::vector<raLivenessRange_t*>();
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@ -1243,7 +1257,6 @@ void PPCRecRA_checkAndTryExtendRange(ppcImlGenContext_t* ppcImlGenContext, IMLSe
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if (remainingScanDist <= 0)
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return; // can't reach end
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// also dont forget: Extending is easier if we allow 'non symmetric' branches. E.g. register range one enters one branch
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IMLSegment* route[64];
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route[0] = currentSegment;
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if (currentSegment->nextSegmentBranchNotTaken)
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