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360
src/Cafe/HW/Espresso/Interpreter/PPCInterpreterOPC.cpp
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360
src/Cafe/HW/Espresso/Interpreter/PPCInterpreterOPC.cpp
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#include "../PPCState.h"
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#include "PPCInterpreterInternal.h"
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#include "PPCInterpreterHelper.h"
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#include "Cafe/OS/libs/coreinit/coreinit_CodeGen.h"
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#include "../Recompiler/PPCRecompiler.h"
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#include "../Recompiler/PPCRecompilerX64.h"
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#include <float.h>
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#include "Cafe/HW/Latte/Core/LatteBufferCache.h"
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void PPCInterpreter_MFMSR(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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forceLogDebug_printf("Rare instruction: MFMSR");
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if (hCPU->sprExtended.msr & MSR_PR)
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{
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PPC_ASSERT(true);
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return;
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}
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int rD, rA, rB;
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PPC_OPC_TEMPL_X(Opcode, rD, rA, rB);
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hCPU->gpr[rD] = hCPU->sprExtended.msr;
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PPCInterpreter_nextInstruction(hCPU);
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}
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void PPCInterpreter_MTMSR(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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forceLogDebug_printf("Rare instruction: MTMSR");
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if (hCPU->sprExtended.msr & MSR_PR)
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{
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PPC_ASSERT(true);
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return;
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}
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int rS, rA, rB;
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PPC_OPC_TEMPL_X(Opcode, rS, rA, rB);
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hCPU->sprExtended.msr = hCPU->gpr[rS];
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PPCInterpreter_nextInstruction(hCPU);
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}
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void PPCInterpreter_MTFSB1X(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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forceLogDebug_printf("Rare instruction: MTFSB1X");
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int crbD, n1, n2;
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PPC_OPC_TEMPL_X(Opcode, crbD, n1, n2);
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if (crbD != 1 && crbD != 2)
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{
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hCPU->fpscr |= 1 << (31 - crbD);
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}
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if (Opcode & PPC_OPC_RC)
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{
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// update cr1 flags
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PPC_ASSERT(true);
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}
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PPCInterpreter_nextInstruction(hCPU);
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}
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void PPCInterpreter_MCRF(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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uint32 crD, crS, b;
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PPC_OPC_TEMPL_X(Opcode, crD, crS, b);
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crD >>= 2;
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crS >>= 2;
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for (sint32 i = 0; i<4; i++)
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ppc_setCRBit(hCPU, crD * 4 + i, ppc_getCRBit(hCPU, crS * 4 + i));
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PPCInterpreter_nextInstruction(hCPU);
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}
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void PPCInterpreter_MFCR(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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// frequently used by GCC compiled code (e.g. SM64 port)
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int rD, rA, rB;
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PPC_OPC_TEMPL_X(Opcode, rD, rA, rB);
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// in our array: cr0.LT is entry with index 0
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// in GPR: cr0.LT is in MSB
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uint32 cr = 0;
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for (sint32 i = 0; i < 32; i++)
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{
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cr <<= 1;
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if (ppc_getCRBit(hCPU, i) != 0)
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cr |= 1;
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}
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hCPU->gpr[rD] = cr;
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PPCInterpreter_nextInstruction(hCPU);
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}
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void PPCInterpreter_MTCRF(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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// frequently used by GCC compiled code (e.g. SM64 port)
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// tested
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uint32 rS;
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uint32 crfMask;
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PPC_OPC_TEMPL_XFX(Opcode, rS, crfMask);
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for (sint32 crIndex = 0; crIndex < 8; crIndex++)
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{
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if (!ppc_MTCRFMaskHasCRFieldSet(crfMask, crIndex))
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continue;
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uint32 crBitBase = crIndex * 4;
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uint8 nibble = (uint8)(hCPU->gpr[rS] >> (28 - crIndex * 4));
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ppc_setCRBit(hCPU, crBitBase + 0, (nibble >> 3) & 1);
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ppc_setCRBit(hCPU, crBitBase + 1, (nibble >> 2) & 1);
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ppc_setCRBit(hCPU, crBitBase + 2, (nibble >> 1) & 1);
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ppc_setCRBit(hCPU, crBitBase + 3, (nibble >> 0) & 1);
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}
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PPCInterpreter_nextInstruction(hCPU);
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}
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void PPCInterpreter_MCRXR(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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// used in Dont Starve: Giant Edition
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// also used frequently by Web Browser (webkit?)
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uint32 cr;
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cr = (Opcode >> (31 - 8)) & 7;
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cr >>= 2;
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uint32 xer = PPCInterpreter_getXER(hCPU);
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uint32 xerBits = (xer >> 28) & 0xF;
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// todo - is the order correct?
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ppc_setCRBit(hCPU, cr * 4 + 0, (xerBits >> 0) & 1);
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ppc_setCRBit(hCPU, cr * 4 + 1, (xerBits >> 1) & 1);
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ppc_setCRBit(hCPU, cr * 4 + 2, (xerBits >> 2) & 1);
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ppc_setCRBit(hCPU, cr * 4 + 3, (xerBits >> 3) & 1);
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// reset copied bits
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PPCInterpreter_setXER(hCPU, xer&~0xF0000000);
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PPCInterpreter_nextInstruction(hCPU);
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}
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void PPCInterpreter_TLBIE(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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int rS, rA, rB;
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PPC_OPC_TEMPL_X(Opcode, rS, rA, rB);
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PPCInterpreter_nextInstruction(hCPU);
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}
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void PPCInterpreter_TLBSYNC(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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cemu_assert_unimplemented();
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PPCInterpreter_nextInstruction(hCPU);
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}
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// branch instructions
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void PPCInterpreter_BX(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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uint32 li;
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PPC_OPC_TEMPL_I(Opcode, li);
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if ((Opcode & PPC_OPC_AA) == 0)
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li += (unsigned int)hCPU->instructionPointer;
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if (Opcode & PPC_OPC_LK)
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{
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// update LR and IP
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hCPU->spr.LR = (unsigned int)hCPU->instructionPointer + 4;
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hCPU->instructionPointer = li;
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PPCInterpreter_jumpToInstruction(hCPU, li);
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PPCRecompiler_attemptEnter(hCPU, li);
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return;
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}
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PPCInterpreter_jumpToInstruction(hCPU, li);
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}
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void PPCInterpreter_BCX(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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uint32 BO, BI, BD;
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PPC_OPC_TEMPL_B(Opcode, BO, BI, BD);
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if (!(BO & 4))
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hCPU->spr.CTR--;
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bool bo2 = (BO & 2) != 0;
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bool bo8 = (BO & 8) != 0; // branch condition true
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bool cr = ppc_getCRBit(hCPU, BI) != 0;
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if (((BO & 4) || ((hCPU->spr.CTR != 0) ^ bo2))
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&& ((BO & 16) || (!(cr ^ bo8))))
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{
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if (!(Opcode & PPC_OPC_AA))
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{
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BD += (unsigned int)hCPU->instructionPointer;
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}
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else
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{
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// should never happen
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cemu_assert_unimplemented();
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}
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if (Opcode & PPC_OPC_LK)
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hCPU->spr.LR = ((unsigned int)hCPU->instructionPointer) + 4;
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PPCInterpreter_jumpToInstruction(hCPU, BD);
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}
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else
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PPCInterpreter_nextInstruction(hCPU);
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}
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void PPCInterpreter_BCLRX(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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uint32 BO, BI, BD;
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PPC_OPC_TEMPL_XL(Opcode, BO, BI, BD);
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PPC_ASSERT(BD == 0);
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if (!(BO & 4))
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{
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if (hCPU->spr.CTR == 0)
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{
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PPC_ASSERT(true);
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forceLogDebug_printf("Decrementer underflow!\n");
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}
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hCPU->spr.CTR--;
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}
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bool bo2 = (BO & 2) ? true : false;
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bool bo8 = (BO & 8) ? true : false;
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bool cr = ppc_getCRBit(hCPU, BI) != 0;
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if (((BO & 4) || ((hCPU->spr.CTR != 0) ^ bo2))
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&& ((BO & 16) || (!(cr ^ bo8))))
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{
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BD = hCPU->spr.LR & 0xfffffffc;
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if (Opcode & PPC_OPC_LK)
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{
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hCPU->spr.LR = (unsigned int)hCPU->instructionPointer + 4;
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}
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PPCInterpreter_jumpToInstruction(hCPU, BD);
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PPCRecompiler_attemptEnter(hCPU, BD);
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return;
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}
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else
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{
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BD = (unsigned int)hCPU->instructionPointer + 4;
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PPCInterpreter_nextInstruction(hCPU);
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}
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}
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void PPCInterpreter_BCCTR(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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uint32 x = (unsigned int)hCPU->instructionPointer;
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uint32 BO, BI, BD;
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PPC_OPC_TEMPL_XL(Opcode, BO, BI, BD);
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PPC_ASSERT(BD == 0);
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PPC_ASSERT(!(BO & 2));
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bool bo8 = (BO & 8) ? true : false;
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bool cr = ppc_getCRBit(hCPU, BI) != 0;
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if ((BO & 16) || (!(cr ^ bo8)))
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{
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if (Opcode & PPC_OPC_LK)
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{
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hCPU->spr.LR = (unsigned int)hCPU->instructionPointer + 4;
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hCPU->instructionPointer = (unsigned int)(hCPU->spr.CTR & 0xfffffffc);
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}
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else
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{
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hCPU->instructionPointer = (unsigned int)(hCPU->spr.CTR & 0xfffffffc);
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}
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PPCRecompiler_attemptEnter(hCPU, hCPU->instructionPointer);
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}
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else
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{
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hCPU->instructionPointer += 4;
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}
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}
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void PPCInterpreter_DCBT(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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sint32 rA, rB;
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rA = (Opcode >> (31 - 15)) & 0x1F;
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rB = (Opcode >> (31 - 20)) & 0x1F;
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PPCInterpreter_nextInstruction(hCPU);
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}
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void PPCInterpreter_DCBST(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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sint32 rA, rB;
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rA = (Opcode >> (31 - 15)) & 0x1F;
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rB = (Opcode >> (31 - 20)) & 0x1F;
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uint32 ea = (rA ? hCPU->gpr[rA] : 0) + hCPU->gpr[rB];
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LatteBufferCache_notifyDCFlush(ea, 32);
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PPCInterpreter_nextInstruction(hCPU);
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}
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void PPCInterpreter_DCBF(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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sint32 rA, rB;
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rA = (Opcode >> (31 - 15)) & 0x1F;
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rB = (Opcode >> (31 - 20)) & 0x1F;
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uint32 ea = (rA ? hCPU->gpr[rA] : 0) + hCPU->gpr[rB];
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LatteBufferCache_notifyDCFlush(ea, 32);
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PPCInterpreter_nextInstruction(hCPU);
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}
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void PPCInterpreter_DCBZL(PPCInterpreter_t* hCPU, uint32 Opcode) //Undocumented
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{
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// no-op
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PPCInterpreter_nextInstruction(hCPU);
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}
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void PPCInterpreter_DCBI(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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// no-op
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PPCInterpreter_nextInstruction(hCPU);
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}
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void PPCInterpreter_ICBI(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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sint32 rD, rA, rB;
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PPC_OPC_TEMPL_X(Opcode, rD, rA, rB);
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uint32 ea = (rA ? hCPU->gpr[rA] : 0) + hCPU->gpr[rB];
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// invalidate range
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coreinit::codeGenHandleICBI(ea);
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PPCInterpreter_nextInstruction(hCPU);
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}
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void PPCInterpreter_EIEIO(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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// no effect
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// next instruction
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PPCInterpreter_nextInstruction(hCPU);
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}
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void PPCInterpreter_SC(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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forceLogDebug_printf("SC executed at 0x%08x", hCPU->instructionPointer);
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// next instruction
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PPCInterpreter_nextInstruction(hCPU);
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}
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void PPCInterpreter_SYNC(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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// no-op
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// next instruction
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PPCInterpreter_nextInstruction(hCPU);
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}
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void PPCInterpreter_ISYNC(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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// no-op
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// next instruction
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PPCInterpreter_nextInstruction(hCPU);
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}
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void PPCInterpreter_RFI(PPCInterpreter_t* hCPU, uint32 Opcode)
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{
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forceLogDebug_printf("RFI");
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hCPU->sprExtended.msr &= ~(0x87C0FF73 | 0x00040000);
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hCPU->sprExtended.msr |= hCPU->sprExtended.srr1 & 0x87c0ff73;
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hCPU->sprExtended.msr |= MSR_RI;
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hCPU->instructionPointer = (unsigned int)(hCPU->sprExtended.srr0);
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}
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