PPCRec: Rework CR bit handling

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CR bits are now resident in registers instead of being baked into the instruction definitions. Same for XER SO, and LWARX reservation EA and value.

Reworked LWARX/STWCX, CRxx ops, compare and branch instructions. As well as RC bit handling. Not all CR-related instructions are reimplemented yet.

Introduced atomic_cmp_store operation to allow implementing STWCX in architecture agnostic IML

Removed legacy CR-based compare and jump operations

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Exzap 2023-01-03 00:51:27 +01:00

parent db1f9c162f

commit ce9a48b987

21 changed files with 1115 additions and 1232 deletions

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src/Cafe/HW/Espresso/Recompiler/PPCRecompilerImlGen.cpp

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