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PPCRec: Rework CR bit handling
CR bits are now resident in registers instead of being baked into the instruction definitions. Same for XER SO, and LWARX reservation EA and value. Reworked LWARX/STWCX, CRxx ops, compare and branch instructions. As well as RC bit handling. Not all CR-related instructions are reimplemented yet. Introduced atomic_cmp_store operation to allow implementing STWCX in architecture agnostic IML Removed legacy CR-based compare and jump operations
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21 changed files with 1115 additions and 1232 deletions
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@ -186,6 +186,14 @@ PPCRecFunction_t* PPCRecompiler_recompileFunction(PPCFunctionBoundaryTracker::PP
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return nullptr;
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}
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//if (ppcRecFunc->ppcAddress == 0x30DF5F8)
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//{
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// debug_printf("----------------------------------------\n");
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// IMLDebug_Dump(&ppcImlGenContext);
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// __debugbreak();
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//}
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//if (ppcRecFunc->ppcAddress == 0x11223344)
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//{
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// //debug_printf("----------------------------------------\n");
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@ -302,9 +310,8 @@ bool PPCRecompiler_ApplyIMLPasses(ppcImlGenContext_t& ppcImlGenContext)
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IMLRegisterAllocator_AllocateRegisters(&ppcImlGenContext, raParam);
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// remove redundant name load and store instructions
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PPCRecompiler_reorderConditionModifyInstructions(&ppcImlGenContext);
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PPCRecompiler_removeRedundantCRUpdates(&ppcImlGenContext);
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//PPCRecompiler_reorderConditionModifyInstructions(&ppcImlGenContext);
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//PPCRecompiler_removeRedundantCRUpdates(&ppcImlGenContext);
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return true;
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}
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