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https://github.com/cemu-project/Cemu.git
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PPCRec: Make LSWI/STWSI more generic + GPR temporaries storage
This commit is contained in:
Exzap
parent
d724dded8e
commit
c4fb7b74f8
7 changed files with 161 additions and 319 deletions
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@ -50,24 +50,9 @@ uint32 PPCRecompiler_iterateCurrentInstruction(ppcImlGenContext_t* ppcImlGenCont
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IMLInstruction* PPCRecompilerImlGen_generateNewEmptyInstruction(ppcImlGenContext_t* ppcImlGenContext)
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{
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//if( ppcImlGenContext->imlListCount+1 > ppcImlGenContext->imlListSize )
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//{
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// sint32 newSize = ppcImlGenContext->imlListCount*2 + 2;
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// ppcImlGenContext->imlList = (IMLInstruction*)realloc(ppcImlGenContext->imlList, sizeof(IMLInstruction)*newSize);
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// ppcImlGenContext->imlListSize = newSize;
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//}
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//IMLInstruction* imlInstruction = ppcImlGenContext->imlList+ppcImlGenContext->imlListCount;
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//memset(imlInstruction, 0x00, sizeof(IMLInstruction));
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//imlInstruction->crRegister = PPC_REC_INVALID_REGISTER; // dont update any cr register by default
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//imlInstruction->associatedPPCAddress = ppcImlGenContext->ppcAddressOfCurrentInstruction;
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//ppcImlGenContext->imlListCount++;
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//return imlInstruction;
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IMLInstruction& inst = ppcImlGenContext->currentOutputSegment->imlList.emplace_back();
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memset(&inst, 0x00, sizeof(IMLInstruction));
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inst.crRegister = PPC_REC_INVALID_REGISTER; // dont update any cr register by default
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//imlInstruction->associatedPPCAddress = ppcImlGenContext->ppcAddressOfCurrentInstruction;
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return &inst;
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}
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@ -86,28 +71,12 @@ void PPCRecompilerImlGen_generateNewInstruction_r_r(ppcImlGenContext_t* ppcImlGe
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void PPCRecompilerImlGen_generateNewInstruction_r_r_r(ppcImlGenContext_t* ppcImlGenContext, uint32 operation, uint8 registerResult, uint8 registerA, uint8 registerB, uint8 crRegister=PPC_REC_INVALID_REGISTER, uint8 crMode=0)
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{
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// operation with three register operands (e.g. "t0 = t1 + t4")
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IMLInstruction* imlInstruction = PPCRecompilerImlGen_generateNewEmptyInstruction(ppcImlGenContext);
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imlInstruction->type = PPCREC_IML_TYPE_R_R_R;
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imlInstruction->operation = operation;
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imlInstruction->crRegister = crRegister;
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imlInstruction->crMode = crMode;
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imlInstruction->op_r_r_r.registerResult = registerResult;
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imlInstruction->op_r_r_r.registerA = registerA;
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imlInstruction->op_r_r_r.registerB = registerB;
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ppcImlGenContext->emitInst().make_r_r_r(operation, registerResult, registerA, registerB, crRegister, crMode);
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}
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void PPCRecompilerImlGen_generateNewInstruction_r_r_s32(ppcImlGenContext_t* ppcImlGenContext, uint32 operation, uint8 registerResult, uint8 registerA, sint32 immS32, uint8 crRegister=PPC_REC_INVALID_REGISTER, uint8 crMode=0)
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{
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// operation with two register operands and one signed immediate (e.g. "t0 = t1 + 1234")
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IMLInstruction* imlInstruction = PPCRecompilerImlGen_generateNewEmptyInstruction(ppcImlGenContext);
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imlInstruction->type = PPCREC_IML_TYPE_R_R_S32;
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imlInstruction->operation = operation;
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imlInstruction->crRegister = crRegister;
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imlInstruction->crMode = crMode;
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imlInstruction->op_r_r_s32.registerResult = registerResult;
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imlInstruction->op_r_r_s32.registerA = registerA;
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imlInstruction->op_r_r_s32.immS32 = immS32;
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ppcImlGenContext->emitInst().make_r_r_s32(operation, registerResult, registerA, immS32, crRegister, crMode);
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}
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void PPCRecompilerImlGen_generateNewInstruction_name_r(ppcImlGenContext_t* ppcImlGenContext, uint32 operation, uint8 registerIndex, uint32 name)
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@ -153,25 +122,6 @@ void PPCRecompilerImlGen_generateNewInstruction_conditional_r_s32(ppcImlGenConte
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}
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void PPCRecompilerImlGen_generateNewInstruction_jump(ppcImlGenContext_t* ppcImlGenContext, IMLInstruction* imlInstruction, uint32 jumpmarkAddress)
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{
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__debugbreak();
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//// jump
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//if (imlInstruction == NULL)
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// imlInstruction = PPCRecompilerImlGen_generateNewEmptyInstruction(ppcImlGenContext);
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//else
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// memset(imlInstruction, 0, sizeof(IMLInstruction));
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//imlInstruction->type = PPCREC_IML_TYPE_CJUMP;
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//imlInstruction->crRegister = PPC_REC_INVALID_REGISTER;
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//imlInstruction->op_conditionalJump.jumpmarkAddress = jumpmarkAddress;
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//imlInstruction->op_conditionalJump.jumpAccordingToSegment = false;
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//imlInstruction->op_conditionalJump.condition = PPCREC_JUMP_CONDITION_NONE;
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//imlInstruction->op_conditionalJump.crRegisterIndex = 0;
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//imlInstruction->op_conditionalJump.crBitIndex = 0;
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//imlInstruction->op_conditionalJump.bitMustBeSet = false;
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}
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// jump based on segment branches
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void PPCRecompilerImlGen_generateNewInstruction_jumpSegment(ppcImlGenContext_t* ppcImlGenContext, IMLInstruction* imlInstruction)
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{
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@ -180,18 +130,22 @@ void PPCRecompilerImlGen_generateNewInstruction_jumpSegment(ppcImlGenContext_t*
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imlInstruction = PPCRecompilerImlGen_generateNewEmptyInstruction(ppcImlGenContext);
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imlInstruction->type = PPCREC_IML_TYPE_CJUMP;
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imlInstruction->crRegister = PPC_REC_INVALID_REGISTER;
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imlInstruction->op_conditionalJump.jumpAccordingToSegment = true;
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imlInstruction->op_conditionalJump.condition = PPCREC_JUMP_CONDITION_NONE;
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imlInstruction->op_conditionalJump.crRegisterIndex = 0;
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imlInstruction->op_conditionalJump.crBitIndex = 0;
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imlInstruction->op_conditionalJump.bitMustBeSet = false;
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}
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void PPCRecompilerImlGen_generateNewInstruction_noOp(ppcImlGenContext_t* ppcImlGenContext, IMLInstruction* imlInstruction)
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void PPCRecompilerImlGen_generateNewInstruction_conditionalJumpSegment(ppcImlGenContext_t* ppcImlGenContext, uint32 jumpCondition, uint32 crRegisterIndex, uint32 crBitIndex, bool bitMustBeSet)
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{
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if (imlInstruction == NULL)
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imlInstruction = PPCRecompilerImlGen_generateNewEmptyInstruction(ppcImlGenContext);
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imlInstruction->make_no_op();
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// conditional jump
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IMLInstruction* imlInstruction = PPCRecompilerImlGen_generateNewEmptyInstruction(ppcImlGenContext);
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imlInstruction->type = PPCREC_IML_TYPE_CJUMP;
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imlInstruction->crRegister = PPC_REC_INVALID_REGISTER;
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imlInstruction->op_conditionalJump.condition = jumpCondition;
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imlInstruction->op_conditionalJump.crRegisterIndex = crRegisterIndex;
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imlInstruction->op_conditionalJump.crBitIndex = crBitIndex;
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imlInstruction->op_conditionalJump.bitMustBeSet = bitMustBeSet;
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}
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void PPCRecompilerImlGen_generateNewInstruction_cr(ppcImlGenContext_t* ppcImlGenContext, uint32 operation, uint8 crD, uint8 crA, uint8 crB)
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@ -209,48 +163,9 @@ void PPCRecompilerImlGen_generateNewInstruction_cr(ppcImlGenContext_t* ppcImlGen
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imlInstruction->op_cr.crB = crB;
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}
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void PPCRecompilerImlGen_generateNewInstruction_conditionalJump(ppcImlGenContext_t* ppcImlGenContext, uint32 jumpmarkAddress, uint32 jumpCondition, uint32 crRegisterIndex, uint32 crBitIndex, bool bitMustBeSet)
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{
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__debugbreak();
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//// conditional jump
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//IMLInstruction* imlInstruction = PPCRecompilerImlGen_generateNewEmptyInstruction(ppcImlGenContext);
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//imlInstruction->type = PPCREC_IML_TYPE_CJUMP;
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//imlInstruction->crRegister = PPC_REC_INVALID_REGISTER;
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//imlInstruction->op_conditionalJump.jumpAccordingToSegment = false;
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//imlInstruction->op_conditionalJump.jumpmarkAddress = jumpmarkAddress;
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//imlInstruction->op_conditionalJump.condition = jumpCondition;
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//imlInstruction->op_conditionalJump.crRegisterIndex = crRegisterIndex;
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//imlInstruction->op_conditionalJump.crBitIndex = crBitIndex;
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//imlInstruction->op_conditionalJump.bitMustBeSet = bitMustBeSet;
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}
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void PPCRecompilerImlGen_generateNewInstruction_conditionalJumpSegment(ppcImlGenContext_t* ppcImlGenContext, uint32 jumpCondition, uint32 crRegisterIndex, uint32 crBitIndex, bool bitMustBeSet)
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{
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// conditional jump
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IMLInstruction* imlInstruction = PPCRecompilerImlGen_generateNewEmptyInstruction(ppcImlGenContext);
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imlInstruction->type = PPCREC_IML_TYPE_CJUMP;
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imlInstruction->crRegister = PPC_REC_INVALID_REGISTER;
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imlInstruction->op_conditionalJump.jumpAccordingToSegment = true;
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imlInstruction->op_conditionalJump.condition = jumpCondition;
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imlInstruction->op_conditionalJump.crRegisterIndex = crRegisterIndex;
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imlInstruction->op_conditionalJump.crBitIndex = crBitIndex;
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imlInstruction->op_conditionalJump.bitMustBeSet = bitMustBeSet;
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}
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void PPCRecompilerImlGen_generateNewInstruction_r_memory(ppcImlGenContext_t* ppcImlGenContext, uint8 registerDestination, uint8 registerMemory, sint32 immS32, uint32 copyWidth, bool signExtend, bool switchEndian)
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{
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// load from memory
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IMLInstruction* imlInstruction = PPCRecompilerImlGen_generateNewEmptyInstruction(ppcImlGenContext);
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imlInstruction->type = PPCREC_IML_TYPE_LOAD;
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imlInstruction->operation = 0;
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imlInstruction->crRegister = PPC_REC_INVALID_REGISTER;
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imlInstruction->op_storeLoad.registerData = registerDestination;
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imlInstruction->op_storeLoad.registerMem = registerMemory;
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imlInstruction->op_storeLoad.immS32 = immS32;
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imlInstruction->op_storeLoad.copyWidth = copyWidth;
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imlInstruction->op_storeLoad.flags2.swapEndian = switchEndian;
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imlInstruction->op_storeLoad.flags2.signExtend = signExtend;
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ppcImlGenContext->emitInst().make_r_memory(registerDestination, registerMemory, immS32, copyWidth, signExtend, switchEndian);
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}
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void PPCRecompilerImlGen_generateNewInstruction_r_memory_indexed(ppcImlGenContext_t* ppcImlGenContext, uint8 registerDestination, uint8 registerMemory1, uint8 registerMemory2, uint32 copyWidth, bool signExtend, bool switchEndian)
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@ -270,17 +185,7 @@ void PPCRecompilerImlGen_generateNewInstruction_r_memory_indexed(ppcImlGenContex
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void PPCRecompilerImlGen_generateNewInstruction_memory_r(ppcImlGenContext_t* ppcImlGenContext, uint8 registerSource, uint8 registerMemory, sint32 immS32, uint32 copyWidth, bool switchEndian)
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{
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// load from memory
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IMLInstruction* imlInstruction = PPCRecompilerImlGen_generateNewEmptyInstruction(ppcImlGenContext);
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imlInstruction->type = PPCREC_IML_TYPE_STORE;
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imlInstruction->operation = 0;
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imlInstruction->crRegister = PPC_REC_INVALID_REGISTER;
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imlInstruction->op_storeLoad.registerData = registerSource;
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imlInstruction->op_storeLoad.registerMem = registerMemory;
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imlInstruction->op_storeLoad.immS32 = immS32;
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imlInstruction->op_storeLoad.copyWidth = copyWidth;
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imlInstruction->op_storeLoad.flags2.swapEndian = switchEndian;
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imlInstruction->op_storeLoad.flags2.signExtend = false;
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ppcImlGenContext->emitInst().make_memory_r(registerSource, registerMemory, immS32, copyWidth, switchEndian);
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}
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void PPCRecompilerImlGen_generateNewInstruction_memory_r_indexed(ppcImlGenContext_t* ppcImlGenContext, uint8 registerDestination, uint8 registerMemory1, uint8 registerMemory2, uint32 copyWidth, bool signExtend, bool switchEndian)
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@ -630,10 +535,11 @@ void PPCRecompiler_generateInlinedCode(ppcImlGenContext_t* ppcImlGenContext, uin
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}
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}
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// add range
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ppcRecRange_t recRange;
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recRange.ppcAddress = startAddress;
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recRange.ppcSize = instructionCount*4 + 4; // + 4 because we have to include the BLR
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ppcImlGenContext->functionRef->list_ranges.push_back(recRange);
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cemu_assert_unimplemented();
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//ppcRecRange_t recRange;
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//recRange.ppcAddress = startAddress;
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//recRange.ppcSize = instructionCount*4 + 4; // + 4 because we have to include the BLR
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//ppcImlGenContext->functionRef->list_ranges.push_back(recRange);
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}
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bool PPCRecompilerImlGen_B(ppcImlGenContext_t* ppcImlGenContext, uint32 opcode)
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@ -653,14 +559,9 @@ bool PPCRecompilerImlGen_B(ppcImlGenContext_t* ppcImlGenContext, uint32 opcode)
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}
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// is jump destination within recompiled function?
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if( ppcImlGenContext->boundaryTracker->ContainsAddress(jumpAddressDest) )
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{
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// jump to target within same function
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PPCRecompilerImlGen_generateNewInstruction_jumpSegment(ppcImlGenContext, nullptr);
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}
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else
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{
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ppcImlGenContext->emitInst().make_macro(PPCREC_IML_MACRO_B_FAR, ppcImlGenContext->ppcAddressOfCurrentInstruction, jumpAddressDest, ppcImlGenContext->cyclesSinceLastBranch);
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}
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return true;
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}
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@ -778,10 +679,6 @@ bool PPCRecompilerImlGen_BC(ppcImlGenContext_t* ppcImlGenContext, uint32 opcode)
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// far jump
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debug_printf("PPCRecompilerImlGen_BC(): Far jump not supported yet");
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return false;
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PPCRecompilerImlGen_generateNewInstruction_conditionalJump(ppcImlGenContext, ppcImlGenContext->ppcAddressOfCurrentInstruction + 4, jumpCondition, crRegister, crBit, !conditionMustBeTrue);
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ppcImlGenContext->emitInst().make_macro(PPCREC_IML_MACRO_B_FAR, ppcImlGenContext->ppcAddressOfCurrentInstruction, jumpAddressDest, ppcImlGenContext->cyclesSinceLastBranch);
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//ppcImlGenContext->emitInst().make_ppcEnter(ppcImlGenContext->ppcAddressOfCurrentInstruction + 4);
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}
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}
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}
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@ -2190,70 +2087,40 @@ bool PPCRecompilerImlGen_LSWI(ppcImlGenContext_t* ppcImlGenContext, uint32 opcod
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PPC_OPC_TEMPL_X(opcode, rD, rA, nb);
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if( nb == 0 )
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nb = 32;
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if( nb == 4 )
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if (rA == 0)
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{
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// if nb == 4 this instruction immitates LWZ
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if( rA == 0 )
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{
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#ifdef CEMU_DEBUG_ASSERT
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assert_dbg(); // special form where gpr is ignored and only imm is used
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#endif
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return false;
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}
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// load memory gpr into register
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uint32 gprRegister = PPCRecompilerImlGen_loadRegister(ppcImlGenContext, PPCREC_NAME_R0+rA, false);
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// check if destination register is already loaded
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uint32 destinationRegister = PPCRecompilerImlGen_findRegisterByMappedName(ppcImlGenContext, PPCREC_NAME_R0+rD);
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if( destinationRegister == PPC_REC_INVALID_REGISTER )
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destinationRegister = PPCRecompilerImlGen_getAndLockFreeTemporaryGPR(ppcImlGenContext, PPCREC_NAME_R0+rD); // else just create new register
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// load half
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PPCRecompilerImlGen_generateNewInstruction_r_memory(ppcImlGenContext, destinationRegister, gprRegister, 0, 32, false, true);
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return true;
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cemu_assert_unimplemented(); // special form where gpr is ignored and EA is 0
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return false;
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}
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else if( nb == 2 )
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// potential optimization: On x86 unaligned access is allowed and we could handle the case nb==4 with a single memory read, and nb==2 with a memory read and shift
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uint32 memReg = PPCRecompilerImlGen_loadRegister(ppcImlGenContext, PPCREC_NAME_R0 + rA);
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uint32 tmpReg = PPCRecompilerImlGen_loadOverwriteRegister(ppcImlGenContext, PPCREC_NAME_TEMPORARY + 0);
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uint32 memOffset = 0;
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while (nb > 0)
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{
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// if nb == 2 this instruction immitates a LHZ but the result is shifted left by 16 bits
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if( rA == 0 )
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{
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#ifdef CEMU_DEBUG_ASSERT
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assert_dbg(); // special form where gpr is ignored and only imm is used
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#endif
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if (rD == rA)
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return false;
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}
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// load memory gpr into register
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uint32 gprRegister = PPCRecompilerImlGen_loadRegister(ppcImlGenContext, PPCREC_NAME_R0+rA, false);
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// check if destination register is already loaded
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uint32 destinationRegister = PPCRecompilerImlGen_findRegisterByMappedName(ppcImlGenContext, PPCREC_NAME_R0+rD);
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if( destinationRegister == PPC_REC_INVALID_REGISTER )
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destinationRegister = PPCRecompilerImlGen_getAndLockFreeTemporaryGPR(ppcImlGenContext, PPCREC_NAME_R0+rD); // else just create new register
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// load half
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PPCRecompilerImlGen_generateNewInstruction_r_memory(ppcImlGenContext, destinationRegister, gprRegister, 0, 16, false, true);
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// shift
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PPCRecompilerImlGen_generateNewInstruction_r_r_s32(ppcImlGenContext, PPCREC_IML_OP_LEFT_SHIFT, destinationRegister, destinationRegister, 16);
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return true;
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}
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else if( nb == 3 )
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{
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// if nb == 3 this instruction loads a 3-byte big-endian and the result is shifted left by 8 bits
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if( rA == 0 )
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cemu_assert(rD < 32);
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uint32 destinationRegister = PPCRecompilerImlGen_loadOverwriteRegister(ppcImlGenContext, PPCREC_NAME_R0 + rD);
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// load bytes one-by-one
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for (sint32 b = 0; b < 4; b++)
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{
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#ifdef CEMU_DEBUG_ASSERT
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assert_dbg(); // special form where gpr is ignored and only imm is used
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#endif
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return false;
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ppcImlGenContext->emitInst().make_r_memory(tmpReg, memReg, memOffset + b, 8, false, false);
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sint32 shiftAmount = (3 - b) * 8;
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if(shiftAmount)
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ppcImlGenContext->emitInst().make_r_r_s32(PPCREC_IML_OP_LEFT_SHIFT, tmpReg, tmpReg, shiftAmount);
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ppcImlGenContext->emitInst().make_r_r(b == 0 ? PPCREC_IML_OP_ASSIGN : PPCREC_IML_OP_OR, destinationRegister, tmpReg);
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nb--;
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if (nb == 0)
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break;
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}
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// load memory gpr into register
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uint32 gprRegister = PPCRecompilerImlGen_loadRegister(ppcImlGenContext, PPCREC_NAME_R0+rA, false);
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// check if destination register is already loaded
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uint32 destinationRegister = PPCRecompilerImlGen_findRegisterByMappedName(ppcImlGenContext, PPCREC_NAME_R0+rD);
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if( destinationRegister == PPC_REC_INVALID_REGISTER )
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destinationRegister = PPCRecompilerImlGen_getAndLockFreeTemporaryGPR(ppcImlGenContext, PPCREC_NAME_R0+rD); // else just create new register
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// load half
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PPCRecompilerImlGen_generateNewInstruction_r_memory(ppcImlGenContext, destinationRegister, gprRegister, 0, PPC_REC_STORE_LSWI_3, false, true);
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return true;
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memOffset += 4;
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rD++;
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}
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debug_printf("PPCRecompilerImlGen_LSWI(): Unsupported nb value %d\n", nb);
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return false;
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||||
return true;
|
||||
}
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||||
|
||||
bool PPCRecompilerImlGen_STSWI(ppcImlGenContext_t* ppcImlGenContext, uint32 opcode)
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||||
|
|
@ -2262,38 +2129,32 @@ bool PPCRecompilerImlGen_STSWI(ppcImlGenContext_t* ppcImlGenContext, uint32 opco
|
|||
PPC_OPC_TEMPL_X(opcode, rS, rA, nb);
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||||
if( nb == 0 )
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||||
nb = 32;
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||||
if( nb == 4 )
|
||||
|
||||
uint32 memReg = PPCRecompilerImlGen_loadRegister(ppcImlGenContext, PPCREC_NAME_R0 + rA);
|
||||
uint32 tmpReg = PPCRecompilerImlGen_loadOverwriteRegister(ppcImlGenContext, PPCREC_NAME_TEMPORARY + 0);
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||||
uint32 memOffset = 0;
|
||||
while (nb > 0)
|
||||
{
|
||||
// load memory gpr into register
|
||||
uint32 gprRegister = PPCRecompilerImlGen_loadRegister(ppcImlGenContext, PPCREC_NAME_R0+rA, false);
|
||||
// load source register
|
||||
uint32 sourceRegister = PPCRecompilerImlGen_loadRegister(ppcImlGenContext, PPCREC_NAME_R0+rS, false); // can be the same as gprRegister
|
||||
// store word
|
||||
PPCRecompilerImlGen_generateNewInstruction_memory_r(ppcImlGenContext, sourceRegister, gprRegister, 0, 32, true);
|
||||
return true;
|
||||
if (rS == rA)
|
||||
return false;
|
||||
cemu_assert(rS < 32);
|
||||
uint32 dataRegister = PPCRecompilerImlGen_loadRegister(ppcImlGenContext, PPCREC_NAME_R0 + rS);
|
||||
// store bytes one-by-one
|
||||
for (sint32 b = 0; b < 4; b++)
|
||||
{
|
||||
ppcImlGenContext->emitInst().make_r_r(PPCREC_IML_OP_ASSIGN, tmpReg, dataRegister);
|
||||
sint32 shiftAmount = (3 - b) * 8;
|
||||
if (shiftAmount)
|
||||
ppcImlGenContext->emitInst().make_r_r_s32(PPCREC_IML_OP_RIGHT_SHIFT, tmpReg, tmpReg, shiftAmount);
|
||||
ppcImlGenContext->emitInst().make_memory_r(tmpReg, memReg, memOffset + b, 8, false);
|
||||
nb--;
|
||||
if (nb == 0)
|
||||
break;
|
||||
}
|
||||
memOffset += 4;
|
||||
rS++;
|
||||
}
|
||||
else if( nb == 2 )
|
||||
{
|
||||
// load memory gpr into register
|
||||
uint32 gprRegister = PPCRecompilerImlGen_loadRegister(ppcImlGenContext, PPCREC_NAME_R0+rA, false);
|
||||
// load source register
|
||||
uint32 sourceRegister = PPCRecompilerImlGen_loadRegister(ppcImlGenContext, PPCREC_NAME_R0+rS, false); // can be the same as gprRegister
|
||||
// store half-word (shifted << 16)
|
||||
PPCRecompilerImlGen_generateNewInstruction_memory_r(ppcImlGenContext, sourceRegister, gprRegister, 0, PPC_REC_STORE_STSWI_2, false);
|
||||
return true;
|
||||
}
|
||||
else if( nb == 3 )
|
||||
{
|
||||
// load memory gpr into register
|
||||
uint32 gprRegister = PPCRecompilerImlGen_loadRegister(ppcImlGenContext, PPCREC_NAME_R0+rA, false);
|
||||
// load source register
|
||||
uint32 sourceRegister = PPCRecompilerImlGen_loadRegister(ppcImlGenContext, PPCREC_NAME_R0+rS, false); // can be the same as gprRegister
|
||||
// store 3-byte-word (shifted << 8)
|
||||
PPCRecompilerImlGen_generateNewInstruction_memory_r(ppcImlGenContext, sourceRegister, gprRegister, 0, PPC_REC_STORE_STSWI_3, false);
|
||||
return true;
|
||||
}
|
||||
debug_printf("PPCRecompilerImlGen_STSWI(): Unsupported nb value %d\n", nb);
|
||||
return false;
|
||||
return true;
|
||||
}
|
||||
|
||||
bool PPCRecompilerImlGen_DCBZ(ppcImlGenContext_t* ppcImlGenContext, uint32 opcode)
|
||||
|
|
@ -4293,9 +4154,7 @@ bool PPCRecompiler_GenerateIML(ppcImlGenContext_t& ppcImlGenContext, PPCFunction
|
|||
|
||||
bool PPCRecompiler_generateIntermediateCode(ppcImlGenContext_t& ppcImlGenContext, PPCRecFunction_t* ppcRecFunc, std::set<uint32>& entryAddresses, PPCFunctionBoundaryTracker& boundaryTracker)
|
||||
{
|
||||
ppcImlGenContext.functionRef = ppcRecFunc; // todo - remove this and replace internally with boundary tracker
|
||||
ppcImlGenContext.boundaryTracker = &boundaryTracker;
|
||||
|
||||
if (!PPCRecompiler_GenerateIML(ppcImlGenContext, boundaryTracker, entryAddresses))
|
||||
return false;
|
||||
|
||||
|
|
@ -4343,8 +4202,7 @@ bool PPCRecompiler_generateIntermediateCode(ppcImlGenContext_t& ppcImlGenContext
|
|||
uint8 branchCond_crRegisterIndex = lastInstruction->op_conditionalJump.crRegisterIndex;
|
||||
uint8 branchCond_crBitIndex = lastInstruction->op_conditionalJump.crBitIndex;
|
||||
bool branchCond_bitMustBeSet = lastInstruction->op_conditionalJump.bitMustBeSet;
|
||||
|
||||
PPCRecompilerImlGen_generateNewInstruction_noOp(&ppcImlGenContext, lastInstruction);
|
||||
lastInstruction->make_no_op();
|
||||
|
||||
// append conditional moves based on branch condition
|
||||
for (sint32 f = 0; f < conditionalSegment->imlList.size(); f++)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue