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PPCRec: Unify BCCTR and BCLR code
Instead of having fixed macros for BCCTR/BCCTRL/BCLR/BCLRL we now have only one single macro instruction that takes the jump destination as a register parameter. This also allows us to reuse an already loaded LR register (by something like MTLR) instead of loading it again from memory. As a necessary requirement for this: The register allocator now has support for read operations in suffix instructions
This commit is contained in:
Exzap
parent
f2a07ade4c
commit
bb6b18d78f
6 changed files with 95 additions and 271 deletions
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@ -797,194 +797,85 @@ bool PPCRecompilerImlGen_BC(ppcImlGenContext_t* ppcImlGenContext, uint32 opcode)
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return true;
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}
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bool PPCRecompilerImlGen_BCLR(ppcImlGenContext_t* ppcImlGenContext, uint32 opcode)
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// BCCTR or BCLR
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bool PPCRecompilerImlGen_BCSPR(ppcImlGenContext_t* ppcImlGenContext, uint32 opcode, uint32 sprReg)
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{
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PPCIMLGen_AssertIfNotLastSegmentInstruction(*ppcImlGenContext);
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uint32 BO, BI, BD;
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PPC_OPC_TEMPL_XL(opcode, BO, BI, BD);
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Espresso::BOField BO;
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uint32 BI;
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bool LK;
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Espresso::decodeOp_BCSPR(opcode, BO, BI, LK);
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uint32 crRegister = BI/4;
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uint32 crBit = BI%4;
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uint32 jumpCondition = 0;
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bool conditionMustBeTrue = (BO&8)!=0;
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bool useDecrementer = (BO&4)==0; // bit not set -> decrement
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bool decrementerMustBeZero = (BO&2)!=0; // bit set -> branch if CTR = 0, bit not set -> branch if CTR != 0
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bool ignoreCondition = (BO&16)!=0;
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bool saveLR = (opcode&PPC_OPC_LK)!=0;
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// since we skip this instruction if the condition is true, we need to invert the logic
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//bool invertedConditionMustBeTrue = !conditionMustBeTrue;
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if( useDecrementer )
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uint32 branchDestReg = PPCRecompilerImlGen_loadRegister(ppcImlGenContext, PPCREC_NAME_SPR0 + sprReg);
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if (LK)
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{
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cemu_assert_debug(false);
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return false; // unsupported
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}
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else
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{
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if( ignoreCondition )
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if (sprReg == SPR_LR)
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{
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// branch always, no condition and no decrementer check
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cemu_assert_debug(!ppcImlGenContext->currentBasicBlock->hasContinuedFlow);
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cemu_assert_debug(!ppcImlGenContext->currentBasicBlock->hasBranchTarget);
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if( saveLR )
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{
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ppcImlGenContext->emitInst().make_macro(PPCREC_IML_MACRO_BLRL, ppcImlGenContext->ppcAddressOfCurrentInstruction, 0, ppcImlGenContext->cyclesSinceLastBranch);
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}
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else
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{
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ppcImlGenContext->emitInst().make_macro(PPCREC_IML_MACRO_BLR, ppcImlGenContext->ppcAddressOfCurrentInstruction, 0, ppcImlGenContext->cyclesSinceLastBranch);
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}
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// if the branch target is LR, then preserve it in a temporary
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cemu_assert_suspicious(); // this case needs testing
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uint32 tmpRegister = PPCRecompilerImlGen_loadOverwriteRegister(ppcImlGenContext, PPCREC_NAME_TEMPORARY);
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PPCRecompilerImlGen_generateNewInstruction_r_r(ppcImlGenContext, nullptr, PPCREC_IML_OP_ASSIGN, tmpRegister, branchDestReg);
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branchDestReg = tmpRegister;
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}
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uint32 registerLR = PPCRecompilerImlGen_loadOverwriteRegister(ppcImlGenContext, PPCREC_NAME_SPR0 + SPR_LR);
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PPCRecompilerImlGen_generateNewInstruction_r_s32(ppcImlGenContext, PPCREC_IML_OP_ASSIGN, registerLR, ppcImlGenContext->ppcAddressOfCurrentInstruction + 4, 0, false, false, PPC_REC_INVALID_REGISTER, 0);
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}
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if (!BO.decrementerIgnore())
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{
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cemu_assert_unimplemented();
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return false;
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}
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else if (!BO.conditionIgnore())
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{
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// no decrementer but CR check
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cemu_assert_debug(ppcImlGenContext->currentBasicBlock->hasContinuedFlow);
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cemu_assert_debug(!ppcImlGenContext->currentBasicBlock->hasBranchTarget);
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// generate jump condition
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uint32 jumpCondition = 0;
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if (!BO.conditionInverted())
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{
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// CR bit must be set
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if (crBit == 0)
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jumpCondition = PPCREC_JUMP_CONDITION_L;
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else if (crBit == 1)
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jumpCondition = PPCREC_JUMP_CONDITION_G;
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else if (crBit == 2)
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jumpCondition = PPCREC_JUMP_CONDITION_E;
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else if (crBit == 3)
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jumpCondition = PPCREC_JUMP_CONDITION_SUMMARYOVERFLOW;
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}
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else
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{
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cemu_assert_debug(ppcImlGenContext->currentBasicBlock->hasContinuedFlow);
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cemu_assert_debug(!ppcImlGenContext->currentBasicBlock->hasBranchTarget);
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//debug_printf("[Rec-Disable] BCLR with condition or LR\n");
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//return false;
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// store LR
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if( saveLR )
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{
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cemu_assert_unimplemented(); // todo - this is difficult to handle because it needs to jump to the unmodified LR (we should cache it in a register which we pass to the macro?)
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return false;
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uint32 registerLR = PPCRecompilerImlGen_loadOverwriteRegister(ppcImlGenContext, PPCREC_NAME_SPR0+SPR_LR);
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PPCRecompilerImlGen_generateNewInstruction_r_s32(ppcImlGenContext, PPCREC_IML_OP_ASSIGN, registerLR, (ppcImlGenContext->ppcAddressOfCurrentInstruction+4)&0x7FFFFFFF, 0, false, false, PPC_REC_INVALID_REGISTER, 0);
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}
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// generate jump condition
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if(conditionMustBeTrue)
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{
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if( crBit == 0 )
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jumpCondition = PPCREC_JUMP_CONDITION_L;
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else if( crBit == 1 )
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jumpCondition = PPCREC_JUMP_CONDITION_G;
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else if( crBit == 2 )
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jumpCondition = PPCREC_JUMP_CONDITION_E;
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else if( crBit == 3 )
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jumpCondition = PPCREC_JUMP_CONDITION_SUMMARYOVERFLOW;
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}
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else
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{
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if( crBit == 0 )
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jumpCondition = PPCREC_JUMP_CONDITION_GE;
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else if( crBit == 1 )
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jumpCondition = PPCREC_JUMP_CONDITION_LE;
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else if( crBit == 2 )
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jumpCondition = PPCREC_JUMP_CONDITION_NE;
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else if( crBit == 3 )
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jumpCondition = PPCREC_JUMP_CONDITION_NSUMMARYOVERFLOW;
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}
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//if(conditionMustBeTrue)
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// ppcImlGenContext->emitInst().make_debugbreak(ppcImlGenContext->ppcAddressOfCurrentInstruction);
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// write the BCTR instruction to a new segment that is set as a branch target for the current segment
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PPCBasicBlockInfo* currentBasicBlock = ppcImlGenContext->currentBasicBlock;
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IMLSegment* bctrSeg = PPCIMLGen_CreateNewSegmentAsBranchTarget(*ppcImlGenContext, *currentBasicBlock);
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PPCRecompilerImlGen_generateNewInstruction_conditionalJumpSegment(ppcImlGenContext, jumpCondition, crRegister, crBit, conditionMustBeTrue);
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bctrSeg->AppendInstruction()->make_macro(PPCREC_IML_MACRO_BLR, ppcImlGenContext->ppcAddressOfCurrentInstruction, 0, ppcImlGenContext->cyclesSinceLastBranch);
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if (crBit == 0)
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jumpCondition = PPCREC_JUMP_CONDITION_GE;
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else if (crBit == 1)
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jumpCondition = PPCREC_JUMP_CONDITION_LE;
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else if (crBit == 2)
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jumpCondition = PPCREC_JUMP_CONDITION_NE;
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else if (crBit == 3)
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jumpCondition = PPCREC_JUMP_CONDITION_NSUMMARYOVERFLOW;
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}
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}
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return true;
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}
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bool PPCRecompilerImlGen_BCCTR(ppcImlGenContext_t* ppcImlGenContext, uint32 opcode)
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{
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PPCIMLGen_AssertIfNotLastSegmentInstruction(*ppcImlGenContext);
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// write the dynamic branch instruction to a new segment that is set as a branch target for the current segment
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PPCBasicBlockInfo* currentBasicBlock = ppcImlGenContext->currentBasicBlock;
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IMLSegment* bctrSeg = PPCIMLGen_CreateNewSegmentAsBranchTarget(*ppcImlGenContext, *currentBasicBlock);
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uint32 BO, BI, BD;
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PPC_OPC_TEMPL_XL(opcode, BO, BI, BD);
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PPCRecompilerImlGen_generateNewInstruction_conditionalJumpSegment(ppcImlGenContext, jumpCondition, crRegister, crBit, !BO.conditionInverted());
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uint32 crRegister = BI/4;
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uint32 crBit = BI%4;
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uint32 jumpCondition = 0;
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bool conditionMustBeTrue = (BO&8)!=0;
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bool useDecrementer = (BO&4)==0; // bit not set -> decrement
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bool decrementerMustBeZero = (BO&2)!=0; // bit set -> branch if CTR = 0, bit not set -> branch if CTR != 0
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bool ignoreCondition = (BO&16)!=0;
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bool saveLR = (opcode&PPC_OPC_LK)!=0;
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// since we skip this instruction if the condition is true, we need to invert the logic
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bool invertedConditionMustBeTrue = !conditionMustBeTrue;
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if( useDecrementer )
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{
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assert_dbg();
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// if added, dont forget inverted logic
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debug_printf("Rec: BCLR unsupported decrementer\n");
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return false; // unsupported
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bctrSeg->AppendInstruction()->make_macro(PPCREC_IML_MACRO_B_TO_REG, branchDestReg, 0, 0);
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}
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else
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{
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if( ignoreCondition )
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{
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// branch always, no condition and no decrementer
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if( saveLR )
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{
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uint32 registerLR = PPCRecompilerImlGen_loadOverwriteRegister(ppcImlGenContext, PPCREC_NAME_SPR0+SPR_LR);
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PPCRecompilerImlGen_generateNewInstruction_r_s32(ppcImlGenContext, PPCREC_IML_OP_ASSIGN, registerLR, (ppcImlGenContext->ppcAddressOfCurrentInstruction+4)&0x7FFFFFFF, 0, false, false, PPC_REC_INVALID_REGISTER, 0);
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}
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if (saveLR)
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ppcImlGenContext->emitInst().make_macro(PPCREC_IML_MACRO_BCTRL, ppcImlGenContext->ppcAddressOfCurrentInstruction, 0, ppcImlGenContext->cyclesSinceLastBranch);
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else
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ppcImlGenContext->emitInst().make_macro(PPCREC_IML_MACRO_BCTR, ppcImlGenContext->ppcAddressOfCurrentInstruction, 0, ppcImlGenContext->cyclesSinceLastBranch);
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}
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else
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{
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// get jump condition
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if (invertedConditionMustBeTrue)
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{
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if (crBit == 0)
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jumpCondition = PPCREC_JUMP_CONDITION_L;
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else if (crBit == 1)
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jumpCondition = PPCREC_JUMP_CONDITION_G;
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else if (crBit == 2)
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jumpCondition = PPCREC_JUMP_CONDITION_E;
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else if (crBit == 3)
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jumpCondition = PPCREC_JUMP_CONDITION_SUMMARYOVERFLOW;
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}
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else
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{
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if (crBit == 0)
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jumpCondition = PPCREC_JUMP_CONDITION_GE;
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else if (crBit == 1)
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jumpCondition = PPCREC_JUMP_CONDITION_LE;
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else if (crBit == 2)
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jumpCondition = PPCREC_JUMP_CONDITION_NE;
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else if (crBit == 3)
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jumpCondition = PPCREC_JUMP_CONDITION_NSUMMARYOVERFLOW;
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}
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// branch always, no condition and no decrementer check
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cemu_assert_debug(!ppcImlGenContext->currentBasicBlock->hasContinuedFlow);
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cemu_assert_debug(!ppcImlGenContext->currentBasicBlock->hasBranchTarget);
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ppcImlGenContext->emitInst().make_macro(PPCREC_IML_MACRO_B_TO_REG, branchDestReg, 0, 0);
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// debug checks
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//if (saveLR)
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// cemu_assert_debug(ppcImlGenContext->currentBasicBlock->);
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// we always store LR
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if (saveLR)
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{
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uint32 registerLR = PPCRecompilerImlGen_loadOverwriteRegister(ppcImlGenContext, PPCREC_NAME_SPR0 + SPR_LR);
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PPCRecompilerImlGen_generateNewInstruction_r_s32(ppcImlGenContext, PPCREC_IML_OP_ASSIGN, registerLR, (ppcImlGenContext->ppcAddressOfCurrentInstruction + 4) & 0x7FFFFFFF, 0, false, false, PPC_REC_INVALID_REGISTER, 0);
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}
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// write the BCTR instruction to a new segment that is set as a branch target for the current segment
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__debugbreak();
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PPCBasicBlockInfo* currentBasicBlock = ppcImlGenContext->currentBasicBlock;
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IMLSegment* bctrSeg = PPCIMLGen_CreateNewSegmentAsBranchTarget(*ppcImlGenContext, *currentBasicBlock);
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//PPCBasicBlockInfo* bctrSeg = currentBasicBlock->Get
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__debugbreak();
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// jump if BCLR condition NOT met (jump to jumpmark of next instruction, essentially skipping current instruction)
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PPCRecompilerImlGen_generateNewInstruction_conditionalJump(ppcImlGenContext, ppcImlGenContext->ppcAddressOfCurrentInstruction+4, jumpCondition, crRegister, crBit, invertedConditionMustBeTrue);
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ppcImlGenContext->emitInst().make_macro(PPCREC_IML_MACRO_BCTR, ppcImlGenContext->ppcAddressOfCurrentInstruction, 0, ppcImlGenContext->cyclesSinceLastBranch);
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}
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}
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return true;
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}
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@ -3333,8 +3224,8 @@ bool PPCRecompiler_decodePPCInstruction(ppcImlGenContext_t* ppcImlGenContext)
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case 19: // opcode category 19
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switch (PPC_getBits(opcode, 30, 10))
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{
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case 16:
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if (PPCRecompilerImlGen_BCLR(ppcImlGenContext, opcode) == false)
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case 16: // BCLR
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if (PPCRecompilerImlGen_BCSPR(ppcImlGenContext, opcode, SPR_LR) == false)
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unsupportedInstructionFound = true;
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break;
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case 129:
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@ -3365,8 +3256,8 @@ bool PPCRecompiler_decodePPCInstruction(ppcImlGenContext_t* ppcImlGenContext)
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if (PPCRecompilerImlGen_CROR(ppcImlGenContext, opcode) == false)
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unsupportedInstructionFound = true;
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break;
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case 528:
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if (PPCRecompilerImlGen_BCCTR(ppcImlGenContext, opcode) == false)
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case 528: // BCCTR
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if (PPCRecompilerImlGen_BCSPR(ppcImlGenContext, opcode, SPR_CTR) == false)
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unsupportedInstructionFound = true;
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break;
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default:
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@ -4008,14 +3899,6 @@ bool PPCRecompiler_CheckIfInstructionEndsSegment(PPCFunctionBoundaryTracker& bou
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case Espresso::PrimaryOpcode::GROUP_19:
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switch (Espresso::GetGroup19Opcode(opcode))
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{
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//case Espresso::Opcode19::BCLR:
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////case Espresso::Opcode19::BCCTR:
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//{
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// continueDefaultPath = false; // todo - set this to true if this instruction has a condition (including decrementer check)
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// makeNextInstEnterable = Espresso::DecodeLK(opcode);
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// return true;
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//}
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case Espresso::Opcode19::BCLR:
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case Espresso::Opcode19::BCCTR:
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{
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@ -4034,19 +3917,6 @@ bool PPCRecompiler_CheckIfInstructionEndsSegment(PPCFunctionBoundaryTracker& bou
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case Espresso::PrimaryOpcode::GROUP_31:
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switch (Espresso::GetGroup31Opcode(opcode))
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{
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//case Espresso::Opcode31::TW:
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// continueDefaultPath = true;
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// return true;
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//case Espresso::Opcode31::MFTB:
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// continueDefaultPath = true;
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// return true;
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//case Espresso::Opcode19::BCLR:
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//case Espresso::Opcode19::BCCTR:
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//{
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// continueDefaultPath = false;
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// makeNextInstEnterable = Espresso::DecodeLK(opcode);
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// return true;
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//}
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default:
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break;
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}
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@ -4336,7 +4206,6 @@ void PPCRecompiler_SetSegmentsUncertainFlow(ppcImlGenContext_t& ppcImlGenContext
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for (IMLSegment* segIt : ppcImlGenContext.segmentList2)
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{
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bool isLastSegment = segIt == ppcImlGenContext.segmentList2.back();
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//IMLSegment* nextSegment = isLastSegment ? nullptr : ppcImlGenContext->segmentList2[s + 1];
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// handle empty segment
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if (segIt->imlList.empty())
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{
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@ -4352,29 +4221,13 @@ void PPCRecompiler_SetSegmentsUncertainFlow(ppcImlGenContext_t& ppcImlGenContext
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{
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cemu_assert_debug(segIt->GetBranchNotTaken());
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}
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//// find destination segment by ppc jump address
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//IMLSegment* jumpDestSegment = PPCRecompiler_getSegmentByPPCJumpAddress(ppcImlGenContext, imlInstruction->op_conditionalJump.jumpmarkAddress);
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//if (jumpDestSegment)
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//{
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// if (imlInstruction->op_conditionalJump.condition != PPCREC_JUMP_CONDITION_NONE)
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// IMLSegment_SetLinkBranchNotTaken(imlSegment, nextSegment);
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// IMLSegment_SetLinkBranchTaken(imlSegment, jumpDestSegment);
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//}
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//else
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//{
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// imlSegment->nextSegmentIsUncertain = true;
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//}
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}
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else if (imlInstruction->type == PPCREC_IML_TYPE_MACRO)
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{
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auto macroType = imlInstruction->operation;
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switch (macroType)
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{
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case PPCREC_IML_MACRO_BLR:
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case PPCREC_IML_MACRO_BLRL:
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case PPCREC_IML_MACRO_BCTR:
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case PPCREC_IML_MACRO_BCTRL:
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case PPCREC_IML_MACRO_B_TO_REG:
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case PPCREC_IML_MACRO_BL:
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case PPCREC_IML_MACRO_B_FAR:
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case PPCREC_IML_MACRO_HLE:
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@ -4500,7 +4353,7 @@ bool PPCRecompiler_GenerateIML(ppcImlGenContext_t& ppcImlGenContext, PPCFunction
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{
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if (seg->imlList[f].IsSuffixInstruction())
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{
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debug_printf("---------------- SegmentDump (Suffix instruction at wrong pos in segment 0x%x):\n", segIndex);
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debug_printf("---------------- SegmentDump (Suffix instruction at wrong pos in segment 0x%x):\n", (int)segIndex);
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IMLDebug_Dump(&ppcImlGenContext);
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__debugbreak();
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}
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@ -4510,7 +4363,7 @@ bool PPCRecompiler_GenerateIML(ppcImlGenContext_t& ppcImlGenContext, PPCFunction
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{
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if (!seg->HasSuffixInstruction())
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{
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debug_printf("---------------- SegmentDump (NoSuffixInstruction in segment 0x%x):\n", segIndex);
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debug_printf("---------------- SegmentDump (NoSuffixInstruction in segment 0x%x):\n", (int)segIndex);
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IMLDebug_Dump(&ppcImlGenContext);
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__debugbreak();
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||||
}
|
||||
|
|
@ -4540,7 +4393,7 @@ bool PPCRecompiler_GenerateIML(ppcImlGenContext_t& ppcImlGenContext, PPCFunction
|
|||
{
|
||||
if (!seg->GetBranchTaken() || !seg->GetBranchNotTaken())
|
||||
{
|
||||
debug_printf("---------------- SegmentDump (Missing branch for CJUMP in segment 0x%x):\n", segIndex);
|
||||
debug_printf("---------------- SegmentDump (Missing branch for CJUMP in segment 0x%x):\n", (int)segIndex);
|
||||
IMLDebug_Dump(&ppcImlGenContext);
|
||||
cemu_assert_error();
|
||||
}
|
||||
|
|
@ -4551,10 +4404,6 @@ bool PPCRecompiler_GenerateIML(ppcImlGenContext_t& ppcImlGenContext, PPCFunction
|
|||
}
|
||||
}
|
||||
}
|
||||
//if (seg->list_prevSegments.empty())
|
||||
//{
|
||||
// cemu_assert_debug(seg->isEnterable);
|
||||
//}
|
||||
segIndex++;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue