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PowerPC recompiler rework (#641)
This commit is contained in:
Exzap
GitHub
parent
06233e3462
commit
b089ae5b32
54 changed files with 15433 additions and 12397 deletions
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@ -1,275 +1,29 @@
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bool PPCRecompiler_generateIntermediateCode(ppcImlGenContext_t& ppcImlGenContext, PPCRecFunction_t* PPCRecFunction, std::set<uint32>& entryAddresses, class PPCFunctionBoundaryTracker& boundaryTracker);
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#define PPCREC_CR_REG_TEMP 8 // there are only 8 cr registers (0-7) we use the 8th as temporary cr register that is never stored (BDNZ instruction for example)
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IMLSegment* PPCIMLGen_CreateSplitSegmentAtEnd(ppcImlGenContext_t& ppcImlGenContext, PPCBasicBlockInfo& basicBlockInfo);
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IMLSegment* PPCIMLGen_CreateNewSegmentAsBranchTarget(ppcImlGenContext_t& ppcImlGenContext, PPCBasicBlockInfo& basicBlockInfo);
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enum
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{
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PPCREC_IML_OP_ASSIGN, // '=' operator
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PPCREC_IML_OP_ENDIAN_SWAP, // '=' operator with 32bit endian swap
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PPCREC_IML_OP_ADD, // '+' operator
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PPCREC_IML_OP_SUB, // '-' operator
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PPCREC_IML_OP_SUB_CARRY_UPDATE_CARRY, // complex operation, result = operand + ~operand2 + carry bit, updates carry bit
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PPCREC_IML_OP_COMPARE_SIGNED, // arithmetic/signed comparison operator (updates cr)
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PPCREC_IML_OP_COMPARE_UNSIGNED, // logical/unsigned comparison operator (updates cr)
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PPCREC_IML_OP_MULTIPLY_SIGNED, // '*' operator (signed multiply)
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PPCREC_IML_OP_MULTIPLY_HIGH_UNSIGNED, // unsigned 64bit multiply, store only high 32bit-word of result
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PPCREC_IML_OP_MULTIPLY_HIGH_SIGNED, // signed 64bit multiply, store only high 32bit-word of result
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PPCREC_IML_OP_DIVIDE_SIGNED, // '/' operator (signed divide)
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PPCREC_IML_OP_DIVIDE_UNSIGNED, // '/' operator (unsigned divide)
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PPCREC_IML_OP_ADD_CARRY, // complex operation, result = operand + carry bit, updates carry bit
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PPCREC_IML_OP_ADD_CARRY_ME, // complex operation, result = operand + carry bit + (-1), updates carry bit
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PPCREC_IML_OP_ADD_UPDATE_CARRY, // '+' operator but also updates carry flag
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PPCREC_IML_OP_ADD_CARRY_UPDATE_CARRY, // '+' operator and also adds carry, updates carry flag
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// assign operators with cast
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PPCREC_IML_OP_ASSIGN_S16_TO_S32, // copy 16bit and sign extend
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PPCREC_IML_OP_ASSIGN_S8_TO_S32, // copy 8bit and sign extend
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// binary operation
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PPCREC_IML_OP_OR, // '|' operator
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PPCREC_IML_OP_ORC, // '|' operator, second operand is complemented first
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PPCREC_IML_OP_AND, // '&' operator
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PPCREC_IML_OP_XOR, // '^' operator
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PPCREC_IML_OP_LEFT_ROTATE, // left rotate operator
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PPCREC_IML_OP_LEFT_SHIFT, // shift left operator
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PPCREC_IML_OP_RIGHT_SHIFT, // right shift operator (unsigned)
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PPCREC_IML_OP_NOT, // complement each bit
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PPCREC_IML_OP_NEG, // negate
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// ppc
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PPCREC_IML_OP_RLWIMI, // RLWIMI instruction (rotate, merge based on mask)
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PPCREC_IML_OP_SRAW, // SRAWI/SRAW instruction (algebraic shift right, sets ca flag)
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PPCREC_IML_OP_SLW, // SLW (shift based on register by up to 63 bits)
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PPCREC_IML_OP_SRW, // SRW (shift based on register by up to 63 bits)
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PPCREC_IML_OP_CNTLZW,
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PPCREC_IML_OP_SUBFC, // SUBFC and SUBFIC (subtract from and set carry)
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PPCREC_IML_OP_DCBZ, // clear 32 bytes aligned to 0x20
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PPCREC_IML_OP_MFCR, // copy cr to gpr
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PPCREC_IML_OP_MTCRF, // copy gpr to cr (with mask)
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// condition register
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PPCREC_IML_OP_CR_CLEAR, // clear cr bit
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PPCREC_IML_OP_CR_SET, // set cr bit
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PPCREC_IML_OP_CR_OR, // OR cr bits
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PPCREC_IML_OP_CR_ORC, // OR cr bits, complement second input operand bit first
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PPCREC_IML_OP_CR_AND, // AND cr bits
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PPCREC_IML_OP_CR_ANDC, // AND cr bits, complement second input operand bit first
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// FPU
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PPCREC_IML_OP_FPR_ADD_BOTTOM,
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PPCREC_IML_OP_FPR_ADD_PAIR,
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PPCREC_IML_OP_FPR_SUB_PAIR,
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PPCREC_IML_OP_FPR_SUB_BOTTOM,
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PPCREC_IML_OP_FPR_MULTIPLY_BOTTOM,
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PPCREC_IML_OP_FPR_MULTIPLY_PAIR,
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PPCREC_IML_OP_FPR_DIVIDE_BOTTOM,
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PPCREC_IML_OP_FPR_DIVIDE_PAIR,
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PPCREC_IML_OP_FPR_COPY_BOTTOM_TO_BOTTOM_AND_TOP,
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PPCREC_IML_OP_FPR_COPY_TOP_TO_BOTTOM_AND_TOP,
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PPCREC_IML_OP_FPR_COPY_BOTTOM_TO_BOTTOM,
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PPCREC_IML_OP_FPR_COPY_BOTTOM_TO_TOP, // leave bottom of destination untouched
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PPCREC_IML_OP_FPR_COPY_TOP_TO_TOP, // leave bottom of destination untouched
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PPCREC_IML_OP_FPR_COPY_TOP_TO_BOTTOM, // leave top of destination untouched
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PPCREC_IML_OP_FPR_COPY_BOTTOM_AND_TOP_SWAPPED,
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PPCREC_IML_OP_FPR_EXPAND_BOTTOM32_TO_BOTTOM64_AND_TOP64, // expand bottom f32 to f64 in bottom and top half
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PPCREC_IML_OP_FPR_BOTTOM_FRES_TO_BOTTOM_AND_TOP, // calculate reciprocal with Espresso accuracy of source bottom half and write result to destination bottom and top half
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PPCREC_IML_OP_FPR_FCMPO_BOTTOM,
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PPCREC_IML_OP_FPR_FCMPU_BOTTOM,
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PPCREC_IML_OP_FPR_FCMPU_TOP,
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PPCREC_IML_OP_FPR_NEGATE_BOTTOM,
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PPCREC_IML_OP_FPR_NEGATE_PAIR,
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PPCREC_IML_OP_FPR_ABS_BOTTOM, // abs(fp0)
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PPCREC_IML_OP_FPR_ABS_PAIR,
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PPCREC_IML_OP_FPR_FRES_PAIR, // 1.0/fp approx (Espresso accuracy)
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PPCREC_IML_OP_FPR_FRSQRTE_PAIR, // 1.0/sqrt(fp) approx (Espresso accuracy)
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PPCREC_IML_OP_FPR_NEGATIVE_ABS_BOTTOM, // -abs(fp0)
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PPCREC_IML_OP_FPR_ROUND_TO_SINGLE_PRECISION_BOTTOM, // round 64bit double to 64bit double with 32bit float precision (in bottom half of xmm register)
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PPCREC_IML_OP_FPR_ROUND_TO_SINGLE_PRECISION_PAIR, // round two 64bit doubles to 64bit double with 32bit float precision
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PPCREC_IML_OP_FPR_BOTTOM_RECIPROCAL_SQRT,
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PPCREC_IML_OP_FPR_BOTTOM_FCTIWZ,
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PPCREC_IML_OP_FPR_SELECT_BOTTOM, // selectively copy bottom value from operand B or C based on value in operand A
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PPCREC_IML_OP_FPR_SELECT_PAIR, // selectively copy top/bottom from operand B or C based on value in top/bottom of operand A
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// PS
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PPCREC_IML_OP_FPR_SUM0,
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PPCREC_IML_OP_FPR_SUM1,
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};
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void PPCIMLGen_AssertIfNotLastSegmentInstruction(ppcImlGenContext_t& ppcImlGenContext);
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#define PPCREC_IML_OP_FPR_COPY_PAIR (PPCREC_IML_OP_ASSIGN)
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enum
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{
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PPCREC_IML_MACRO_BLR, // macro for BLR instruction code
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PPCREC_IML_MACRO_BLRL, // macro for BLRL instruction code
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PPCREC_IML_MACRO_BCTR, // macro for BCTR instruction code
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PPCREC_IML_MACRO_BCTRL, // macro for BCTRL instruction code
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PPCREC_IML_MACRO_BL, // call to different function (can be within same function)
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PPCREC_IML_MACRO_B_FAR, // branch to different function
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PPCREC_IML_MACRO_COUNT_CYCLES, // decrease current remaining thread cycles by a certain amount
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PPCREC_IML_MACRO_HLE, // HLE function call
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PPCREC_IML_MACRO_MFTB, // get TB register value (low or high)
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PPCREC_IML_MACRO_LEAVE, // leaves recompiler and switches to interpeter
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// debugging
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PPCREC_IML_MACRO_DEBUGBREAK, // throws a debugbreak
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};
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enum
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{
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PPCREC_JUMP_CONDITION_NONE,
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PPCREC_JUMP_CONDITION_E, // equal / zero
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PPCREC_JUMP_CONDITION_NE, // not equal / not zero
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PPCREC_JUMP_CONDITION_LE, // less or equal
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PPCREC_JUMP_CONDITION_L, // less
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PPCREC_JUMP_CONDITION_GE, // greater or equal
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PPCREC_JUMP_CONDITION_G, // greater
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// special case:
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PPCREC_JUMP_CONDITION_SUMMARYOVERFLOW, // needs special handling
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PPCREC_JUMP_CONDITION_NSUMMARYOVERFLOW, // not summaryoverflow
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};
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enum
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{
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PPCREC_CR_MODE_COMPARE_SIGNED,
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PPCREC_CR_MODE_COMPARE_UNSIGNED, // alias logic compare
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// others: PPCREC_CR_MODE_ARITHMETIC,
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PPCREC_CR_MODE_ARITHMETIC, // arithmetic use (for use with add/sub instructions without generating extra code)
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PPCREC_CR_MODE_LOGICAL,
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};
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enum
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{
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PPCREC_IML_TYPE_NONE,
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PPCREC_IML_TYPE_NO_OP, // no-op instruction
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PPCREC_IML_TYPE_JUMPMARK, // possible jump destination (generated before each ppc instruction)
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PPCREC_IML_TYPE_R_R, // r* (op) *r
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PPCREC_IML_TYPE_R_R_R, // r* = r* (op) r*
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PPCREC_IML_TYPE_R_R_S32, // r* = r* (op) s32*
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PPCREC_IML_TYPE_LOAD, // r* = [r*+s32*]
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PPCREC_IML_TYPE_LOAD_INDEXED, // r* = [r*+r*]
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PPCREC_IML_TYPE_STORE, // [r*+s32*] = r*
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PPCREC_IML_TYPE_STORE_INDEXED, // [r*+r*] = r*
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PPCREC_IML_TYPE_R_NAME, // r* = name
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PPCREC_IML_TYPE_NAME_R, // name* = r*
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PPCREC_IML_TYPE_R_S32, // r* (op) imm
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PPCREC_IML_TYPE_MACRO,
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PPCREC_IML_TYPE_CJUMP, // conditional jump
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PPCREC_IML_TYPE_CJUMP_CYCLE_CHECK, // jumps only if remaining thread cycles >= 0
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PPCREC_IML_TYPE_PPC_ENTER, // used to mark locations that should be written to recompilerCallTable
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PPCREC_IML_TYPE_CR, // condition register specific operations (one or more operands)
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// conditional
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PPCREC_IML_TYPE_CONDITIONAL_R_S32,
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// FPR
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PPCREC_IML_TYPE_FPR_R_NAME, // name = f*
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PPCREC_IML_TYPE_FPR_NAME_R, // f* = name
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PPCREC_IML_TYPE_FPR_LOAD, // r* = (bitdepth) [r*+s32*] (single or paired single mode)
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PPCREC_IML_TYPE_FPR_LOAD_INDEXED, // r* = (bitdepth) [r*+r*] (single or paired single mode)
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PPCREC_IML_TYPE_FPR_STORE, // (bitdepth) [r*+s32*] = r* (single or paired single mode)
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PPCREC_IML_TYPE_FPR_STORE_INDEXED, // (bitdepth) [r*+r*] = r* (single or paired single mode)
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PPCREC_IML_TYPE_FPR_R_R,
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PPCREC_IML_TYPE_FPR_R_R_R,
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PPCREC_IML_TYPE_FPR_R_R_R_R,
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PPCREC_IML_TYPE_FPR_R,
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// special
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PPCREC_IML_TYPE_MEM2MEM, // memory to memory copy (deprecated)
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};
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enum
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{
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PPCREC_NAME_NONE,
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PPCREC_NAME_TEMPORARY,
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PPCREC_NAME_R0 = 1000,
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PPCREC_NAME_SPR0 = 2000,
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PPCREC_NAME_FPR0 = 3000,
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PPCREC_NAME_TEMPORARY_FPR0 = 4000, // 0 to 7
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//PPCREC_NAME_CR0 = 3000, // value mapped condition register (usually it isn't needed and can be optimized away)
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};
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// special cases for LOAD/STORE
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#define PPC_REC_LOAD_LWARX_MARKER (100) // lwarx instruction (similar to LWZX but sets reserved address/value)
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#define PPC_REC_STORE_STWCX_MARKER (100) // stwcx instruction (similar to STWX but writes only if reservation from LWARX is valid)
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#define PPC_REC_STORE_STSWI_1 (200) // stswi nb = 1
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#define PPC_REC_STORE_STSWI_2 (201) // stswi nb = 2
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#define PPC_REC_STORE_STSWI_3 (202) // stswi nb = 3
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#define PPC_REC_STORE_LSWI_1 (200) // lswi nb = 1
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#define PPC_REC_STORE_LSWI_2 (201) // lswi nb = 2
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#define PPC_REC_STORE_LSWI_3 (202) // lswi nb = 3
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#define PPC_REC_INVALID_REGISTER 0xFF
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#define PPCREC_CR_BIT_LT 0
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#define PPCREC_CR_BIT_GT 1
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#define PPCREC_CR_BIT_EQ 2
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#define PPCREC_CR_BIT_SO 3
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enum
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{
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// fpr load
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PPCREC_FPR_LD_MODE_SINGLE_INTO_PS0,
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PPCREC_FPR_LD_MODE_SINGLE_INTO_PS0_PS1,
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PPCREC_FPR_LD_MODE_DOUBLE_INTO_PS0,
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PPCREC_FPR_LD_MODE_PSQ_GENERIC_PS0,
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PPCREC_FPR_LD_MODE_PSQ_GENERIC_PS0_PS1,
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PPCREC_FPR_LD_MODE_PSQ_FLOAT_PS0,
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PPCREC_FPR_LD_MODE_PSQ_FLOAT_PS0_PS1,
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PPCREC_FPR_LD_MODE_PSQ_S16_PS0,
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PPCREC_FPR_LD_MODE_PSQ_S16_PS0_PS1,
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PPCREC_FPR_LD_MODE_PSQ_U16_PS0,
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PPCREC_FPR_LD_MODE_PSQ_U16_PS0_PS1,
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PPCREC_FPR_LD_MODE_PSQ_S8_PS0,
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PPCREC_FPR_LD_MODE_PSQ_S8_PS0_PS1,
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PPCREC_FPR_LD_MODE_PSQ_U8_PS0,
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PPCREC_FPR_LD_MODE_PSQ_U8_PS0_PS1,
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// fpr store
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PPCREC_FPR_ST_MODE_SINGLE_FROM_PS0, // store 1 single precision float from ps0
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PPCREC_FPR_ST_MODE_DOUBLE_FROM_PS0, // store 1 double precision float from ps0
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PPCREC_FPR_ST_MODE_UI32_FROM_PS0, // store raw low-32bit of PS0
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PPCREC_FPR_ST_MODE_PSQ_GENERIC_PS0_PS1,
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PPCREC_FPR_ST_MODE_PSQ_GENERIC_PS0,
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PPCREC_FPR_ST_MODE_PSQ_FLOAT_PS0_PS1,
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PPCREC_FPR_ST_MODE_PSQ_FLOAT_PS0,
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PPCREC_FPR_ST_MODE_PSQ_S8_PS0,
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PPCREC_FPR_ST_MODE_PSQ_S8_PS0_PS1,
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PPCREC_FPR_ST_MODE_PSQ_U8_PS0,
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PPCREC_FPR_ST_MODE_PSQ_U8_PS0_PS1,
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PPCREC_FPR_ST_MODE_PSQ_U16_PS0,
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PPCREC_FPR_ST_MODE_PSQ_U16_PS0_PS1,
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PPCREC_FPR_ST_MODE_PSQ_S16_PS0,
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PPCREC_FPR_ST_MODE_PSQ_S16_PS0_PS1,
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};
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bool PPCRecompiler_generateIntermediateCode(ppcImlGenContext_t& ppcImlGenContext, PPCRecFunction_t* PPCRecFunction, std::set<uint32>& entryAddresses);
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void PPCRecompiler_freeContext(ppcImlGenContext_t* ppcImlGenContext); // todo - move to destructor
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PPCRecImlInstruction_t* PPCRecompilerImlGen_generateNewEmptyInstruction(ppcImlGenContext_t* ppcImlGenContext);
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void PPCRecompiler_pushBackIMLInstructions(PPCRecImlSegment_t* imlSegment, sint32 index, sint32 shiftBackCount);
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PPCRecImlInstruction_t* PPCRecompiler_insertInstruction(PPCRecImlSegment_t* imlSegment, sint32 index);
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IMLInstruction* PPCRecompilerImlGen_generateNewEmptyInstruction(ppcImlGenContext_t* ppcImlGenContext);
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void PPCRecompiler_pushBackIMLInstructions(IMLSegment* imlSegment, sint32 index, sint32 shiftBackCount);
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IMLInstruction* PPCRecompiler_insertInstruction(IMLSegment* imlSegment, sint32 index);
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void PPCRecompilerIml_insertSegments(ppcImlGenContext_t* ppcImlGenContext, sint32 index, sint32 count);
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void PPCRecompilerIml_setSegmentPoint(ppcRecompilerSegmentPoint_t* segmentPoint, PPCRecImlSegment_t* imlSegment, sint32 index);
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void PPCRecompilerIml_removeSegmentPoint(ppcRecompilerSegmentPoint_t* segmentPoint);
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void PPCRecompilerIml_setSegmentPoint(IMLSegmentPoint* segmentPoint, IMLSegment* imlSegment, sint32 index);
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void PPCRecompilerIml_removeSegmentPoint(IMLSegmentPoint* segmentPoint);
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// GPR register management
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uint32 PPCRecompilerImlGen_loadRegister(ppcImlGenContext_t* ppcImlGenContext, uint32 mappedName, bool loadNew = false);
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uint32 PPCRecompilerImlGen_loadOverwriteRegister(ppcImlGenContext_t* ppcImlGenContext, uint32 mappedName);
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IMLReg PPCRecompilerImlGen_loadRegister(ppcImlGenContext_t* ppcImlGenContext, uint32 mappedName);
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// FPR register management
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uint32 PPCRecompilerImlGen_loadFPRRegister(ppcImlGenContext_t* ppcImlGenContext, uint32 mappedName, bool loadNew = false);
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uint32 PPCRecompilerImlGen_loadOverwriteFPRRegister(ppcImlGenContext_t* ppcImlGenContext, uint32 mappedName);
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IMLReg PPCRecompilerImlGen_loadFPRRegister(ppcImlGenContext_t* ppcImlGenContext, uint32 mappedName, bool loadNew = false);
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IMLReg PPCRecompilerImlGen_loadOverwriteFPRRegister(ppcImlGenContext_t* ppcImlGenContext, uint32 mappedName);
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// IML instruction generation
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void PPCRecompilerImlGen_generateNewInstruction_jump(ppcImlGenContext_t* ppcImlGenContext, PPCRecImlInstruction_t* imlInstruction, uint32 jumpmarkAddress);
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void PPCRecompilerImlGen_generateNewInstruction_jumpSegment(ppcImlGenContext_t* ppcImlGenContext, PPCRecImlInstruction_t* imlInstruction);
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void PPCRecompilerImlGen_generateNewInstruction_r_s32(ppcImlGenContext_t* ppcImlGenContext, uint32 operation, uint8 registerIndex, sint32 immS32, uint32 copyWidth, bool signExtend, bool bigEndian, uint8 crRegister, uint32 crMode);
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void PPCRecompilerImlGen_generateNewInstruction_conditional_r_s32(ppcImlGenContext_t* ppcImlGenContext, PPCRecImlInstruction_t* imlInstruction, uint32 operation, uint8 registerIndex, sint32 immS32, uint32 crRegisterIndex, uint32 crBitIndex, bool bitMustBeSet);
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void PPCRecompilerImlGen_generateNewInstruction_r_r(ppcImlGenContext_t* ppcImlGenContext, PPCRecImlInstruction_t* imlInstruction, uint32 operation, uint8 registerResult, uint8 registerA, uint8 crRegister = PPC_REC_INVALID_REGISTER, uint8 crMode = 0);
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// IML instruction generation (new style, can generate new instructions but also overwrite existing ones)
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void PPCRecompilerImlGen_generateNewInstruction_noOp(ppcImlGenContext_t* ppcImlGenContext, PPCRecImlInstruction_t* imlInstruction);
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void PPCRecompilerImlGen_generateNewInstruction_memory_memory(ppcImlGenContext_t* ppcImlGenContext, PPCRecImlInstruction_t* imlInstruction, uint8 srcMemReg, sint32 srcImmS32, uint8 dstMemReg, sint32 dstImmS32, uint8 copyWidth);
|
||||
|
||||
void PPCRecompilerImlGen_generateNewInstruction_fpr_r(ppcImlGenContext_t* ppcImlGenContext, PPCRecImlInstruction_t* imlInstruction, sint32 operation, uint8 registerResult, sint32 crRegister = PPC_REC_INVALID_REGISTER);
|
||||
void PPCRecompilerImlGen_generateNewInstruction_conditional_r_s32(ppcImlGenContext_t* ppcImlGenContext, IMLInstruction* imlInstruction, uint32 operation, IMLReg registerIndex, sint32 immS32, uint32 crRegisterIndex, uint32 crBitIndex, bool bitMustBeSet);
|
||||
void PPCRecompilerImlGen_generateNewInstruction_fpr_r(ppcImlGenContext_t* ppcImlGenContext, IMLInstruction* imlInstruction, sint32 operation, IMLReg registerResult);
|
||||
|
||||
// IML generation - FPU
|
||||
bool PPCRecompilerImlGen_LFS(ppcImlGenContext_t* ppcImlGenContext, uint32 opcode);
|
||||
|
|
@ -347,76 +101,4 @@ bool PPCRecompilerImlGen_PS_CMPU1(ppcImlGenContext_t* ppcImlGenContext, uint32 o
|
|||
|
||||
// IML general
|
||||
|
||||
bool PPCRecompiler_isSuffixInstruction(PPCRecImlInstruction_t* iml);
|
||||
void PPCRecompilerIML_linkSegments(ppcImlGenContext_t* ppcImlGenContext);
|
||||
void PPCRecompilerIml_setLinkBranchNotTaken(PPCRecImlSegment_t* imlSegmentSrc, PPCRecImlSegment_t* imlSegmentDst);
|
||||
void PPCRecompilerIml_setLinkBranchTaken(PPCRecImlSegment_t* imlSegmentSrc, PPCRecImlSegment_t* imlSegmentDst);
|
||||
void PPCRecompilerIML_relinkInputSegment(PPCRecImlSegment_t* imlSegmentOrig, PPCRecImlSegment_t* imlSegmentNew);
|
||||
void PPCRecompilerIML_removeLink(PPCRecImlSegment_t* imlSegmentSrc, PPCRecImlSegment_t* imlSegmentDst);
|
||||
void PPCRecompilerIML_isolateEnterableSegments(ppcImlGenContext_t* ppcImlGenContext);
|
||||
|
||||
PPCRecImlInstruction_t* PPCRecompilerIML_getLastInstruction(PPCRecImlSegment_t* imlSegment);
|
||||
|
||||
// IML analyzer
|
||||
typedef struct
|
||||
{
|
||||
uint32 readCRBits;
|
||||
uint32 writtenCRBits;
|
||||
}PPCRecCRTracking_t;
|
||||
|
||||
bool PPCRecompilerImlAnalyzer_isTightFiniteLoop(PPCRecImlSegment_t* imlSegment);
|
||||
bool PPCRecompilerImlAnalyzer_canTypeWriteCR(PPCRecImlInstruction_t* imlInstruction);
|
||||
void PPCRecompilerImlAnalyzer_getCRTracking(PPCRecImlInstruction_t* imlInstruction, PPCRecCRTracking_t* crTracking);
|
||||
|
||||
// IML optimizer
|
||||
bool PPCRecompiler_reduceNumberOfFPRRegisters(ppcImlGenContext_t* ppcImlGenContext);
|
||||
|
||||
bool PPCRecompiler_manageFPRRegisters(ppcImlGenContext_t* ppcImlGenContext);
|
||||
|
||||
void PPCRecompiler_removeRedundantCRUpdates(ppcImlGenContext_t* ppcImlGenContext);
|
||||
void PPCRecompiler_optimizeDirectFloatCopies(ppcImlGenContext_t* ppcImlGenContext);
|
||||
void PPCRecompiler_optimizeDirectIntegerCopies(ppcImlGenContext_t* ppcImlGenContext);
|
||||
|
||||
void PPCRecompiler_optimizePSQLoadAndStore(ppcImlGenContext_t* ppcImlGenContext);
|
||||
|
||||
// IML register allocator
|
||||
void PPCRecompilerImm_allocateRegisters(ppcImlGenContext_t* ppcImlGenContext);
|
||||
|
||||
// late optimizations
|
||||
void PPCRecompiler_reorderConditionModifyInstructions(ppcImlGenContext_t* ppcImlGenContext);
|
||||
|
||||
// debug
|
||||
|
||||
void PPCRecompiler_dumpIMLSegment(PPCRecImlSegment_t* imlSegment, sint32 segmentIndex, bool printLivenessRangeInfo = false);
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
sint16 readNamedReg1;
|
||||
sint16 readNamedReg2;
|
||||
sint16 readNamedReg3;
|
||||
sint16 writtenNamedReg1;
|
||||
};
|
||||
sint16 gpr[4]; // 3 read + 1 write
|
||||
};
|
||||
// FPR
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
// note: If destination operand is not fully written, it will be added as a read FPR as well
|
||||
sint16 readFPR1;
|
||||
sint16 readFPR2;
|
||||
sint16 readFPR3;
|
||||
sint16 readFPR4; // usually this is set to the result FPR if only partially overwritten
|
||||
sint16 writtenFPR1;
|
||||
};
|
||||
sint16 fpr[4];
|
||||
};
|
||||
}PPCImlOptimizerUsedRegisters_t;
|
||||
|
||||
void PPCRecompiler_checkRegisterUsage(ppcImlGenContext_t* ppcImlGenContext, PPCRecImlInstruction_t* imlInstruction, PPCImlOptimizerUsedRegisters_t* registersUsed);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue