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https://github.com/cemu-project/Cemu.git
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PowerPC recompiler rework (#641)
This commit is contained in:
Exzap
GitHub
parent
06233e3462
commit
b089ae5b32
54 changed files with 15433 additions and 12397 deletions
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@ -1,4 +1,4 @@
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#include <vector>
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#pragma once
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#define PPC_REC_CODE_AREA_START (0x00000000) // lower bound of executable memory area. Recompiler expects this address to be 0
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#define PPC_REC_CODE_AREA_END (0x10000000) // upper bound of executable memory area
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@ -6,336 +6,113 @@
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#define PPC_REC_ALIGN_TO_4MB(__v) (((__v)+4*1024*1024-1)&~(4*1024*1024-1))
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#define PPC_REC_MAX_VIRTUAL_GPR (40) // enough to store 32 GPRs + a few SPRs + temp registers (usually only 1-2)
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#define PPC_REC_MAX_VIRTUAL_GPR (40 + 32) // enough to store 32 GPRs + a few SPRs + temp registers (usually only 1-2)
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typedef struct
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struct ppcRecRange_t
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{
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uint32 ppcAddress;
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uint32 ppcSize;
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//void* x86Start;
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//size_t x86Size;
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void* storedRange;
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}ppcRecRange_t;
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};
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typedef struct
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struct PPCRecFunction_t
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{
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uint32 ppcAddress;
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uint32 ppcSize; // ppc code size of function
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void* x86Code; // pointer to x86 code
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size_t x86Size;
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std::vector<ppcRecRange_t> list_ranges;
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}PPCRecFunction_t;
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#define PPCREC_IML_OP_FLAG_SIGNEXTEND (1<<0)
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#define PPCREC_IML_OP_FLAG_SWITCHENDIAN (1<<1)
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#define PPCREC_IML_OP_FLAG_NOT_EXPANDED (1<<2) // set single-precision load instructions to indicate that the value should not be rounded to double-precision
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#define PPCREC_IML_OP_FLAG_UNUSED (1<<7) // used to mark instructions that are not used
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typedef struct
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{
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uint8 type;
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uint8 operation;
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uint8 crRegister; // set to 0xFF if not set, not all IML instruction types support cr.
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uint8 crMode; // only used when crRegister is valid, used to differentiate between various forms of condition flag set/clear behavior
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uint32 crIgnoreMask; // bit set for every respective CR bit that doesn't need to be updated
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uint32 associatedPPCAddress; // ppc address that is associated with this instruction
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union
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{
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struct
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{
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uint8 _padding[7];
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}padding;
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struct
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{
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// R (op) A [update cr* in mode *]
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uint8 registerResult;
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uint8 registerA;
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}op_r_r;
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struct
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{
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// R = A (op) B [update cr* in mode *]
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uint8 registerResult;
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uint8 registerA;
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uint8 registerB;
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}op_r_r_r;
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struct
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{
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// R = A (op) immS32 [update cr* in mode *]
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uint8 registerResult;
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uint8 registerA;
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sint32 immS32;
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}op_r_r_s32;
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struct
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{
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// R/F = NAME or NAME = R/F
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uint8 registerIndex;
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uint8 copyWidth;
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uint32 name;
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uint8 flags;
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}op_r_name;
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struct
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{
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// R (op) s32 [update cr* in mode *]
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uint8 registerIndex;
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sint32 immS32;
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}op_r_immS32;
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struct
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{
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uint32 address;
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uint8 flags;
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}op_jumpmark;
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struct
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{
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uint32 param;
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uint32 param2;
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uint16 paramU16;
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}op_macro;
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struct
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{
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uint32 jumpmarkAddress;
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bool jumpAccordingToSegment; //PPCRecImlSegment_t* destinationSegment; // if set, this replaces jumpmarkAddress
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uint8 condition; // only used when crRegisterIndex is 8 or above (update: Apparently only used to mark jumps without a condition? -> Cleanup)
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uint8 crRegisterIndex;
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uint8 crBitIndex;
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bool bitMustBeSet;
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}op_conditionalJump;
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struct
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{
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uint8 registerData;
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uint8 registerMem;
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uint8 registerMem2;
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uint8 registerGQR;
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uint8 copyWidth;
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//uint8 flags;
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struct
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{
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bool swapEndian : 1;
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bool signExtend : 1;
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bool notExpanded : 1; // for floats
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}flags2;
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uint8 mode; // transfer mode (copy width, ps0/ps1 behavior)
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sint32 immS32;
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}op_storeLoad;
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struct
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{
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struct
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{
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uint8 registerMem;
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sint32 immS32;
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}src;
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struct
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{
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uint8 registerMem;
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sint32 immS32;
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}dst;
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uint8 copyWidth;
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}op_mem2mem;
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struct
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{
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uint8 registerResult;
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uint8 registerOperand;
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uint8 flags;
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}op_fpr_r_r;
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struct
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{
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uint8 registerResult;
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uint8 registerOperandA;
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uint8 registerOperandB;
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uint8 flags;
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}op_fpr_r_r_r;
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struct
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{
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uint8 registerResult;
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uint8 registerOperandA;
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uint8 registerOperandB;
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uint8 registerOperandC;
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uint8 flags;
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}op_fpr_r_r_r_r;
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struct
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{
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uint8 registerResult;
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//uint8 flags;
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}op_fpr_r;
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struct
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{
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uint32 ppcAddress;
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uint32 x64Offset;
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}op_ppcEnter;
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struct
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{
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uint8 crD; // crBitIndex (result)
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uint8 crA; // crBitIndex
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uint8 crB; // crBitIndex
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}op_cr;
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// conditional operations (emitted if supported by target platform)
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struct
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{
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// r_s32
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uint8 registerIndex;
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sint32 immS32;
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// condition
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uint8 crRegisterIndex;
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uint8 crBitIndex;
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bool bitMustBeSet;
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}op_conditional_r_s32;
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};
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}PPCRecImlInstruction_t;
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typedef struct _PPCRecImlSegment_t PPCRecImlSegment_t;
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typedef struct _ppcRecompilerSegmentPoint_t
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{
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sint32 index;
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PPCRecImlSegment_t* imlSegment;
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_ppcRecompilerSegmentPoint_t* next;
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_ppcRecompilerSegmentPoint_t* prev;
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}ppcRecompilerSegmentPoint_t;
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struct raLivenessLocation_t
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{
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sint32 index;
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bool isRead;
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bool isWrite;
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raLivenessLocation_t() = default;
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raLivenessLocation_t(sint32 index, bool isRead, bool isWrite)
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: index(index), isRead(isRead), isWrite(isWrite) {};
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};
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struct raLivenessSubrangeLink_t
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{
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struct raLivenessSubrange_t* prev;
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struct raLivenessSubrange_t* next;
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};
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#include "Cafe/HW/Espresso/Recompiler/IML/IMLInstruction.h"
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#include "Cafe/HW/Espresso/Recompiler/IML/IMLSegment.h"
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struct raLivenessSubrange_t
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{
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struct raLivenessRange_t* range;
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PPCRecImlSegment_t* imlSegment;
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ppcRecompilerSegmentPoint_t start;
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ppcRecompilerSegmentPoint_t end;
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// dirty state tracking
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bool _noLoad;
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bool hasStore;
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bool hasStoreDelayed;
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// next
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raLivenessSubrange_t* subrangeBranchTaken;
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raLivenessSubrange_t* subrangeBranchNotTaken;
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// processing
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uint32 lastIterationIndex;
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// instruction locations
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std::vector<raLivenessLocation_t> list_locations;
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// linked list (subranges with same GPR virtual register)
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raLivenessSubrangeLink_t link_sameVirtualRegisterGPR;
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// linked list (all subranges for this segment)
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raLivenessSubrangeLink_t link_segmentSubrangesGPR;
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};
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struct raLivenessRange_t
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{
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sint32 virtualRegister;
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sint32 physicalRegister;
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sint32 name;
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std::vector<raLivenessSubrange_t*> list_subranges;
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};
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struct PPCSegmentRegisterAllocatorInfo_t
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{
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// analyzer stage
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bool isPartOfProcessedLoop{}; // used during loop detection
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sint32 lastIterationIndex{};
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// linked lists
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raLivenessSubrange_t* linkedList_allSubranges{};
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raLivenessSubrange_t* linkedList_perVirtualGPR[PPC_REC_MAX_VIRTUAL_GPR]{};
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};
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struct PPCRecVGPRDistances_t
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{
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struct _RegArrayEntry
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{
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sint32 usageStart{};
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sint32 usageEnd{};
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}reg[PPC_REC_MAX_VIRTUAL_GPR];
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bool isProcessed[PPC_REC_MAX_VIRTUAL_GPR]{};
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};
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typedef struct _PPCRecImlSegment_t
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{
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sint32 momentaryIndex{}; // index in segment list, generally not kept up to date except if needed (necessary for loop detection)
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sint32 startOffset{}; // offset to first instruction in iml instruction list
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sint32 count{}; // number of instructions in segment
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uint32 ppcAddress{}; // ppc address (0xFFFFFFFF if not associated with an address)
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uint32 x64Offset{}; // x64 code offset of segment start
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uint32 cycleCount{}; // number of PPC cycles required to execute this segment (roughly)
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// list of intermediate instructions in this segment
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PPCRecImlInstruction_t* imlList{};
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sint32 imlListSize{};
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sint32 imlListCount{};
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// segment link
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_PPCRecImlSegment_t* nextSegmentBranchNotTaken{}; // this is also the default for segments where there is no branch
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_PPCRecImlSegment_t* nextSegmentBranchTaken{};
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bool nextSegmentIsUncertain{};
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sint32 loopDepth{};
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//sList_t* list_prevSegments;
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std::vector<_PPCRecImlSegment_t*> list_prevSegments{};
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// PPC range of segment
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uint32 ppcAddrMin{};
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uint32 ppcAddrMax{};
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// enterable segments
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bool isEnterable{}; // this segment can be entered from outside the recompiler (no preloaded registers necessary)
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uint32 enterPPCAddress{}; // used if isEnterable is true
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// jump destination segments
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bool isJumpDestination{}; // segment is a destination for one or more (conditional) jumps
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uint32 jumpDestinationPPCAddress{};
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// PPC FPR use mask
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bool ppcFPRUsed[32]{}; // same as ppcGPRUsed, but for FPR
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// CR use mask
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uint32 crBitsInput{}; // bits that are expected to be set from the previous segment (read in this segment but not overwritten)
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uint32 crBitsRead{}; // all bits that are read in this segment
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uint32 crBitsWritten{}; // bits that are written in this segment
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// register allocator info
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PPCSegmentRegisterAllocatorInfo_t raInfo{};
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PPCRecVGPRDistances_t raDistances{};
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bool raRangeExtendProcessed{};
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// segment points
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ppcRecompilerSegmentPoint_t* segmentPointList{};
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}PPCRecImlSegment_t;
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struct IMLInstruction* PPCRecompilerImlGen_generateNewEmptyInstruction(struct ppcImlGenContext_t* ppcImlGenContext);
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struct ppcImlGenContext_t
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{
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PPCRecFunction_t* functionRef;
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class PPCFunctionBoundaryTracker* boundaryTracker;
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uint32* currentInstruction;
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uint32 ppcAddressOfCurrentInstruction;
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IMLSegment* currentOutputSegment;
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struct PPCBasicBlockInfo* currentBasicBlock{};
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// fpr mode
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bool LSQE{ true };
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bool PSE{ true };
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// cycle counter
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uint32 cyclesSinceLastBranch; // used to track ppc cycles
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// temporary general purpose registers
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uint32 mappedRegister[PPC_REC_MAX_VIRTUAL_GPR];
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// temporary floating point registers (single and double precision)
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uint32 mappedFPRRegister[256];
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// list of intermediate instructions
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PPCRecImlInstruction_t* imlList;
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sint32 imlListSize;
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sint32 imlListCount;
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std::unordered_map<IMLName, IMLReg> mappedRegs;
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uint32 GetMaxRegId() const
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{
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if (mappedRegs.empty())
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return 0;
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return mappedRegs.size()-1;
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}
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// list of segments
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PPCRecImlSegment_t** segmentList;
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sint32 segmentListSize;
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sint32 segmentListCount;
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std::vector<IMLSegment*> segmentList2;
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// code generation control
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bool hasFPUInstruction; // if true, PPCEnter macro will create FP_UNAVAIL checks -> Not needed in user mode
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// register allocator info
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struct
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{
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std::vector<raLivenessRange_t*> list_ranges;
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}raInfo;
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// analysis info
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struct
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{
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bool modifiesGQR[8];
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}tracking;
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// debug helpers
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uint32 debug_entryPPCAddress{0};
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~ppcImlGenContext_t()
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{
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for (IMLSegment* imlSegment : segmentList2)
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delete imlSegment;
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segmentList2.clear();
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}
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// append raw instruction
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IMLInstruction& emitInst()
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{
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return *PPCRecompilerImlGen_generateNewEmptyInstruction(this);
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}
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IMLSegment* NewSegment()
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{
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IMLSegment* seg = new IMLSegment();
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segmentList2.emplace_back(seg);
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return seg;
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}
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size_t GetSegmentIndex(IMLSegment* seg)
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{
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for (size_t i = 0; i < segmentList2.size(); i++)
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{
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if (segmentList2[i] == seg)
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return i;
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}
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cemu_assert_error();
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return 0;
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}
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IMLSegment* InsertSegment(size_t index)
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{
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IMLSegment* newSeg = new IMLSegment();
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segmentList2.insert(segmentList2.begin() + index, 1, newSeg);
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return newSeg;
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}
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std::span<IMLSegment*> InsertSegments(size_t index, size_t count)
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{
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segmentList2.insert(segmentList2.begin() + index, count, {});
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for (size_t i = index; i < (index + count); i++)
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segmentList2[i] = new IMLSegment();
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return { segmentList2.data() + index, count};
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}
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void UpdateSegmentIndices()
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{
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for (size_t i = 0; i < segmentList2.size(); i++)
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segmentList2[i]->momentaryIndex = (sint32)i;
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}
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};
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typedef void ATTR_MS_ABI (*PPCREC_JUMP_ENTRY)();
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@ -385,8 +162,6 @@ extern void ATTR_MS_ABI (*PPCRecompiler_leaveRecompilerCode_unvisited)();
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#define PPC_REC_INVALID_FUNCTION ((PPCRecFunction_t*)-1)
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// todo - move some of the stuff above into PPCRecompilerInternal.h
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// recompiler interface
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void PPCRecompiler_recompileIfUnvisited(uint32 enterAddress);
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