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PowerPC recompiler rework (#641)
This commit is contained in:
Exzap
GitHub
parent
06233e3462
commit
b089ae5b32
54 changed files with 15433 additions and 12397 deletions
669
src/Cafe/HW/Espresso/Recompiler/IML/IMLInstruction.cpp
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669
src/Cafe/HW/Espresso/Recompiler/IML/IMLInstruction.cpp
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@ -0,0 +1,669 @@
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#include "IMLInstruction.h"
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#include "IML.h"
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#include "../PPCRecompiler.h"
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#include "../PPCRecompilerIml.h"
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// return true if an instruction has side effects on top of just reading and writing registers
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bool IMLInstruction::HasSideEffects() const
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{
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bool hasSideEffects = true;
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if(type == PPCREC_IML_TYPE_R_R || type == PPCREC_IML_TYPE_R_R_S32 || type == PPCREC_IML_TYPE_COMPARE || type == PPCREC_IML_TYPE_COMPARE_S32)
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hasSideEffects = false;
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// todo - add more cases
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return hasSideEffects;
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}
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void IMLInstruction::CheckRegisterUsage(IMLUsedRegisters* registersUsed) const
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{
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registersUsed->readGPR1 = IMLREG_INVALID;
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registersUsed->readGPR2 = IMLREG_INVALID;
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registersUsed->readGPR3 = IMLREG_INVALID;
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registersUsed->readGPR4 = IMLREG_INVALID;
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registersUsed->writtenGPR1 = IMLREG_INVALID;
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registersUsed->writtenGPR2 = IMLREG_INVALID;
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if (type == PPCREC_IML_TYPE_R_NAME)
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{
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registersUsed->writtenGPR1 = op_r_name.regR;
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}
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else if (type == PPCREC_IML_TYPE_NAME_R)
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{
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registersUsed->readGPR1 = op_r_name.regR;
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}
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else if (type == PPCREC_IML_TYPE_R_R)
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{
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if (operation == PPCREC_IML_OP_X86_CMP)
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{
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// both operands are read only
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registersUsed->readGPR1 = op_r_r.regR;
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registersUsed->readGPR2 = op_r_r.regA;
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}
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else if (
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operation == PPCREC_IML_OP_ASSIGN ||
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operation == PPCREC_IML_OP_ENDIAN_SWAP ||
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operation == PPCREC_IML_OP_CNTLZW ||
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operation == PPCREC_IML_OP_NOT ||
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operation == PPCREC_IML_OP_NEG ||
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operation == PPCREC_IML_OP_ASSIGN_S16_TO_S32 ||
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operation == PPCREC_IML_OP_ASSIGN_S8_TO_S32)
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{
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// result is written, operand is read
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registersUsed->writtenGPR1 = op_r_r.regR;
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registersUsed->readGPR1 = op_r_r.regA;
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}
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else
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cemu_assert_unimplemented();
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}
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else if (type == PPCREC_IML_TYPE_R_S32)
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{
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cemu_assert_debug(operation != PPCREC_IML_OP_ADD &&
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operation != PPCREC_IML_OP_SUB &&
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operation != PPCREC_IML_OP_AND &&
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operation != PPCREC_IML_OP_OR &&
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operation != PPCREC_IML_OP_XOR); // deprecated, use r_r_s32 for these
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if (operation == PPCREC_IML_OP_LEFT_ROTATE)
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{
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// register operand is read and write
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registersUsed->readGPR1 = op_r_immS32.regR;
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registersUsed->writtenGPR1 = op_r_immS32.regR;
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}
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else if (operation == PPCREC_IML_OP_X86_CMP)
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{
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// register operand is read only
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registersUsed->readGPR1 = op_r_immS32.regR;
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}
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else
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{
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// register operand is write only
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// todo - use explicit lists, avoid default cases
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registersUsed->writtenGPR1 = op_r_immS32.regR;
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}
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}
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else if (type == PPCREC_IML_TYPE_R_R_S32)
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{
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registersUsed->writtenGPR1 = op_r_r_s32.regR;
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registersUsed->readGPR1 = op_r_r_s32.regA;
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}
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else if (type == PPCREC_IML_TYPE_R_R_S32_CARRY)
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{
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registersUsed->writtenGPR1 = op_r_r_s32_carry.regR;
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registersUsed->readGPR1 = op_r_r_s32_carry.regA;
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// some operations read carry
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switch (operation)
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{
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case PPCREC_IML_OP_ADD_WITH_CARRY:
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registersUsed->readGPR2 = op_r_r_s32_carry.regCarry;
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break;
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case PPCREC_IML_OP_ADD:
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break;
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default:
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cemu_assert_unimplemented();
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}
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// carry is always written
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registersUsed->writtenGPR2 = op_r_r_s32_carry.regCarry;
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}
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else if (type == PPCREC_IML_TYPE_R_R_R)
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{
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// in all cases result is written and other operands are read only
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// with the exception of XOR, where if regA == regB then all bits are zeroed out. So we don't consider it a read
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registersUsed->writtenGPR1 = op_r_r_r.regR;
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if(!(operation == PPCREC_IML_OP_XOR && op_r_r_r.regA == op_r_r_r.regB))
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{
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registersUsed->readGPR1 = op_r_r_r.regA;
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registersUsed->readGPR2 = op_r_r_r.regB;
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}
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}
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else if (type == PPCREC_IML_TYPE_R_R_R_CARRY)
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{
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registersUsed->writtenGPR1 = op_r_r_r_carry.regR;
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registersUsed->readGPR1 = op_r_r_r_carry.regA;
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registersUsed->readGPR2 = op_r_r_r_carry.regB;
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// some operations read carry
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switch (operation)
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{
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case PPCREC_IML_OP_ADD_WITH_CARRY:
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registersUsed->readGPR3 = op_r_r_r_carry.regCarry;
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break;
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case PPCREC_IML_OP_ADD:
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break;
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default:
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cemu_assert_unimplemented();
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}
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// carry is always written
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registersUsed->writtenGPR2 = op_r_r_r_carry.regCarry;
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}
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else if (type == PPCREC_IML_TYPE_CJUMP_CYCLE_CHECK)
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{
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// no effect on registers
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}
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else if (type == PPCREC_IML_TYPE_NO_OP)
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{
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// no effect on registers
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}
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else if (type == PPCREC_IML_TYPE_MACRO)
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{
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if (operation == PPCREC_IML_MACRO_BL || operation == PPCREC_IML_MACRO_B_FAR || operation == PPCREC_IML_MACRO_LEAVE || operation == PPCREC_IML_MACRO_DEBUGBREAK || operation == PPCREC_IML_MACRO_COUNT_CYCLES || operation == PPCREC_IML_MACRO_HLE)
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{
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// no effect on registers
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}
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else if (operation == PPCREC_IML_MACRO_B_TO_REG)
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{
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cemu_assert_debug(op_macro.paramReg.IsValid());
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registersUsed->readGPR1 = op_macro.paramReg;
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}
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else
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cemu_assert_unimplemented();
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}
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else if (type == PPCREC_IML_TYPE_COMPARE)
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{
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registersUsed->readGPR1 = op_compare.regA;
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registersUsed->readGPR2 = op_compare.regB;
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registersUsed->writtenGPR1 = op_compare.regR;
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}
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else if (type == PPCREC_IML_TYPE_COMPARE_S32)
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{
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registersUsed->readGPR1 = op_compare_s32.regA;
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registersUsed->writtenGPR1 = op_compare_s32.regR;
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}
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else if (type == PPCREC_IML_TYPE_CONDITIONAL_JUMP)
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{
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registersUsed->readGPR1 = op_conditional_jump.registerBool;
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}
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else if (type == PPCREC_IML_TYPE_JUMP)
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{
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// no registers affected
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}
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else if (type == PPCREC_IML_TYPE_LOAD)
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{
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registersUsed->writtenGPR1 = op_storeLoad.registerData;
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if (op_storeLoad.registerMem.IsValid())
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registersUsed->readGPR1 = op_storeLoad.registerMem;
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}
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else if (type == PPCREC_IML_TYPE_LOAD_INDEXED)
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{
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registersUsed->writtenGPR1 = op_storeLoad.registerData;
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if (op_storeLoad.registerMem.IsValid())
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registersUsed->readGPR1 = op_storeLoad.registerMem;
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if (op_storeLoad.registerMem2.IsValid())
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registersUsed->readGPR2 = op_storeLoad.registerMem2;
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}
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else if (type == PPCREC_IML_TYPE_STORE)
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{
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registersUsed->readGPR1 = op_storeLoad.registerData;
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if (op_storeLoad.registerMem.IsValid())
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registersUsed->readGPR2 = op_storeLoad.registerMem;
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}
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else if (type == PPCREC_IML_TYPE_STORE_INDEXED)
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{
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registersUsed->readGPR1 = op_storeLoad.registerData;
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if (op_storeLoad.registerMem.IsValid())
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registersUsed->readGPR2 = op_storeLoad.registerMem;
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if (op_storeLoad.registerMem2.IsValid())
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registersUsed->readGPR3 = op_storeLoad.registerMem2;
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}
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else if (type == PPCREC_IML_TYPE_ATOMIC_CMP_STORE)
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{
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registersUsed->readGPR1 = op_atomic_compare_store.regEA;
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registersUsed->readGPR2 = op_atomic_compare_store.regCompareValue;
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registersUsed->readGPR3 = op_atomic_compare_store.regWriteValue;
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registersUsed->writtenGPR1 = op_atomic_compare_store.regBoolOut;
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}
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else if (type == PPCREC_IML_TYPE_CALL_IMM)
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{
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if (op_call_imm.regParam0.IsValid())
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registersUsed->readGPR1 = op_call_imm.regParam0;
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if (op_call_imm.regParam1.IsValid())
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registersUsed->readGPR2 = op_call_imm.regParam1;
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if (op_call_imm.regParam2.IsValid())
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registersUsed->readGPR3 = op_call_imm.regParam2;
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registersUsed->writtenGPR1 = op_call_imm.regReturn;
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}
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else if (type == PPCREC_IML_TYPE_FPR_LOAD)
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{
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// fpr load operation
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registersUsed->writtenGPR1 = op_storeLoad.registerData;
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// address is in gpr register
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if (op_storeLoad.registerMem.IsValid())
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registersUsed->readGPR1 = op_storeLoad.registerMem;
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// determine partially written result
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switch (op_storeLoad.mode)
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{
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case PPCREC_FPR_LD_MODE_PSQ_GENERIC_PS0:
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case PPCREC_FPR_LD_MODE_PSQ_GENERIC_PS0_PS1:
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cemu_assert_debug(op_storeLoad.registerGQR.IsValid());
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registersUsed->readGPR2 = op_storeLoad.registerGQR;
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break;
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case PPCREC_FPR_LD_MODE_DOUBLE_INTO_PS0:
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// PS1 remains the same
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cemu_assert_debug(op_storeLoad.registerGQR.IsInvalid());
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registersUsed->readGPR2 = op_storeLoad.registerData;
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break;
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case PPCREC_FPR_LD_MODE_SINGLE_INTO_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_FLOAT_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_FLOAT_PS0:
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case PPCREC_FPR_LD_MODE_PSQ_S16_PS0:
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case PPCREC_FPR_LD_MODE_PSQ_S16_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_U16_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_U16_PS0:
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case PPCREC_FPR_LD_MODE_PSQ_S8_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_U8_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_U8_PS0:
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case PPCREC_FPR_LD_MODE_PSQ_S8_PS0:
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cemu_assert_debug(op_storeLoad.registerGQR.IsInvalid());
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break;
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default:
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cemu_assert_unimplemented();
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}
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}
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else if (type == PPCREC_IML_TYPE_FPR_LOAD_INDEXED)
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{
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// fpr load operation
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registersUsed->writtenGPR1 = op_storeLoad.registerData;
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// address is in gpr registers
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if (op_storeLoad.registerMem.IsValid())
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registersUsed->readGPR1 = op_storeLoad.registerMem;
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if (op_storeLoad.registerMem2.IsValid())
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registersUsed->readGPR2 = op_storeLoad.registerMem2;
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// determine partially written result
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switch (op_storeLoad.mode)
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{
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case PPCREC_FPR_LD_MODE_PSQ_GENERIC_PS0:
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case PPCREC_FPR_LD_MODE_PSQ_GENERIC_PS0_PS1:
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cemu_assert_debug(op_storeLoad.registerGQR.IsValid());
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registersUsed->readGPR3 = op_storeLoad.registerGQR;
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break;
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case PPCREC_FPR_LD_MODE_DOUBLE_INTO_PS0:
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// PS1 remains the same
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cemu_assert_debug(op_storeLoad.registerGQR.IsInvalid());
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registersUsed->readGPR3 = op_storeLoad.registerData;
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break;
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case PPCREC_FPR_LD_MODE_SINGLE_INTO_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_FLOAT_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_FLOAT_PS0:
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case PPCREC_FPR_LD_MODE_PSQ_S16_PS0:
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case PPCREC_FPR_LD_MODE_PSQ_S16_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_U16_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_U16_PS0:
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case PPCREC_FPR_LD_MODE_PSQ_S8_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_U8_PS0_PS1:
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case PPCREC_FPR_LD_MODE_PSQ_U8_PS0:
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cemu_assert_debug(op_storeLoad.registerGQR.IsInvalid());
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break;
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default:
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cemu_assert_unimplemented();
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}
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}
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else if (type == PPCREC_IML_TYPE_FPR_STORE)
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{
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// fpr store operation
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registersUsed->readGPR1 = op_storeLoad.registerData;
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if (op_storeLoad.registerMem.IsValid())
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registersUsed->readGPR2 = op_storeLoad.registerMem;
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// PSQ generic stores also access GQR
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switch (op_storeLoad.mode)
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{
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case PPCREC_FPR_ST_MODE_PSQ_GENERIC_PS0:
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case PPCREC_FPR_ST_MODE_PSQ_GENERIC_PS0_PS1:
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cemu_assert_debug(op_storeLoad.registerGQR.IsValid());
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registersUsed->readGPR3 = op_storeLoad.registerGQR;
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break;
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default:
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cemu_assert_debug(op_storeLoad.registerGQR.IsInvalid());
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break;
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}
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}
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else if (type == PPCREC_IML_TYPE_FPR_STORE_INDEXED)
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{
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// fpr store operation
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registersUsed->readGPR1 = op_storeLoad.registerData;
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// address is in gpr registers
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if (op_storeLoad.registerMem.IsValid())
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registersUsed->readGPR2 = op_storeLoad.registerMem;
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if (op_storeLoad.registerMem2.IsValid())
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registersUsed->readGPR3 = op_storeLoad.registerMem2;
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// PSQ generic stores also access GQR
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switch (op_storeLoad.mode)
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{
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case PPCREC_FPR_ST_MODE_PSQ_GENERIC_PS0:
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case PPCREC_FPR_ST_MODE_PSQ_GENERIC_PS0_PS1:
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cemu_assert_debug(op_storeLoad.registerGQR.IsValid());
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registersUsed->readGPR4 = op_storeLoad.registerGQR;
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break;
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default:
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cemu_assert_debug(op_storeLoad.registerGQR.IsInvalid());
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break;
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}
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}
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else if (type == PPCREC_IML_TYPE_FPR_R_R)
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{
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// fpr operation
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if (operation == PPCREC_IML_OP_FPR_COPY_BOTTOM_TO_BOTTOM_AND_TOP ||
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operation == PPCREC_IML_OP_FPR_COPY_TOP_TO_BOTTOM_AND_TOP ||
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operation == PPCREC_IML_OP_FPR_COPY_BOTTOM_AND_TOP_SWAPPED ||
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operation == PPCREC_IML_OP_ASSIGN ||
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operation == PPCREC_IML_OP_FPR_NEGATE_PAIR ||
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operation == PPCREC_IML_OP_FPR_ABS_PAIR ||
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operation == PPCREC_IML_OP_FPR_FRES_PAIR ||
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operation == PPCREC_IML_OP_FPR_FRSQRTE_PAIR)
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{
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// operand read, result written
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registersUsed->readGPR1 = op_fpr_r_r.regA;
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registersUsed->writtenGPR1 = op_fpr_r_r.regR;
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}
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else if (
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operation == PPCREC_IML_OP_FPR_COPY_BOTTOM_TO_BOTTOM ||
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operation == PPCREC_IML_OP_FPR_COPY_BOTTOM_TO_TOP ||
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operation == PPCREC_IML_OP_FPR_COPY_TOP_TO_TOP ||
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operation == PPCREC_IML_OP_FPR_COPY_TOP_TO_BOTTOM ||
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operation == PPCREC_IML_OP_FPR_EXPAND_BOTTOM32_TO_BOTTOM64_AND_TOP64 ||
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operation == PPCREC_IML_OP_FPR_BOTTOM_FCTIWZ ||
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operation == PPCREC_IML_OP_FPR_BOTTOM_RECIPROCAL_SQRT
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)
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{
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// operand read, result read and (partially) written
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registersUsed->readGPR1 = op_fpr_r_r.regA;
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registersUsed->readGPR2 = op_fpr_r_r.regR;
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registersUsed->writtenGPR1 = op_fpr_r_r.regR;
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}
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else if (operation == PPCREC_IML_OP_FPR_MULTIPLY_BOTTOM ||
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operation == PPCREC_IML_OP_FPR_MULTIPLY_PAIR ||
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operation == PPCREC_IML_OP_FPR_DIVIDE_BOTTOM ||
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operation == PPCREC_IML_OP_FPR_DIVIDE_PAIR ||
|
||||
operation == PPCREC_IML_OP_FPR_ADD_BOTTOM ||
|
||||
operation == PPCREC_IML_OP_FPR_ADD_PAIR ||
|
||||
operation == PPCREC_IML_OP_FPR_SUB_PAIR ||
|
||||
operation == PPCREC_IML_OP_FPR_SUB_BOTTOM)
|
||||
{
|
||||
// operand read, result read and written
|
||||
registersUsed->readGPR1 = op_fpr_r_r.regA;
|
||||
registersUsed->readGPR2 = op_fpr_r_r.regR;
|
||||
registersUsed->writtenGPR1 = op_fpr_r_r.regR;
|
||||
|
||||
}
|
||||
else if (operation == PPCREC_IML_OP_FPR_FCMPU_BOTTOM ||
|
||||
operation == PPCREC_IML_OP_FPR_FCMPU_TOP ||
|
||||
operation == PPCREC_IML_OP_FPR_FCMPO_BOTTOM)
|
||||
{
|
||||
// operand read, result read
|
||||
registersUsed->readGPR1 = op_fpr_r_r.regA;
|
||||
registersUsed->readGPR2 = op_fpr_r_r.regR;
|
||||
}
|
||||
else
|
||||
cemu_assert_unimplemented();
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_FPR_R_R_R)
|
||||
{
|
||||
// fpr operation
|
||||
registersUsed->readGPR1 = op_fpr_r_r_r.regA;
|
||||
registersUsed->readGPR2 = op_fpr_r_r_r.regB;
|
||||
registersUsed->writtenGPR1 = op_fpr_r_r_r.regR;
|
||||
// handle partially written result
|
||||
switch (operation)
|
||||
{
|
||||
case PPCREC_IML_OP_FPR_MULTIPLY_BOTTOM:
|
||||
case PPCREC_IML_OP_FPR_ADD_BOTTOM:
|
||||
case PPCREC_IML_OP_FPR_SUB_BOTTOM:
|
||||
registersUsed->readGPR3 = op_fpr_r_r_r.regR;
|
||||
break;
|
||||
case PPCREC_IML_OP_FPR_SUB_PAIR:
|
||||
break;
|
||||
default:
|
||||
cemu_assert_unimplemented();
|
||||
}
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_FPR_R_R_R_R)
|
||||
{
|
||||
// fpr operation
|
||||
registersUsed->readGPR1 = op_fpr_r_r_r_r.regA;
|
||||
registersUsed->readGPR2 = op_fpr_r_r_r_r.regB;
|
||||
registersUsed->readGPR3 = op_fpr_r_r_r_r.regC;
|
||||
registersUsed->writtenGPR1 = op_fpr_r_r_r_r.regR;
|
||||
// handle partially written result
|
||||
switch (operation)
|
||||
{
|
||||
case PPCREC_IML_OP_FPR_SELECT_BOTTOM:
|
||||
registersUsed->readGPR4 = op_fpr_r_r_r_r.regR;
|
||||
break;
|
||||
case PPCREC_IML_OP_FPR_SUM0:
|
||||
case PPCREC_IML_OP_FPR_SUM1:
|
||||
case PPCREC_IML_OP_FPR_SELECT_PAIR:
|
||||
break;
|
||||
default:
|
||||
cemu_assert_unimplemented();
|
||||
}
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_FPR_R)
|
||||
{
|
||||
// fpr operation
|
||||
if (operation == PPCREC_IML_OP_FPR_NEGATE_BOTTOM ||
|
||||
operation == PPCREC_IML_OP_FPR_ABS_BOTTOM ||
|
||||
operation == PPCREC_IML_OP_FPR_NEGATIVE_ABS_BOTTOM ||
|
||||
operation == PPCREC_IML_OP_FPR_EXPAND_BOTTOM32_TO_BOTTOM64_AND_TOP64 ||
|
||||
operation == PPCREC_IML_OP_FPR_ROUND_TO_SINGLE_PRECISION_BOTTOM ||
|
||||
operation == PPCREC_IML_OP_FPR_ROUND_TO_SINGLE_PRECISION_PAIR)
|
||||
{
|
||||
registersUsed->readGPR1 = op_fpr_r.regR;
|
||||
registersUsed->writtenGPR1 = op_fpr_r.regR;
|
||||
}
|
||||
else
|
||||
cemu_assert_unimplemented();
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_FPR_COMPARE)
|
||||
{
|
||||
registersUsed->writtenGPR1 = op_fpr_compare.regR;
|
||||
registersUsed->readGPR1 = op_fpr_compare.regA;
|
||||
registersUsed->readGPR2 = op_fpr_compare.regB;
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_X86_EFLAGS_JCC)
|
||||
{
|
||||
// no registers read or written (except for the implicit eflags)
|
||||
}
|
||||
else
|
||||
{
|
||||
cemu_assert_unimplemented();
|
||||
}
|
||||
}
|
||||
|
||||
IMLReg replaceRegisterIdMultiple(IMLReg reg, const std::unordered_map<IMLRegID, IMLRegID>& translationTable)
|
||||
{
|
||||
if (reg.IsInvalid())
|
||||
return reg;
|
||||
const auto& it = translationTable.find(reg.GetRegID());
|
||||
cemu_assert_debug(it != translationTable.cend());
|
||||
IMLReg alteredReg = reg;
|
||||
alteredReg.SetRegID(it->second);
|
||||
return alteredReg;
|
||||
}
|
||||
|
||||
void IMLInstruction::RewriteGPR(const std::unordered_map<IMLRegID, IMLRegID>& translationTable)
|
||||
{
|
||||
if (type == PPCREC_IML_TYPE_R_NAME)
|
||||
{
|
||||
op_r_name.regR = replaceRegisterIdMultiple(op_r_name.regR, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_NAME_R)
|
||||
{
|
||||
op_r_name.regR = replaceRegisterIdMultiple(op_r_name.regR, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_R_R)
|
||||
{
|
||||
op_r_r.regR = replaceRegisterIdMultiple(op_r_r.regR, translationTable);
|
||||
op_r_r.regA = replaceRegisterIdMultiple(op_r_r.regA, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_R_S32)
|
||||
{
|
||||
op_r_immS32.regR = replaceRegisterIdMultiple(op_r_immS32.regR, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_R_R_S32)
|
||||
{
|
||||
op_r_r_s32.regR = replaceRegisterIdMultiple(op_r_r_s32.regR, translationTable);
|
||||
op_r_r_s32.regA = replaceRegisterIdMultiple(op_r_r_s32.regA, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_R_R_S32_CARRY)
|
||||
{
|
||||
op_r_r_s32_carry.regR = replaceRegisterIdMultiple(op_r_r_s32_carry.regR, translationTable);
|
||||
op_r_r_s32_carry.regA = replaceRegisterIdMultiple(op_r_r_s32_carry.regA, translationTable);
|
||||
op_r_r_s32_carry.regCarry = replaceRegisterIdMultiple(op_r_r_s32_carry.regCarry, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_R_R_R)
|
||||
{
|
||||
op_r_r_r.regR = replaceRegisterIdMultiple(op_r_r_r.regR, translationTable);
|
||||
op_r_r_r.regA = replaceRegisterIdMultiple(op_r_r_r.regA, translationTable);
|
||||
op_r_r_r.regB = replaceRegisterIdMultiple(op_r_r_r.regB, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_R_R_R_CARRY)
|
||||
{
|
||||
op_r_r_r_carry.regR = replaceRegisterIdMultiple(op_r_r_r_carry.regR, translationTable);
|
||||
op_r_r_r_carry.regA = replaceRegisterIdMultiple(op_r_r_r_carry.regA, translationTable);
|
||||
op_r_r_r_carry.regB = replaceRegisterIdMultiple(op_r_r_r_carry.regB, translationTable);
|
||||
op_r_r_r_carry.regCarry = replaceRegisterIdMultiple(op_r_r_r_carry.regCarry, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_COMPARE)
|
||||
{
|
||||
op_compare.regR = replaceRegisterIdMultiple(op_compare.regR, translationTable);
|
||||
op_compare.regA = replaceRegisterIdMultiple(op_compare.regA, translationTable);
|
||||
op_compare.regB = replaceRegisterIdMultiple(op_compare.regB, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_COMPARE_S32)
|
||||
{
|
||||
op_compare_s32.regR = replaceRegisterIdMultiple(op_compare_s32.regR, translationTable);
|
||||
op_compare_s32.regA = replaceRegisterIdMultiple(op_compare_s32.regA, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_CONDITIONAL_JUMP)
|
||||
{
|
||||
op_conditional_jump.registerBool = replaceRegisterIdMultiple(op_conditional_jump.registerBool, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_CJUMP_CYCLE_CHECK || type == PPCREC_IML_TYPE_JUMP)
|
||||
{
|
||||
// no effect on registers
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_NO_OP)
|
||||
{
|
||||
// no effect on registers
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_MACRO)
|
||||
{
|
||||
if (operation == PPCREC_IML_MACRO_BL || operation == PPCREC_IML_MACRO_B_FAR || operation == PPCREC_IML_MACRO_LEAVE || operation == PPCREC_IML_MACRO_DEBUGBREAK || operation == PPCREC_IML_MACRO_HLE || operation == PPCREC_IML_MACRO_COUNT_CYCLES)
|
||||
{
|
||||
// no effect on registers
|
||||
}
|
||||
else if (operation == PPCREC_IML_MACRO_B_TO_REG)
|
||||
{
|
||||
op_macro.paramReg = replaceRegisterIdMultiple(op_macro.paramReg, translationTable);
|
||||
}
|
||||
else
|
||||
{
|
||||
cemu_assert_unimplemented();
|
||||
}
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_LOAD)
|
||||
{
|
||||
op_storeLoad.registerData = replaceRegisterIdMultiple(op_storeLoad.registerData, translationTable);
|
||||
if (op_storeLoad.registerMem.IsValid())
|
||||
{
|
||||
op_storeLoad.registerMem = replaceRegisterIdMultiple(op_storeLoad.registerMem, translationTable);
|
||||
}
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_LOAD_INDEXED)
|
||||
{
|
||||
op_storeLoad.registerData = replaceRegisterIdMultiple(op_storeLoad.registerData, translationTable);
|
||||
if (op_storeLoad.registerMem.IsValid())
|
||||
op_storeLoad.registerMem = replaceRegisterIdMultiple(op_storeLoad.registerMem, translationTable);
|
||||
if (op_storeLoad.registerMem2.IsValid())
|
||||
op_storeLoad.registerMem2 = replaceRegisterIdMultiple(op_storeLoad.registerMem2, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_STORE)
|
||||
{
|
||||
op_storeLoad.registerData = replaceRegisterIdMultiple(op_storeLoad.registerData, translationTable);
|
||||
if (op_storeLoad.registerMem.IsValid())
|
||||
op_storeLoad.registerMem = replaceRegisterIdMultiple(op_storeLoad.registerMem, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_STORE_INDEXED)
|
||||
{
|
||||
op_storeLoad.registerData = replaceRegisterIdMultiple(op_storeLoad.registerData, translationTable);
|
||||
if (op_storeLoad.registerMem.IsValid())
|
||||
op_storeLoad.registerMem = replaceRegisterIdMultiple(op_storeLoad.registerMem, translationTable);
|
||||
if (op_storeLoad.registerMem2.IsValid())
|
||||
op_storeLoad.registerMem2 = replaceRegisterIdMultiple(op_storeLoad.registerMem2, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_ATOMIC_CMP_STORE)
|
||||
{
|
||||
op_atomic_compare_store.regEA = replaceRegisterIdMultiple(op_atomic_compare_store.regEA, translationTable);
|
||||
op_atomic_compare_store.regCompareValue = replaceRegisterIdMultiple(op_atomic_compare_store.regCompareValue, translationTable);
|
||||
op_atomic_compare_store.regWriteValue = replaceRegisterIdMultiple(op_atomic_compare_store.regWriteValue, translationTable);
|
||||
op_atomic_compare_store.regBoolOut = replaceRegisterIdMultiple(op_atomic_compare_store.regBoolOut, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_CALL_IMM)
|
||||
{
|
||||
op_call_imm.regReturn = replaceRegisterIdMultiple(op_call_imm.regReturn, translationTable);
|
||||
if (op_call_imm.regParam0.IsValid())
|
||||
op_call_imm.regParam0 = replaceRegisterIdMultiple(op_call_imm.regParam0, translationTable);
|
||||
if (op_call_imm.regParam1.IsValid())
|
||||
op_call_imm.regParam1 = replaceRegisterIdMultiple(op_call_imm.regParam1, translationTable);
|
||||
if (op_call_imm.regParam2.IsValid())
|
||||
op_call_imm.regParam2 = replaceRegisterIdMultiple(op_call_imm.regParam2, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_FPR_LOAD)
|
||||
{
|
||||
op_storeLoad.registerData = replaceRegisterIdMultiple(op_storeLoad.registerData, translationTable);
|
||||
op_storeLoad.registerMem = replaceRegisterIdMultiple(op_storeLoad.registerMem, translationTable);
|
||||
op_storeLoad.registerGQR = replaceRegisterIdMultiple(op_storeLoad.registerGQR, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_FPR_LOAD_INDEXED)
|
||||
{
|
||||
op_storeLoad.registerData = replaceRegisterIdMultiple(op_storeLoad.registerData, translationTable);
|
||||
op_storeLoad.registerMem = replaceRegisterIdMultiple(op_storeLoad.registerMem, translationTable);
|
||||
op_storeLoad.registerMem2 = replaceRegisterIdMultiple(op_storeLoad.registerMem2, translationTable);
|
||||
op_storeLoad.registerGQR = replaceRegisterIdMultiple(op_storeLoad.registerGQR, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_FPR_STORE)
|
||||
{
|
||||
op_storeLoad.registerData = replaceRegisterIdMultiple(op_storeLoad.registerData, translationTable);
|
||||
op_storeLoad.registerMem = replaceRegisterIdMultiple(op_storeLoad.registerMem, translationTable);
|
||||
op_storeLoad.registerGQR = replaceRegisterIdMultiple(op_storeLoad.registerGQR, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_FPR_STORE_INDEXED)
|
||||
{
|
||||
op_storeLoad.registerData = replaceRegisterIdMultiple(op_storeLoad.registerData, translationTable);
|
||||
op_storeLoad.registerMem = replaceRegisterIdMultiple(op_storeLoad.registerMem, translationTable);
|
||||
op_storeLoad.registerMem2 = replaceRegisterIdMultiple(op_storeLoad.registerMem2, translationTable);
|
||||
op_storeLoad.registerGQR = replaceRegisterIdMultiple(op_storeLoad.registerGQR, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_FPR_R)
|
||||
{
|
||||
op_fpr_r.regR = replaceRegisterIdMultiple(op_fpr_r.regR, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_FPR_R_R)
|
||||
{
|
||||
op_fpr_r_r.regR = replaceRegisterIdMultiple(op_fpr_r_r.regR, translationTable);
|
||||
op_fpr_r_r.regA = replaceRegisterIdMultiple(op_fpr_r_r.regA, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_FPR_R_R_R)
|
||||
{
|
||||
op_fpr_r_r_r.regR = replaceRegisterIdMultiple(op_fpr_r_r_r.regR, translationTable);
|
||||
op_fpr_r_r_r.regA = replaceRegisterIdMultiple(op_fpr_r_r_r.regA, translationTable);
|
||||
op_fpr_r_r_r.regB = replaceRegisterIdMultiple(op_fpr_r_r_r.regB, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_FPR_R_R_R_R)
|
||||
{
|
||||
op_fpr_r_r_r_r.regR = replaceRegisterIdMultiple(op_fpr_r_r_r_r.regR, translationTable);
|
||||
op_fpr_r_r_r_r.regA = replaceRegisterIdMultiple(op_fpr_r_r_r_r.regA, translationTable);
|
||||
op_fpr_r_r_r_r.regB = replaceRegisterIdMultiple(op_fpr_r_r_r_r.regB, translationTable);
|
||||
op_fpr_r_r_r_r.regC = replaceRegisterIdMultiple(op_fpr_r_r_r_r.regC, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_FPR_COMPARE)
|
||||
{
|
||||
op_fpr_compare.regA = replaceRegisterIdMultiple(op_fpr_compare.regA, translationTable);
|
||||
op_fpr_compare.regB = replaceRegisterIdMultiple(op_fpr_compare.regB, translationTable);
|
||||
op_fpr_compare.regR = replaceRegisterIdMultiple(op_fpr_compare.regR, translationTable);
|
||||
}
|
||||
else if (type == PPCREC_IML_TYPE_X86_EFLAGS_JCC)
|
||||
{
|
||||
// no registers read or written (except for the implicit eflags)
|
||||
}
|
||||
else
|
||||
{
|
||||
cemu_assert_unimplemented();
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue