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https://github.com/cemu-project/Cemu.git
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PowerPC recompiler rework (#641)
This commit is contained in:
Exzap
GitHub
parent
06233e3462
commit
b089ae5b32
54 changed files with 15433 additions and 12397 deletions
528
src/Cafe/HW/Espresso/Recompiler/IML/IMLDebug.cpp
Normal file
528
src/Cafe/HW/Espresso/Recompiler/IML/IMLDebug.cpp
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@ -0,0 +1,528 @@
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#include "IML.h"
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#include "IMLInstruction.h"
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#include "IMLSegment.h"
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#include "IMLRegisterAllocatorRanges.h"
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#include "util/helpers/StringBuf.h"
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#include "../PPCRecompiler.h"
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const char* IMLDebug_GetOpcodeName(const IMLInstruction* iml)
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{
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static char _tempOpcodename[32];
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uint32 op = iml->operation;
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if (op == PPCREC_IML_OP_ASSIGN)
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return "MOV";
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else if (op == PPCREC_IML_OP_ADD)
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return "ADD";
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else if (op == PPCREC_IML_OP_ADD_WITH_CARRY)
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return "ADC";
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else if (op == PPCREC_IML_OP_SUB)
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return "SUB";
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else if (op == PPCREC_IML_OP_OR)
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return "OR";
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else if (op == PPCREC_IML_OP_AND)
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return "AND";
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else if (op == PPCREC_IML_OP_XOR)
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return "XOR";
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else if (op == PPCREC_IML_OP_LEFT_SHIFT)
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return "LSH";
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else if (op == PPCREC_IML_OP_RIGHT_SHIFT_U)
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return "RSH";
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else if (op == PPCREC_IML_OP_RIGHT_SHIFT_S)
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return "ARSH";
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else if (op == PPCREC_IML_OP_LEFT_ROTATE)
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return "LROT";
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else if (op == PPCREC_IML_OP_MULTIPLY_SIGNED)
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return "MULS";
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else if (op == PPCREC_IML_OP_DIVIDE_SIGNED)
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return "DIVS";
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sprintf(_tempOpcodename, "OP0%02x_T%d", iml->operation, iml->type);
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return _tempOpcodename;
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}
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std::string IMLDebug_GetRegName(IMLReg r)
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{
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std::string regName;
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uint32 regId = r.GetRegID();
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switch (r.GetRegFormat())
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{
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case IMLRegFormat::F32:
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regName.append("f");
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break;
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case IMLRegFormat::F64:
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regName.append("fd");
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break;
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case IMLRegFormat::I32:
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regName.append("i");
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break;
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case IMLRegFormat::I64:
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regName.append("r");
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break;
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default:
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DEBUG_BREAK;
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}
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regName.append(fmt::format("{}", regId));
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return regName;
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}
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void IMLDebug_AppendRegisterParam(StringBuf& strOutput, IMLReg virtualRegister, bool isLast = false)
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{
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strOutput.add(IMLDebug_GetRegName(virtualRegister));
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if (!isLast)
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strOutput.add(", ");
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}
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void IMLDebug_AppendS32Param(StringBuf& strOutput, sint32 val, bool isLast = false)
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{
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if (val < 0)
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{
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strOutput.add("-");
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val = -val;
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}
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strOutput.addFmt("0x{:08x}", val);
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if (!isLast)
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strOutput.add(", ");
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}
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void IMLDebug_PrintLivenessRangeInfo(StringBuf& currentLineText, IMLSegment* imlSegment, sint32 offset)
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{
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// pad to 70 characters
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sint32 index = currentLineText.getLen();
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while (index < 70)
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{
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currentLineText.add(" ");
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index++;
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}
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raLivenessRange* subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
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while (subrangeItr)
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{
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if (subrangeItr->interval.start.GetInstructionIndexEx() == offset)
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{
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if(subrangeItr->interval.start.IsInstructionIndex() && !subrangeItr->interval.start.IsOnInputEdge())
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currentLineText.add(".");
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else
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currentLineText.add("|");
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currentLineText.addFmt("{:<4}", subrangeItr->GetVirtualRegister());
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}
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else if (subrangeItr->interval.end.GetInstructionIndexEx() == offset)
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{
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if(subrangeItr->interval.end.IsInstructionIndex() && !subrangeItr->interval.end.IsOnOutputEdge())
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currentLineText.add("* ");
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else
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currentLineText.add("| ");
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}
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else if (subrangeItr->interval.ContainsInstructionIndexEx(offset))
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{
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currentLineText.add("| ");
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}
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else
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{
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currentLineText.add(" ");
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}
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index += 5;
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// next
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subrangeItr = subrangeItr->link_allSegmentRanges.next;
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}
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}
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std::string IMLDebug_GetSegmentName(ppcImlGenContext_t* ctx, IMLSegment* seg)
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{
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if (!ctx)
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{
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return "<NoNameWithoutCtx>";
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}
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// find segment index
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for (size_t i = 0; i < ctx->segmentList2.size(); i++)
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{
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if (ctx->segmentList2[i] == seg)
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{
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return fmt::format("Seg{:04x}", i);
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}
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}
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return "<SegmentNotInCtx>";
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}
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std::string IMLDebug_GetConditionName(IMLCondition cond)
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{
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switch (cond)
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{
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case IMLCondition::EQ:
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return "EQ";
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case IMLCondition::NEQ:
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return "NEQ";
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case IMLCondition::UNSIGNED_GT:
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return "UGT";
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case IMLCondition::UNSIGNED_LT:
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return "ULT";
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case IMLCondition::SIGNED_GT:
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return "SGT";
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case IMLCondition::SIGNED_LT:
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return "SLT";
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default:
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cemu_assert_unimplemented();
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}
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return "ukn";
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}
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void IMLDebug_DisassembleInstruction(const IMLInstruction& inst, std::string& disassemblyLineOut)
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{
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const sint32 lineOffsetParameters = 10;//18;
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StringBuf strOutput(1024);
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strOutput.reset();
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if (inst.type == PPCREC_IML_TYPE_R_NAME || inst.type == PPCREC_IML_TYPE_NAME_R)
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{
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if (inst.type == PPCREC_IML_TYPE_R_NAME)
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strOutput.add("R_NAME");
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else
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strOutput.add("NAME_R");
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while ((sint32)strOutput.getLen() < lineOffsetParameters)
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strOutput.add(" ");
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if(inst.type == PPCREC_IML_TYPE_R_NAME)
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_name.regR);
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strOutput.add("name_");
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if (inst.op_r_name.name >= PPCREC_NAME_R0 && inst.op_r_name.name < (PPCREC_NAME_R0 + 999))
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{
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strOutput.addFmt("r{}", inst.op_r_name.name - PPCREC_NAME_R0);
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}
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else if (inst.op_r_name.name >= PPCREC_NAME_FPR0 && inst.op_r_name.name < (PPCREC_NAME_FPR0 + 999))
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{
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strOutput.addFmt("f{}", inst.op_r_name.name - PPCREC_NAME_FPR0);
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}
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else if (inst.op_r_name.name >= PPCREC_NAME_SPR0 && inst.op_r_name.name < (PPCREC_NAME_SPR0 + 999))
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{
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strOutput.addFmt("spr{}", inst.op_r_name.name - PPCREC_NAME_SPR0);
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}
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else if (inst.op_r_name.name >= PPCREC_NAME_CR && inst.op_r_name.name <= PPCREC_NAME_CR_LAST)
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strOutput.addFmt("cr{}", inst.op_r_name.name - PPCREC_NAME_CR);
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else if (inst.op_r_name.name == PPCREC_NAME_XER_CA)
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strOutput.add("xer.ca");
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else if (inst.op_r_name.name == PPCREC_NAME_XER_SO)
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strOutput.add("xer.so");
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else if (inst.op_r_name.name == PPCREC_NAME_XER_OV)
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strOutput.add("xer.ov");
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else if (inst.op_r_name.name == PPCREC_NAME_CPU_MEMRES_EA)
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strOutput.add("cpuReservation.ea");
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else if (inst.op_r_name.name == PPCREC_NAME_CPU_MEMRES_VAL)
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strOutput.add("cpuReservation.value");
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else
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{
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strOutput.addFmt("name_ukn{}", inst.op_r_name.name);
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}
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if (inst.type != PPCREC_IML_TYPE_R_NAME)
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{
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strOutput.add(", ");
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_name.regR, true);
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}
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}
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else if (inst.type == PPCREC_IML_TYPE_R_R)
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{
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strOutput.addFmt("{}", IMLDebug_GetOpcodeName(&inst));
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while ((sint32)strOutput.getLen() < lineOffsetParameters)
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strOutput.add(" ");
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_r.regR);
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_r.regA, true);
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}
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else if (inst.type == PPCREC_IML_TYPE_R_R_R)
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{
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strOutput.addFmt("{}", IMLDebug_GetOpcodeName(&inst));
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while ((sint32)strOutput.getLen() < lineOffsetParameters)
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strOutput.add(" ");
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_r_r.regR);
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_r_r.regA);
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_r_r.regB, true);
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}
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else if (inst.type == PPCREC_IML_TYPE_R_R_R_CARRY)
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{
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strOutput.addFmt("{}", IMLDebug_GetOpcodeName(&inst));
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while ((sint32)strOutput.getLen() < lineOffsetParameters)
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strOutput.add(" ");
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_r_r_carry.regR);
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_r_r_carry.regA);
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_r_r_carry.regB);
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_r_r_carry.regCarry, true);
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}
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else if (inst.type == PPCREC_IML_TYPE_COMPARE)
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{
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strOutput.add("CMP ");
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while ((sint32)strOutput.getLen() < lineOffsetParameters)
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strOutput.add(" ");
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IMLDebug_AppendRegisterParam(strOutput, inst.op_compare.regA);
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IMLDebug_AppendRegisterParam(strOutput, inst.op_compare.regB);
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strOutput.addFmt("{}", IMLDebug_GetConditionName(inst.op_compare.cond));
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strOutput.add(" -> ");
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IMLDebug_AppendRegisterParam(strOutput, inst.op_compare.regR, true);
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}
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else if (inst.type == PPCREC_IML_TYPE_COMPARE_S32)
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{
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strOutput.add("CMP ");
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while ((sint32)strOutput.getLen() < lineOffsetParameters)
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strOutput.add(" ");
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IMLDebug_AppendRegisterParam(strOutput, inst.op_compare_s32.regA);
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strOutput.addFmt("{}", inst.op_compare_s32.immS32);
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strOutput.addFmt(", {}", IMLDebug_GetConditionName(inst.op_compare_s32.cond));
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strOutput.add(" -> ");
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IMLDebug_AppendRegisterParam(strOutput, inst.op_compare_s32.regR, true);
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}
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else if (inst.type == PPCREC_IML_TYPE_CONDITIONAL_JUMP)
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{
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strOutput.add("CJUMP ");
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while ((sint32)strOutput.getLen() < lineOffsetParameters)
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strOutput.add(" ");
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IMLDebug_AppendRegisterParam(strOutput, inst.op_conditional_jump.registerBool, true);
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if (!inst.op_conditional_jump.mustBeTrue)
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strOutput.add("(inverted)");
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}
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else if (inst.type == PPCREC_IML_TYPE_JUMP)
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{
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strOutput.add("JUMP");
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}
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else if (inst.type == PPCREC_IML_TYPE_R_R_S32)
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{
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strOutput.addFmt("{}", IMLDebug_GetOpcodeName(&inst));
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while ((sint32)strOutput.getLen() < lineOffsetParameters)
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strOutput.add(" ");
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_r_s32.regR);
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_r_s32.regA);
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IMLDebug_AppendS32Param(strOutput, inst.op_r_r_s32.immS32, true);
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}
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else if (inst.type == PPCREC_IML_TYPE_R_R_S32_CARRY)
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{
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strOutput.addFmt("{}", IMLDebug_GetOpcodeName(&inst));
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while ((sint32)strOutput.getLen() < lineOffsetParameters)
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strOutput.add(" ");
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_r_s32_carry.regR);
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_r_s32_carry.regA);
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IMLDebug_AppendS32Param(strOutput, inst.op_r_r_s32_carry.immS32);
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_r_s32_carry.regCarry, true);
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}
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else if (inst.type == PPCREC_IML_TYPE_R_S32)
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{
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strOutput.addFmt("{}", IMLDebug_GetOpcodeName(&inst));
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while ((sint32)strOutput.getLen() < lineOffsetParameters)
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strOutput.add(" ");
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IMLDebug_AppendRegisterParam(strOutput, inst.op_r_immS32.regR);
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IMLDebug_AppendS32Param(strOutput, inst.op_r_immS32.immS32, true);
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}
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else if (inst.type == PPCREC_IML_TYPE_LOAD || inst.type == PPCREC_IML_TYPE_STORE ||
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inst.type == PPCREC_IML_TYPE_LOAD_INDEXED || inst.type == PPCREC_IML_TYPE_STORE_INDEXED)
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{
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if (inst.type == PPCREC_IML_TYPE_LOAD || inst.type == PPCREC_IML_TYPE_LOAD_INDEXED)
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strOutput.add("LD_");
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else
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strOutput.add("ST_");
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if (inst.op_storeLoad.flags2.signExtend)
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strOutput.add("S");
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else
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strOutput.add("U");
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strOutput.addFmt("{}", inst.op_storeLoad.copyWidth);
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while ((sint32)strOutput.getLen() < lineOffsetParameters)
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strOutput.add(" ");
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IMLDebug_AppendRegisterParam(strOutput, inst.op_storeLoad.registerData);
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if (inst.type == PPCREC_IML_TYPE_LOAD_INDEXED || inst.type == PPCREC_IML_TYPE_STORE_INDEXED)
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strOutput.addFmt("[{}+{}]", IMLDebug_GetRegName(inst.op_storeLoad.registerMem), IMLDebug_GetRegName(inst.op_storeLoad.registerMem2));
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else
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strOutput.addFmt("[{}+{}]", IMLDebug_GetRegName(inst.op_storeLoad.registerMem), inst.op_storeLoad.immS32);
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}
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else if (inst.type == PPCREC_IML_TYPE_ATOMIC_CMP_STORE)
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{
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strOutput.add("ATOMIC_ST_U32");
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while ((sint32)strOutput.getLen() < lineOffsetParameters)
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strOutput.add(" ");
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IMLDebug_AppendRegisterParam(strOutput, inst.op_atomic_compare_store.regEA);
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IMLDebug_AppendRegisterParam(strOutput, inst.op_atomic_compare_store.regCompareValue);
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IMLDebug_AppendRegisterParam(strOutput, inst.op_atomic_compare_store.regWriteValue);
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IMLDebug_AppendRegisterParam(strOutput, inst.op_atomic_compare_store.regBoolOut, true);
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}
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else if (inst.type == PPCREC_IML_TYPE_NO_OP)
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{
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strOutput.add("NOP");
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}
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else if (inst.type == PPCREC_IML_TYPE_MACRO)
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{
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if (inst.operation == PPCREC_IML_MACRO_B_TO_REG)
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{
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strOutput.addFmt("MACRO B_TO_REG {}", IMLDebug_GetRegName(inst.op_macro.paramReg));
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}
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else if (inst.operation == PPCREC_IML_MACRO_BL)
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{
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strOutput.addFmt("MACRO BL 0x{:08x} -> 0x{:08x} cycles (depr): {}", inst.op_macro.param, inst.op_macro.param2, (sint32)inst.op_macro.paramU16);
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}
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else if (inst.operation == PPCREC_IML_MACRO_B_FAR)
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{
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strOutput.addFmt("MACRO B_FAR 0x{:08x} -> 0x{:08x} cycles (depr): {}", inst.op_macro.param, inst.op_macro.param2, (sint32)inst.op_macro.paramU16);
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}
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else if (inst.operation == PPCREC_IML_MACRO_LEAVE)
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{
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strOutput.addFmt("MACRO LEAVE ppc: 0x{:08x}", inst.op_macro.param);
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}
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else if (inst.operation == PPCREC_IML_MACRO_HLE)
|
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{
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strOutput.addFmt("MACRO HLE ppcAddr: 0x{:08x} funcId: 0x{:08x}", inst.op_macro.param, inst.op_macro.param2);
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}
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else if (inst.operation == PPCREC_IML_MACRO_COUNT_CYCLES)
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{
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strOutput.addFmt("MACRO COUNT_CYCLES cycles: {}", inst.op_macro.param);
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}
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else
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{
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strOutput.addFmt("MACRO ukn operation {}", inst.operation);
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}
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}
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else if (inst.type == PPCREC_IML_TYPE_FPR_LOAD)
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{
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strOutput.addFmt("{} = ", IMLDebug_GetRegName(inst.op_storeLoad.registerData));
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if (inst.op_storeLoad.flags2.signExtend)
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strOutput.add("S");
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else
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strOutput.add("U");
|
||||
strOutput.addFmt("{} [{}+{}] mode {}", inst.op_storeLoad.copyWidth / 8, IMLDebug_GetRegName(inst.op_storeLoad.registerMem), inst.op_storeLoad.immS32, inst.op_storeLoad.mode);
|
||||
if (inst.op_storeLoad.flags2.notExpanded)
|
||||
{
|
||||
strOutput.addFmt(" <No expand>");
|
||||
}
|
||||
}
|
||||
else if (inst.type == PPCREC_IML_TYPE_FPR_STORE)
|
||||
{
|
||||
if (inst.op_storeLoad.flags2.signExtend)
|
||||
strOutput.add("S");
|
||||
else
|
||||
strOutput.add("U");
|
||||
strOutput.addFmt("{} [t{}+{}]", inst.op_storeLoad.copyWidth / 8, inst.op_storeLoad.registerMem.GetRegID(), inst.op_storeLoad.immS32);
|
||||
strOutput.addFmt(" = {} mode {}", IMLDebug_GetRegName(inst.op_storeLoad.registerData), inst.op_storeLoad.mode);
|
||||
}
|
||||
else if (inst.type == PPCREC_IML_TYPE_FPR_R_R)
|
||||
{
|
||||
strOutput.addFmt("{:>6} ", IMLDebug_GetOpcodeName(&inst));
|
||||
strOutput.addFmt("{}, {}", IMLDebug_GetRegName(inst.op_fpr_r_r.regR), IMLDebug_GetRegName(inst.op_fpr_r_r.regA));
|
||||
}
|
||||
else if (inst.type == PPCREC_IML_TYPE_FPR_R_R_R_R)
|
||||
{
|
||||
strOutput.addFmt("{:>6} ", IMLDebug_GetOpcodeName(&inst));
|
||||
strOutput.addFmt("{}, {}, {}, {}", IMLDebug_GetRegName(inst.op_fpr_r_r_r_r.regR), IMLDebug_GetRegName(inst.op_fpr_r_r_r_r.regA), IMLDebug_GetRegName(inst.op_fpr_r_r_r_r.regB), IMLDebug_GetRegName(inst.op_fpr_r_r_r_r.regC));
|
||||
}
|
||||
else if (inst.type == PPCREC_IML_TYPE_FPR_R_R_R)
|
||||
{
|
||||
strOutput.addFmt("{:>6} ", IMLDebug_GetOpcodeName(&inst));
|
||||
strOutput.addFmt("{}, {}, {}", IMLDebug_GetRegName(inst.op_fpr_r_r_r.regR), IMLDebug_GetRegName(inst.op_fpr_r_r_r.regA), IMLDebug_GetRegName(inst.op_fpr_r_r_r.regB));
|
||||
}
|
||||
else if (inst.type == PPCREC_IML_TYPE_CJUMP_CYCLE_CHECK)
|
||||
{
|
||||
strOutput.addFmt("CYCLE_CHECK");
|
||||
}
|
||||
else if (inst.type == PPCREC_IML_TYPE_X86_EFLAGS_JCC)
|
||||
{
|
||||
strOutput.addFmt("X86_JCC {}", IMLDebug_GetConditionName(inst.op_x86_eflags_jcc.cond));
|
||||
}
|
||||
else
|
||||
{
|
||||
strOutput.addFmt("Unknown iml type {}", inst.type);
|
||||
}
|
||||
disassemblyLineOut.assign(strOutput.c_str());
|
||||
}
|
||||
|
||||
void IMLDebug_DumpSegment(ppcImlGenContext_t* ctx, IMLSegment* imlSegment, bool printLivenessRangeInfo)
|
||||
{
|
||||
StringBuf strOutput(4096);
|
||||
|
||||
strOutput.addFmt("SEGMENT {} | PPC=0x{:08x} Loop-depth {}", IMLDebug_GetSegmentName(ctx, imlSegment), imlSegment->ppcAddress, imlSegment->loopDepth);
|
||||
if (imlSegment->isEnterable)
|
||||
{
|
||||
strOutput.addFmt(" ENTERABLE (0x{:08x})", imlSegment->enterPPCAddress);
|
||||
}
|
||||
if (imlSegment->deadCodeEliminationHintSeg)
|
||||
{
|
||||
strOutput.addFmt(" InheritOverwrite: {}", IMLDebug_GetSegmentName(ctx, imlSegment->deadCodeEliminationHintSeg));
|
||||
}
|
||||
cemuLog_log(LogType::Force, "{}", strOutput.c_str());
|
||||
|
||||
if (printLivenessRangeInfo)
|
||||
{
|
||||
strOutput.reset();
|
||||
IMLDebug_PrintLivenessRangeInfo(strOutput, imlSegment, RA_INTER_RANGE_START);
|
||||
cemuLog_log(LogType::Force, "{}", strOutput.c_str());
|
||||
}
|
||||
//debug_printf("\n");
|
||||
strOutput.reset();
|
||||
|
||||
std::string disassemblyLine;
|
||||
for (sint32 i = 0; i < imlSegment->imlList.size(); i++)
|
||||
{
|
||||
const IMLInstruction& inst = imlSegment->imlList[i];
|
||||
// don't log NOP instructions
|
||||
if (inst.type == PPCREC_IML_TYPE_NO_OP)
|
||||
continue;
|
||||
strOutput.reset();
|
||||
strOutput.addFmt("{:02x} ", i);
|
||||
//cemuLog_log(LogType::Force, "{:02x} ", i);
|
||||
disassemblyLine.clear();
|
||||
IMLDebug_DisassembleInstruction(inst, disassemblyLine);
|
||||
strOutput.add(disassemblyLine);
|
||||
if (printLivenessRangeInfo)
|
||||
{
|
||||
IMLDebug_PrintLivenessRangeInfo(strOutput, imlSegment, i);
|
||||
}
|
||||
cemuLog_log(LogType::Force, "{}", strOutput.c_str());
|
||||
}
|
||||
// all ranges
|
||||
if (printLivenessRangeInfo)
|
||||
{
|
||||
strOutput.reset();
|
||||
strOutput.add("Ranges-VirtReg ");
|
||||
raLivenessRange* subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
|
||||
while (subrangeItr)
|
||||
{
|
||||
strOutput.addFmt("v{:<4}", (uint32)subrangeItr->GetVirtualRegister());
|
||||
subrangeItr = subrangeItr->link_allSegmentRanges.next;
|
||||
}
|
||||
cemuLog_log(LogType::Force, "{}", strOutput.c_str());
|
||||
strOutput.reset();
|
||||
strOutput.add("Ranges-PhysReg ");
|
||||
subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
|
||||
while (subrangeItr)
|
||||
{
|
||||
strOutput.addFmt("p{:<4}", subrangeItr->GetPhysicalRegister());
|
||||
subrangeItr = subrangeItr->link_allSegmentRanges.next;
|
||||
}
|
||||
cemuLog_log(LogType::Force, "{}", strOutput.c_str());
|
||||
}
|
||||
// branch info
|
||||
strOutput.reset();
|
||||
strOutput.add("Links from: ");
|
||||
for (sint32 i = 0; i < imlSegment->list_prevSegments.size(); i++)
|
||||
{
|
||||
if (i)
|
||||
strOutput.add(", ");
|
||||
strOutput.addFmt("{}", IMLDebug_GetSegmentName(ctx, imlSegment->list_prevSegments[i]).c_str());
|
||||
}
|
||||
cemuLog_log(LogType::Force, "{}", strOutput.c_str());
|
||||
if (imlSegment->nextSegmentBranchNotTaken)
|
||||
cemuLog_log(LogType::Force, "BranchNotTaken: {}", IMLDebug_GetSegmentName(ctx, imlSegment->nextSegmentBranchNotTaken).c_str());
|
||||
if (imlSegment->nextSegmentBranchTaken)
|
||||
cemuLog_log(LogType::Force, "BranchTaken: {}", IMLDebug_GetSegmentName(ctx, imlSegment->nextSegmentBranchTaken).c_str());
|
||||
if (imlSegment->nextSegmentIsUncertain)
|
||||
cemuLog_log(LogType::Force, "Dynamic target");
|
||||
}
|
||||
|
||||
void IMLDebug_Dump(ppcImlGenContext_t* ppcImlGenContext, bool printLivenessRangeInfo)
|
||||
{
|
||||
for (size_t i = 0; i < ppcImlGenContext->segmentList2.size(); i++)
|
||||
{
|
||||
IMLDebug_DumpSegment(ppcImlGenContext, ppcImlGenContext->segmentList2[i], printLivenessRangeInfo);
|
||||
cemuLog_log(LogType::Force, "");
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue