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https://github.com/cemu-project/Cemu.git
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PPCRec: Add RA support for instructions with register constraints
Also make interval tracking more fine grained and differentiate between input and output edges of each instruction
This commit is contained in:
Exzap
parent
675c802cc1
commit
aa946ae42d
10 changed files with 2308 additions and 736 deletions
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@ -22,7 +22,6 @@ IMLName raLivenessRange::GetName() const
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void raLivenessRange::SetPhysicalRegister(sint32 physicalRegister)
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{
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cemu_assert_suspicious(); // not used yet
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this->physicalRegister = physicalRegister;
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}
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@ -68,6 +67,58 @@ boost::container::small_vector<raLivenessRange*, 32> raLivenessRange::GetAllSubr
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return subranges;
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}
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bool raLivenessRange::GetAllowedRegistersEx(IMLPhysRegisterSet& allowedRegisters)
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{
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if(interval2.ExtendsPreviousSegment() || interval2.ExtendsIntoNextSegment())
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{
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auto clusterRanges = GetAllSubrangesInCluster();
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bool hasAnyRequirement = false;
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for(auto& subrange : clusterRanges)
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{
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if(subrange->list_fixedRegRequirements.empty())
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continue;
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allowedRegisters = subrange->list_fixedRegRequirements.front().allowedReg;
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hasAnyRequirement = true;
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break;
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}
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if(!hasAnyRequirement)
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return false;
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for(auto& subrange : clusterRanges)
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{
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for(auto& fixedRegLoc : subrange->list_fixedRegRequirements)
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allowedRegisters &= fixedRegLoc.allowedReg;
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}
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}
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else
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{
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// local check only, slightly faster
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if(list_fixedRegRequirements.empty())
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return false;
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allowedRegisters = list_fixedRegRequirements.front().allowedReg;
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for(auto& fixedRegLoc : list_fixedRegRequirements)
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allowedRegisters &= fixedRegLoc.allowedReg;
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}
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return true;
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}
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IMLPhysRegisterSet raLivenessRange::GetAllowedRegisters(IMLPhysRegisterSet regPool)
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{
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IMLPhysRegisterSet fixedRegRequirements = regPool;
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if(interval2.ExtendsPreviousSegment() || interval2.ExtendsIntoNextSegment())
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{
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auto clusterRanges = GetAllSubrangesInCluster();
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for(auto& subrange : clusterRanges)
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{
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for(auto& fixedRegLoc : subrange->list_fixedRegRequirements)
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fixedRegRequirements &= fixedRegLoc.allowedReg;
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}
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return fixedRegRequirements;
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}
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for(auto& fixedRegLoc : list_fixedRegRequirements)
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fixedRegRequirements &= fixedRegLoc.allowedReg;
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return fixedRegRequirements;
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}
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void PPCRecRARange_addLink_perVirtualGPR(std::unordered_map<IMLRegID, raLivenessRange*>& root, raLivenessRange* subrange)
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{
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IMLRegID regId = subrange->GetVirtualRegister();
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@ -142,14 +193,19 @@ void PPCRecRARange_removeLink_allSegmentRanges(raLivenessRange** root, raLivenes
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MemoryPoolPermanentObjects<raLivenessRange> memPool_livenessSubrange(4096);
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raLivenessRange* PPCRecRA_createSubrange(ppcImlGenContext_t* ppcImlGenContext, IMLSegment* imlSegment, IMLRegID virtualRegister, IMLName name, sint32 startIndex, sint32 endIndex)
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// startPosition and endPosition are inclusive
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raLivenessRange* PPCRecRA_createSubrange2(ppcImlGenContext_t* ppcImlGenContext, IMLSegment* imlSegment, IMLRegID virtualRegister, IMLName name, raInstructionEdge startPosition, raInstructionEdge endPosition)
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{
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raLivenessRange* range = memPool_livenessSubrange.acquireObj();
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range->previousRanges.clear();
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range->list_locations.resize(0);
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range->list_locations.clear();
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range->list_fixedRegRequirements.clear();
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range->imlSegment = imlSegment;
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PPCRecompilerIml_setSegmentPoint(&range->start, imlSegment, startIndex);
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PPCRecompilerIml_setSegmentPoint(&range->end, imlSegment, endIndex);
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cemu_assert_debug(startPosition <= endPosition);
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range->interval2.start = startPosition;
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range->interval2.end = endPosition;
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// register mapping
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range->virtualRegister = virtualRegister;
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range->name = name;
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@ -160,6 +216,7 @@ raLivenessRange* PPCRecRA_createSubrange(ppcImlGenContext_t* ppcImlGenContext, I
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range->lastIterationIndex = 0;
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range->subrangeBranchNotTaken = nullptr;
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range->subrangeBranchTaken = nullptr;
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cemu_assert_debug(range->previousRanges.empty());
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range->_noLoad = false;
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// add to segment linked lists
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PPCRecRARange_addLink_perVirtualGPR(imlSegment->raInfo.linkedList_perVirtualRegister, range);
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@ -172,6 +229,22 @@ void _unlinkSubrange(raLivenessRange* subrange)
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IMLSegment* imlSegment = subrange->imlSegment;
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PPCRecRARange_removeLink_perVirtualGPR(imlSegment->raInfo.linkedList_perVirtualRegister, subrange);
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PPCRecRARange_removeLink_allSegmentRanges(&imlSegment->raInfo.linkedList_allSubranges, subrange);
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// unlink reverse references
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if(subrange->subrangeBranchTaken)
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subrange->subrangeBranchTaken->previousRanges.erase(std::find(subrange->subrangeBranchTaken->previousRanges.begin(), subrange->subrangeBranchTaken->previousRanges.end(), subrange));
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if(subrange->subrangeBranchNotTaken)
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subrange->subrangeBranchNotTaken->previousRanges.erase(std::find(subrange->subrangeBranchNotTaken->previousRanges.begin(), subrange->subrangeBranchNotTaken->previousRanges.end(), subrange));
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subrange->subrangeBranchTaken = (raLivenessRange*)(uintptr_t)-1;
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subrange->subrangeBranchNotTaken = (raLivenessRange*)(uintptr_t)-1;
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// remove forward references
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for(auto& prev : subrange->previousRanges)
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{
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if(prev->subrangeBranchTaken == subrange)
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prev->subrangeBranchTaken = nullptr;
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if(prev->subrangeBranchNotTaken == subrange)
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prev->subrangeBranchNotTaken = nullptr;
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}
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subrange->previousRanges.clear();
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}
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void PPCRecRA_deleteSubrange(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange* subrange)
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@ -179,14 +252,9 @@ void PPCRecRA_deleteSubrange(ppcImlGenContext_t* ppcImlGenContext, raLivenessRan
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_unlinkSubrange(subrange);
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//subrange->range->list_subranges.erase(std::find(subrange->range->list_subranges.begin(), subrange->range->list_subranges.end(), subrange));
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subrange->list_locations.clear();
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// unlink reverse references
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if(subrange->subrangeBranchTaken)
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subrange->subrangeBranchTaken->previousRanges.erase(std::find(subrange->subrangeBranchTaken->previousRanges.begin(), subrange->subrangeBranchTaken->previousRanges.end(), subrange));
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if(subrange->subrangeBranchNotTaken)
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subrange->subrangeBranchTaken->previousRanges.erase(std::find(subrange->subrangeBranchNotTaken->previousRanges.begin(), subrange->subrangeBranchNotTaken->previousRanges.end(), subrange));
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PPCRecompilerIml_removeSegmentPoint(&subrange->start);
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PPCRecompilerIml_removeSegmentPoint(&subrange->end);
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//PPCRecompilerIml_removeSegmentPoint(&subrange->interval.start);
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//PPCRecompilerIml_removeSegmentPoint(&subrange->interval.end);
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memPool_livenessSubrange.releaseObj(subrange);
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}
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@ -194,9 +262,18 @@ void PPCRecRA_deleteSubrange(ppcImlGenContext_t* ppcImlGenContext, raLivenessRan
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void _PPCRecRA_deleteSubrangeNoUnlink(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange* subrange)
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{
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_unlinkSubrange(subrange);
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PPCRecompilerIml_removeSegmentPoint(&subrange->start);
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PPCRecompilerIml_removeSegmentPoint(&subrange->end);
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//PPCRecompilerIml_removeSegmentPoint(&subrange->interval.start);
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//PPCRecompilerIml_removeSegmentPoint(&subrange->interval.end);
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memPool_livenessSubrange.releaseObj(subrange);
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// #ifdef CEMU_DEBUG_ASSERT
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// // DEBUG BEGIN
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// subrange->lastIterationIndex = 0xFFFFFFFE;
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// subrange->subrangeBranchTaken = (raLivenessRange*)(uintptr_t)-1;
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// subrange->subrangeBranchNotTaken = (raLivenessRange*)(uintptr_t)-1;
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//
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// // DEBUG END
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// #endif
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}
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void PPCRecRA_deleteSubrangeCluster(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange* subrange)
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@ -229,8 +306,8 @@ void PPCRecRA_mergeSubranges(ppcImlGenContext_t* ppcImlGenContext, raLivenessRan
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PPCRecRA_debugValidateSubrange(absorbedSubrange);
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if (subrange->imlSegment != absorbedSubrange->imlSegment)
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assert_dbg();
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if (subrange->end.index > absorbedSubrange->start.index)
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assert_dbg();
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cemu_assert_debug(subrange->interval2.end == absorbedSubrange->interval2.start);
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if (subrange->subrangeBranchTaken || subrange->subrangeBranchNotTaken)
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assert_dbg();
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if (subrange == absorbedSubrange)
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@ -238,21 +315,45 @@ void PPCRecRA_mergeSubranges(ppcImlGenContext_t* ppcImlGenContext, raLivenessRan
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#endif
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// update references
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if(absorbedSubrange->subrangeBranchTaken)
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*std::find(absorbedSubrange->subrangeBranchTaken->previousRanges.begin(), absorbedSubrange->subrangeBranchTaken->previousRanges.end(), absorbedSubrange) = subrange;
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if(absorbedSubrange->subrangeBranchNotTaken)
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*std::find(absorbedSubrange->subrangeBranchNotTaken->previousRanges.begin(), absorbedSubrange->subrangeBranchNotTaken->previousRanges.end(), absorbedSubrange) = subrange;
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subrange->subrangeBranchTaken = absorbedSubrange->subrangeBranchTaken;
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subrange->subrangeBranchNotTaken = absorbedSubrange->subrangeBranchNotTaken;
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absorbedSubrange->subrangeBranchTaken = nullptr;
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absorbedSubrange->subrangeBranchNotTaken = nullptr;
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if(subrange->subrangeBranchTaken)
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*std::find(subrange->subrangeBranchTaken->previousRanges.begin(), subrange->subrangeBranchTaken->previousRanges.end(), absorbedSubrange) = subrange;
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if(subrange->subrangeBranchNotTaken)
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*std::find(subrange->subrangeBranchNotTaken->previousRanges.begin(), subrange->subrangeBranchNotTaken->previousRanges.end(), absorbedSubrange) = subrange;
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// merge usage locations
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// at the merge point both ranges might track the same instruction, we handle this by first merging this duplicate location
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if(subrange && absorbedSubrange && !subrange->list_locations.empty() && !absorbedSubrange->list_locations.empty())
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{
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if(subrange->list_locations.back().index == absorbedSubrange->list_locations.front().index)
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{
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subrange->list_locations.back().isRead |= absorbedSubrange->list_locations.front().isRead;
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subrange->list_locations.back().isWrite |= absorbedSubrange->list_locations.front().isWrite;
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absorbedSubrange->list_locations.erase(absorbedSubrange->list_locations.begin()); // inefficient
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}
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}
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for (auto& location : absorbedSubrange->list_locations)
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{
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cemu_assert_debug(subrange->list_locations.empty() || (subrange->list_locations.back().index < location.index)); // todo - sometimes a subrange can contain the same instruction at the merge point if they are covering half of the instruction edge
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subrange->list_locations.push_back(location);
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}
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absorbedSubrange->list_locations.clear();
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// merge fixed reg locations
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#ifdef CEMU_DEBUG_ASSERT
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if(!subrange->list_fixedRegRequirements.empty() && !absorbedSubrange->list_fixedRegRequirements.empty())
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{
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cemu_assert_debug(subrange->list_fixedRegRequirements.back().pos < absorbedSubrange->list_fixedRegRequirements.front().pos);
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}
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#endif
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for (auto& fixedReg : absorbedSubrange->list_fixedRegRequirements)
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{
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subrange->list_fixedRegRequirements.push_back(fixedReg);
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}
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subrange->end.index = absorbedSubrange->end.index;
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subrange->interval2.end = absorbedSubrange->interval2.end;
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PPCRecRA_debugValidateSubrange(subrange);
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@ -262,16 +363,21 @@ void PPCRecRA_mergeSubranges(ppcImlGenContext_t* ppcImlGenContext, raLivenessRan
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// remove all inter-segment connections from the range cluster and split it into local ranges (also removes empty ranges)
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void PPCRecRA_explodeRange(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange* originRange)
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{
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cemu_assert_debug(originRange->interval2.ExtendsPreviousSegment() || originRange->interval2.ExtendsIntoNextSegment()); // only call this on ranges that span multiple segments
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auto clusterRanges = originRange->GetAllSubrangesInCluster();
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for (auto& subrange : clusterRanges)
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{
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if (subrange->list_locations.empty())
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continue;
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raLivenessRange* newSubrange = PPCRecRA_createSubrange(ppcImlGenContext, subrange->imlSegment, subrange->GetVirtualRegister(), subrange->GetName(), subrange->list_locations.data()[0].index, subrange->list_locations.data()[subrange->list_locations.size() - 1].index + 1);
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// copy locations
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for (auto& location : subrange->list_locations)
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raInterval interval;
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interval.SetInterval(subrange->list_locations.front().index, true, subrange->list_locations.back().index, true);
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raLivenessRange* newSubrange = PPCRecRA_createSubrange2(ppcImlGenContext, subrange->imlSegment, subrange->GetVirtualRegister(), subrange->GetName(), interval.start, interval.end);
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// copy locations and fixed reg indices
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newSubrange->list_locations = subrange->list_locations;
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newSubrange->list_fixedRegRequirements = subrange->list_fixedRegRequirements;
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if(originRange->HasPhysicalRegister())
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{
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newSubrange->list_locations.push_back(location);
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cemu_assert_debug(subrange->list_fixedRegRequirements.empty()); // avoid unassigning a register from a range with a fixed register requirement
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}
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}
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// remove subranges
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@ -279,82 +385,223 @@ void PPCRecRA_explodeRange(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange
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}
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#ifdef CEMU_DEBUG_ASSERT
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void PPCRecRA_debugValidateSubrange(raLivenessRange* subrange)
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void PPCRecRA_debugValidateSubrange(raLivenessRange* range)
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{
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// validate subrange
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if (subrange->subrangeBranchTaken && subrange->subrangeBranchTaken->imlSegment != subrange->imlSegment->nextSegmentBranchTaken)
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if (range->subrangeBranchTaken && range->subrangeBranchTaken->imlSegment != range->imlSegment->nextSegmentBranchTaken)
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assert_dbg();
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if (subrange->subrangeBranchNotTaken && subrange->subrangeBranchNotTaken->imlSegment != subrange->imlSegment->nextSegmentBranchNotTaken)
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if (range->subrangeBranchNotTaken && range->subrangeBranchNotTaken->imlSegment != range->imlSegment->nextSegmentBranchNotTaken)
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assert_dbg();
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if(range->subrangeBranchTaken || range->subrangeBranchNotTaken)
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{
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cemu_assert_debug(range->interval2.end.ConnectsToNextSegment());
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}
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if(!range->previousRanges.empty())
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{
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cemu_assert_debug(range->interval2.start.ConnectsToPreviousSegment());
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}
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// validate locations
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if (!range->list_locations.empty())
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{
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cemu_assert_debug(range->list_locations.front().index >= range->interval2.start.GetInstructionIndexEx());
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cemu_assert_debug(range->list_locations.back().index <= range->interval2.end.GetInstructionIndexEx());
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}
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}
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#else
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void PPCRecRA_debugValidateSubrange(raLivenessSubrange_t* subrange) {}
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void PPCRecRA_debugValidateSubrange(raLivenessRange* range) {}
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#endif
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// split subrange at the given index
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// After the split there will be two ranges and subranges:
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// since locations are per-instruction, but intervals are per-edge, it's possible that locations track reads/writes outside of the range
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// this function will remove any outside read/write locations
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void IMLRA_FixLocations(raLivenessRange* range)
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{
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if(range->list_locations.empty())
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return;
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if(range->interval2.start.IsInstructionIndex() && range->interval2.start.GetInstructionIndex() == range->list_locations.front().index)
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{
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auto& location = range->list_locations.front();
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if(range->interval2.start.IsOnOutputEdge())
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{
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location.isRead = false;
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if(!location.isRead && !location.isWrite)
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range->list_locations.erase(range->list_locations.begin());
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}
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}
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if(range->list_locations.empty())
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return;
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if(range->interval2.end.IsInstructionIndex() && range->interval2.end.GetInstructionIndex() == range->list_locations.back().index)
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{
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auto& location = range->list_locations.back();
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if(range->interval2.end.IsOnInputEdge())
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{
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location.isWrite = false;
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if(!location.isRead && !location.isWrite)
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range->list_locations.pop_back();
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}
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}
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}
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// trim start and end of range to match first and last read/write locations
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// does not trim start/endpoints which extend into the next/previous segment
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void IMLRA_TrimRangeToUse(raLivenessRange* range)
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{
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if(range->list_locations.empty())
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{
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// special case where we trim ranges extending from other segments to a single instruction edge
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cemu_assert_debug(!range->interval2.start.IsInstructionIndex() || !range->interval2.end.IsInstructionIndex());
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if(range->interval2.start.IsInstructionIndex())
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range->interval2.start = range->interval2.end;
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if(range->interval2.end.IsInstructionIndex())
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range->interval2.end = range->interval2.start;
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return;
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}
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raInterval prevInterval = range->interval2;
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// trim start
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if(range->interval2.start.IsInstructionIndex())
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{
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bool isInputEdge = range->list_locations.front().isRead;
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range->interval2.start.Set(range->list_locations.front().index, isInputEdge);
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}
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// trim end
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if(range->interval2.end.IsInstructionIndex())
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{
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bool isOutputEdge = range->list_locations.back().isWrite;
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range->interval2.end.Set(range->list_locations.back().index, !isOutputEdge);
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}
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// extra checks
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#ifdef CEMU_DEBUG_ASSERT
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cemu_assert_debug(range->interval2.start <= range->interval2.end);
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for(auto& loc : range->list_locations)
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{
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cemu_assert_debug(range->interval2.ContainsInstructionIndex(loc.index));
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}
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cemu_assert_debug(prevInterval.ContainsWholeInterval(range->interval2));
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#endif
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}
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// split range at the given position
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// After the split there will be two ranges:
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// head -> subrange is shortened to end at splitIndex (exclusive)
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// tail -> a new subrange that ranges from splitIndex (inclusive) to the end of the original subrange
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// if head has a physical register assigned it will not carry over to tail
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// The return value is the tail subrange
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// If trimToHole is true, the end of the head subrange and the start of the tail subrange will be moved to fit the locations
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// Ranges that begin at RA_INTER_RANGE_START are allowed and can be split
|
||||
raLivenessRange* PPCRecRA_splitLocalSubrange(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange* subrange, sint32 splitIndex, bool trimToHole)
|
||||
// The return value is the tail range
|
||||
// If trimToHole is true, the end of the head subrange and the start of the tail subrange will be shrunk to fit the read/write locations within them
|
||||
// the range after the split point does not inherit the physical register
|
||||
// if trimToHole is true and any of the halfes is empty, it will be deleted
|
||||
raLivenessRange* PPCRecRA_splitLocalSubrange2(ppcImlGenContext_t* ppcImlGenContext, raLivenessRange*& subrange, raInstructionEdge splitPosition, bool trimToHole)
|
||||
{
|
||||
// validation
|
||||
#ifdef CEMU_DEBUG_ASSERT
|
||||
//if (subrange->end.index == RA_INTER_RANGE_END || subrange->end.index == RA_INTER_RANGE_START)
|
||||
// assert_dbg();
|
||||
if (subrange->start.index == RA_INTER_RANGE_END || subrange->end.index == RA_INTER_RANGE_START)
|
||||
assert_dbg();
|
||||
if (subrange->start.index >= splitIndex)
|
||||
assert_dbg();
|
||||
if (subrange->end.index <= splitIndex)
|
||||
assert_dbg();
|
||||
#endif
|
||||
cemu_assert_debug(splitPosition.IsInstructionIndex());
|
||||
cemu_assert_debug(!subrange->interval2.IsNextSegmentOnly() && !subrange->interval2.IsPreviousSegmentOnly());
|
||||
cemu_assert_debug(subrange->interval2.ContainsEdge(splitPosition));
|
||||
// determine new intervals
|
||||
raInterval headInterval, tailInterval;
|
||||
headInterval.SetInterval(subrange->interval2.start, splitPosition-1);
|
||||
tailInterval.SetInterval(splitPosition, subrange->interval2.end);
|
||||
cemu_assert_debug(headInterval.start <= headInterval.end);
|
||||
cemu_assert_debug(tailInterval.start <= tailInterval.end);
|
||||
// create tail
|
||||
raLivenessRange* tailSubrange = PPCRecRA_createSubrange(ppcImlGenContext, subrange->imlSegment, subrange->GetVirtualRegister(), subrange->GetName(), splitIndex, subrange->end.index);
|
||||
// copy locations
|
||||
raLivenessRange* tailSubrange = PPCRecRA_createSubrange2(ppcImlGenContext, subrange->imlSegment, subrange->GetVirtualRegister(), subrange->GetName(), tailInterval.start, tailInterval.end);
|
||||
tailSubrange->SetPhysicalRegister(subrange->GetPhysicalRegister());
|
||||
// carry over branch targets and update reverse references
|
||||
tailSubrange->subrangeBranchTaken = subrange->subrangeBranchTaken;
|
||||
tailSubrange->subrangeBranchNotTaken = subrange->subrangeBranchNotTaken;
|
||||
subrange->subrangeBranchTaken = nullptr;
|
||||
subrange->subrangeBranchNotTaken = nullptr;
|
||||
if(tailSubrange->subrangeBranchTaken)
|
||||
*std::find(tailSubrange->subrangeBranchTaken->previousRanges.begin(), tailSubrange->subrangeBranchTaken->previousRanges.end(), subrange) = tailSubrange;
|
||||
if(tailSubrange->subrangeBranchNotTaken)
|
||||
*std::find(tailSubrange->subrangeBranchNotTaken->previousRanges.begin(), tailSubrange->subrangeBranchNotTaken->previousRanges.end(), subrange) = tailSubrange;
|
||||
// we assume that list_locations is ordered by instruction index and contains no duplicate indices, so lets check that here just in case
|
||||
#ifdef CEMU_DEBUG_ASSERT
|
||||
if(!subrange->list_locations.empty())
|
||||
{
|
||||
sint32 curIdx = -1;
|
||||
for(auto& location : subrange->list_locations)
|
||||
{
|
||||
cemu_assert_debug(curIdx < location.index);
|
||||
curIdx = location.index;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
// split locations
|
||||
// since there are 2 edges per instruction and locations track both via a single index, locations on the split point might need to be copied into both ranges
|
||||
for (auto& location : subrange->list_locations)
|
||||
{
|
||||
if (location.index >= splitIndex)
|
||||
if(tailInterval.ContainsInstructionIndex(location.index))
|
||||
tailSubrange->list_locations.push_back(location);
|
||||
}
|
||||
// remove tail locations from head
|
||||
for (sint32 i = 0; i < subrange->list_locations.size(); i++)
|
||||
{
|
||||
raLivenessLocation_t* location = subrange->list_locations.data() + i;
|
||||
if (location->index >= splitIndex)
|
||||
if (!headInterval.ContainsInstructionIndex(location->index))
|
||||
{
|
||||
subrange->list_locations.resize(i);
|
||||
break;
|
||||
}
|
||||
}
|
||||
// adjust start/end
|
||||
if (trimToHole)
|
||||
// split fixed reg requirements
|
||||
for (sint32 i = 0; i < subrange->list_fixedRegRequirements.size(); i++)
|
||||
{
|
||||
if (subrange->list_locations.empty())
|
||||
raFixedRegRequirement* fixedReg = subrange->list_fixedRegRequirements.data() + i;
|
||||
if (tailInterval.ContainsInstructionIndex(fixedReg->pos.GetInstructionIndex()))
|
||||
{
|
||||
subrange->end.index = subrange->start.index+1;
|
||||
tailSubrange->list_fixedRegRequirements.push_back(*fixedReg);
|
||||
}
|
||||
}
|
||||
// remove tail fixed reg requirements from head
|
||||
for (sint32 i = 0; i < subrange->list_fixedRegRequirements.size(); i++)
|
||||
{
|
||||
raFixedRegRequirement* fixedReg = subrange->list_fixedRegRequirements.data() + i;
|
||||
if (!headInterval.ContainsInstructionIndex(fixedReg->pos.GetInstructionIndex()))
|
||||
{
|
||||
subrange->list_fixedRegRequirements.resize(i);
|
||||
break;
|
||||
}
|
||||
}
|
||||
// adjust intervals
|
||||
subrange->interval2 = headInterval;
|
||||
tailSubrange->interval2 = tailInterval;
|
||||
// fix locations to only include read/write edges within the range
|
||||
if(subrange)
|
||||
IMLRA_FixLocations(subrange);
|
||||
if(tailSubrange)
|
||||
IMLRA_FixLocations(tailSubrange);
|
||||
// trim to hole
|
||||
if(trimToHole)
|
||||
{
|
||||
if(subrange->list_locations.empty() && (subrange->interval2.start.IsInstructionIndex() && subrange->interval2.end.IsInstructionIndex()))
|
||||
{
|
||||
PPCRecRA_deleteSubrange(ppcImlGenContext, subrange);
|
||||
subrange = nullptr;
|
||||
}
|
||||
else
|
||||
{
|
||||
subrange->end.index = subrange->list_locations.back().index + 1;
|
||||
IMLRA_TrimRangeToUse(subrange);
|
||||
}
|
||||
if (tailSubrange->list_locations.empty())
|
||||
if(tailSubrange->list_locations.empty() && (tailSubrange->interval2.start.IsInstructionIndex() && tailSubrange->interval2.end.IsInstructionIndex()))
|
||||
{
|
||||
assert_dbg(); // should not happen? (In this case we can just avoid generating a tail at all)
|
||||
PPCRecRA_deleteSubrange(ppcImlGenContext, tailSubrange);
|
||||
tailSubrange = nullptr;
|
||||
}
|
||||
else
|
||||
{
|
||||
tailSubrange->start.index = tailSubrange->list_locations.front().index;
|
||||
IMLRA_TrimRangeToUse(tailSubrange);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// set head range to end at split index
|
||||
subrange->end.index = splitIndex;
|
||||
}
|
||||
// validation
|
||||
cemu_assert_debug(!subrange || subrange->interval2.start <= subrange->interval2.end);
|
||||
cemu_assert_debug(!tailSubrange || tailSubrange->interval2.start <= tailSubrange->interval2.end);
|
||||
cemu_assert_debug(!tailSubrange || tailSubrange->interval2.start >= splitPosition);
|
||||
if (!trimToHole)
|
||||
cemu_assert_debug(!tailSubrange || tailSubrange->interval2.start == splitPosition);
|
||||
|
||||
if(subrange)
|
||||
PPCRecRA_debugValidateSubrange(subrange);
|
||||
if(tailSubrange)
|
||||
PPCRecRA_debugValidateSubrange(tailSubrange);
|
||||
return tailSubrange;
|
||||
}
|
||||
|
||||
|
|
@ -401,13 +648,13 @@ sint32 PPCRecRARange_estimateTotalCost(std::span<raLivenessRange*> ranges)
|
|||
|
||||
for (auto& subrange : ranges)
|
||||
{
|
||||
if (subrange->start.index != RA_INTER_RANGE_START)
|
||||
if (!subrange->interval2.ExtendsPreviousSegment())
|
||||
{
|
||||
//cost += PPCRecRARange_getReadWriteCost(subrange->imlSegment);
|
||||
mostExpensiveRead = std::max(mostExpensiveRead, PPCRecRARange_getReadWriteCost(subrange->imlSegment));
|
||||
readCount++;
|
||||
}
|
||||
if (subrange->end.index != RA_INTER_RANGE_END)
|
||||
if (!subrange->interval2.ExtendsIntoNextSegment())
|
||||
{
|
||||
//cost += PPCRecRARange_getReadWriteCost(subrange->imlSegment);
|
||||
mostExpensiveWrite = std::max(mostExpensiveWrite, PPCRecRARange_getReadWriteCost(subrange->imlSegment));
|
||||
|
|
@ -433,13 +680,14 @@ sint32 PPCRecRARange_estimateCostAfterRangeExplode(raLivenessRange* subrange)
|
|||
return cost;
|
||||
}
|
||||
|
||||
sint32 PPCRecRARange_estimateAdditionalCostAfterSplit(raLivenessRange* subrange, sint32 splitIndex)
|
||||
sint32 PPCRecRARange_estimateAdditionalCostAfterSplit(raLivenessRange* subrange, raInstructionEdge splitPosition)
|
||||
{
|
||||
// validation
|
||||
#ifdef CEMU_DEBUG_ASSERT
|
||||
if (subrange->end.index == RA_INTER_RANGE_END)
|
||||
if (subrange->interval2.ExtendsIntoNextSegment())
|
||||
assert_dbg();
|
||||
#endif
|
||||
cemu_assert_debug(splitPosition.IsInstructionIndex());
|
||||
|
||||
sint32 cost = 0;
|
||||
// find split position in location list
|
||||
|
|
@ -448,25 +696,15 @@ sint32 PPCRecRARange_estimateAdditionalCostAfterSplit(raLivenessRange* subrange,
|
|||
assert_dbg(); // should not happen?
|
||||
return 0;
|
||||
}
|
||||
if (splitIndex <= subrange->list_locations.front().index)
|
||||
sint32 splitInstructionIndex = splitPosition.GetInstructionIndex();
|
||||
if (splitInstructionIndex <= subrange->list_locations.front().index)
|
||||
return 0;
|
||||
if (splitIndex > subrange->list_locations.back().index)
|
||||
if (splitInstructionIndex > subrange->list_locations.back().index)
|
||||
return 0;
|
||||
|
||||
// todo - determine exact cost of split subranges
|
||||
|
||||
cost += PPCRecRARange_getReadWriteCost(subrange->imlSegment) * 2; // currently we assume that the additional region will require a read and a store
|
||||
|
||||
//for (sint32 f = 0; f < subrange->list_locations.size(); f++)
|
||||
//{
|
||||
// raLivenessLocation_t* location = subrange->list_locations.data() + f;
|
||||
// if (location->index >= splitIndex)
|
||||
// {
|
||||
// ...
|
||||
// return cost;
|
||||
// }
|
||||
//}
|
||||
|
||||
return cost;
|
||||
}
|
||||
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue