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PPCRec: Unify code + misc RA preparation
Whoopsie
This commit is contained in:
Exzap
parent
1f6f74d6ac
commit
948e33f9bf
5 changed files with 216 additions and 178 deletions
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@ -7,6 +7,8 @@
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#include "../BackendX64/BackendX64.h"
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#include <boost/container/small_vector.hpp>
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struct IMLRegisterAllocatorContext
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{
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IMLRegisterAllocatorParameters* raParam;
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@ -212,11 +214,67 @@ sint32 PPCRecRA_countInstructionsUntilNextLocalPhysRegisterUse(IMLSegment* imlSe
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return minDistance;
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}
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typedef struct
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struct IMLRALivenessTimeline
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{
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raLivenessSubrange_t* liveRangeList[64];
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sint32 liveRangesCount;
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}raLiveRangeInfo_t;
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// IMLRALivenessTimeline(raLivenessSubrange_t* subrangeChain)
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// {
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//#ifdef CEMU_DEBUG_ASSERT
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// raLivenessSubrange_t* it = subrangeChain;
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// raLivenessSubrange_t* prevIt = it;
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// while (it)
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// {
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// cemu_assert_debug(prevIt->start.index <= it->start.index);
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// prevIt = it;
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// it = it->link_segmentSubrangesGPR.next;
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// }
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//#endif
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// }
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IMLRALivenessTimeline()
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{
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}
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// manually add an active range
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void AddActiveRange(raLivenessSubrange_t* subrange)
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{
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activeRanges.emplace_back(subrange);
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}
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// remove all ranges from activeRanges with end <= instructionIndex
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void ExpireRanges(sint32 instructionIndex)
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{
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expiredRanges.clear();
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size_t count = activeRanges.size();
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for (size_t f = 0; f < count; f++)
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{
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raLivenessSubrange_t* liverange = activeRanges[f];
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if (liverange->end.index <= instructionIndex)
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{
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#ifdef CEMU_DEBUG_ASSERT
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if (instructionIndex != RA_INTER_RANGE_END && (liverange->subrangeBranchTaken || liverange->subrangeBranchNotTaken))
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assert_dbg(); // infinite subranges should not expire
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#endif
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expiredRanges.emplace_back(liverange);
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// remove entry
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activeRanges[f] = activeRanges[count-1];
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f--;
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count--;
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}
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}
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if(count != activeRanges.size())
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activeRanges.resize(count);
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}
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std::span<raLivenessSubrange_t*> GetExpiredRanges()
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{
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return { expiredRanges.data(), expiredRanges.size() };
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}
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boost::container::small_vector<raLivenessSubrange_t*, 64> activeRanges;
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private:
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boost::container::small_vector<raLivenessSubrange_t*, 16> expiredRanges;
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};
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bool IsRangeOverlapping(raLivenessSubrange_t* rangeA, raLivenessSubrange_t* rangeB)
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{
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@ -244,10 +302,6 @@ void PPCRecRA_MaskOverlappingPhysRegForGlobalRange(raLivenessRange_t* range, IML
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subrangeItr = subrangeItr->link_segmentSubrangesGPR.next;
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continue;
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}
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//if (subrange->start.index < subrangeItr->end.index && subrange->end.index > subrangeItr->start.index ||
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// (subrange->start.index == RA_INTER_RANGE_START && subrange->start.index == subrangeItr->start.index) ||
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// (subrange->end.index == RA_INTER_RANGE_END && subrange->end.index == subrangeItr->end.index) )
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if(IsRangeOverlapping(subrange, subrangeItr))
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{
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if (subrangeItr->range->physicalRegister >= 0)
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@ -312,84 +366,95 @@ void _sortSegmentAllSubrangesLinkedList(IMLSegment* imlSegment)
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#endif
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}
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void PPCRecRA_HandleFixedRegisters(ppcImlGenContext_t* ppcImlGenContext, IMLSegment* imlSegment)
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raLivenessSubrange_t* _GetSubrangeByInstructionIndexAndVirtualReg(IMLSegment* imlSegment, IMLReg regToSearch, sint32 instructionIndex)
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{
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uint32 regId = regToSearch & 0xFF;
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raLivenessSubrange_t* subrangeItr = imlSegment->raInfo.linkedList_perVirtualGPR[regId];
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while (subrangeItr)
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{
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if (subrangeItr->start.index <= instructionIndex && subrangeItr->end.index > instructionIndex)
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return subrangeItr;
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subrangeItr = subrangeItr->link_sameVirtualRegisterGPR.next;
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}
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return nullptr;
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}
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void IMLRA_IsolateRangeOnInstruction(ppcImlGenContext_t* ppcImlGenContext, IMLSegment* imlSegment, raLivenessSubrange_t* subrange, sint32 instructionIndex)
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{
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__debugbreak();
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}
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void IMLRA_HandleFixedRegisters(ppcImlGenContext_t* ppcImlGenContext, IMLSegment* imlSegment)
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{
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// this works as a pre-pass to actual register allocation. Assigning registers in advance based on fixed requirements (e.g. calling conventions and operations with fixed-reg input/output like x86 DIV/MUL)
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// algorithm goes as follows:
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// 1) Iterate all instructions from beginning to end and keep a list of covering ranges
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// 2) If we encounter an instruction with a fixed-register we:
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// 2) If we encounter an instruction with a fixed register we:
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// 2.0) Check if there are any other ranges already using the same fixed-register and if yes, we split them and unassign the register for any follow-up instructions just prior to the current instruction
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// 2.1) For inputs: Split the range that needs to be assigned a phys reg on the current instruction. Basically creating a 1-instruction long subrange that we can assign the physical register. RA will then schedule register allocation around that and avoid moves
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// 2.2) For outputs: Split the range that needs to be assigned a phys reg on the current instruction
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// Q: What if a specific fixed-register is used both for input and output and thus is destructive? A: Create temporary range
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// Q: What if we have 3 different inputs that are all the same virtual register? A: Create temporary range
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// Q: Assuming the above is implemented, do we even support overlapping two ranges of separate virtual regs on the same phys register? In theory the RA shouldn't care
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// assume imlSegment->raInfo.linkedList_allSubranges is ordered ascending by start index already
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// todo
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// experimental code
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//for (size_t i = 0; i < imlSegment->imlList.size(); i++)
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//{
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// IMLInstruction& inst = imlSegment->imlList[i];
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// if (inst.type == PPCREC_IML_TYPE_R_R_R)
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// {
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// if (inst.operation == PPCREC_IML_OP_LEFT_SHIFT)
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// {
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// // get the virtual reg which needs to be assigned a fixed register
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// //IMLUsedRegisters usedReg;
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// //inst.CheckRegisterUsage(&usedReg);
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// IMLReg rB = inst.op_r_r_r.regB;
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// // rB needs to use RCX/ECX
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// raLivenessSubrange_t* subrange = _GetSubrangeByInstructionIndexAndVirtualReg(imlSegment, rB, i);
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// cemu_assert_debug(subrange->range->physicalRegister < 0); // already has a phys reg assigned
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// // make sure RCX/ECX is free
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// // split before (if needed) and after instruction so that we get a new 1-instruction long range for which we can assign the physical register
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// raLivenessSubrange_t* instructionRange = subrange->start.index < i ? PPCRecRA_splitLocalSubrange(ppcImlGenContext, subrange, i, false) : subrange;
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// raLivenessSubrange_t* tailRange = PPCRecRA_splitLocalSubrange(ppcImlGenContext, instructionRange, i+1, false);
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// }
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// }
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//}
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}
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bool PPCRecRA_assignSegmentRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGenContext_t* ppcImlGenContext, IMLSegment* imlSegment)
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bool IMLRA_AssignSegmentRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGenContext_t* ppcImlGenContext, IMLSegment* imlSegment)
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{
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// sort subranges ascending by start index
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_sortSegmentAllSubrangesLinkedList(imlSegment);
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PPCRecRA_HandleFixedRegisters(ppcImlGenContext, imlSegment);
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raLiveRangeInfo_t liveInfo;
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liveInfo.liveRangesCount = 0;
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IMLRALivenessTimeline livenessTimeline;
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raLivenessSubrange_t* subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
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while(subrangeItr)
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{
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sint32 currentIndex = subrangeItr->start.index;
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// validate subrange
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PPCRecRA_debugValidateSubrange(subrangeItr);
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// expire ranges
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for (sint32 f = 0; f < liveInfo.liveRangesCount; f++)
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{
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raLivenessSubrange_t* liverange = liveInfo.liveRangeList[f];
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if (liverange->end.index <= currentIndex && liverange->end.index != RA_INTER_RANGE_END)
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{
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#ifdef CEMU_DEBUG_ASSERT
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if (liverange->subrangeBranchTaken || liverange->subrangeBranchNotTaken)
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assert_dbg(); // infinite subranges should not expire
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#endif
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// remove entry
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liveInfo.liveRangesCount--;
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liveInfo.liveRangeList[f] = liveInfo.liveRangeList[liveInfo.liveRangesCount];
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f--;
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}
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}
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// check if subrange already has register assigned
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livenessTimeline.ExpireRanges(std::min<sint32>(currentIndex, RA_INTER_RANGE_END-1)); // expire up to currentIndex (inclusive), but exclude infinite ranges
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// if subrange already has register assigned then add it to the active list and continue
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if (subrangeItr->range->physicalRegister >= 0)
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{
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// verify if register is actually available
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#ifdef CEMU_DEBUG_ASSERT
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for (sint32 f = 0; f < liveInfo.liveRangesCount; f++)
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for (auto& liverangeItr : livenessTimeline.activeRanges)
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{
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raLivenessSubrange_t* liverangeItr = liveInfo.liveRangeList[f];
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if (liverangeItr->range->physicalRegister == subrangeItr->range->physicalRegister)
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{
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// this should never happen because we try to preventively avoid register conflicts
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assert_dbg();
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}
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// check for register mismatch
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cemu_assert_debug(liverangeItr->range->physicalRegister != subrangeItr->range->physicalRegister);
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}
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#endif
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// add to live ranges
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liveInfo.liveRangeList[liveInfo.liveRangesCount] = subrangeItr;
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liveInfo.liveRangesCount++;
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// next
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livenessTimeline.AddActiveRange(subrangeItr);
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subrangeItr = subrangeItr->link_segmentSubrangesGPR.next;
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continue;
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}
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// find free register for this segment
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// find free register for current subrangeItr and segment
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IMLPhysRegisterSet physRegSet = ctx.raParam->physicalRegisterPool;
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for (sint32 f = 0; f < liveInfo.liveRangesCount; f++)
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for (auto& liverangeItr : livenessTimeline.activeRanges)
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{
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raLivenessSubrange_t* liverange = liveInfo.liveRangeList[f];
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cemu_assert_debug(liverange->range->physicalRegister >= 0);
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physRegSet.SetReserved(liverange->range->physicalRegister);
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cemu_assert_debug(liverangeItr->range->physicalRegister >= 0);
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physRegSet.SetReserved(liverangeItr->range->physicalRegister);
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}
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// check intersections with other ranges and determine allowed registers
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IMLPhysRegisterSet localAvailableRegsMask = physRegSet; // mask of registers that are currently not used (does not include range checks in other segments)
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@ -449,9 +514,8 @@ bool PPCRecRA_assignSegmentRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGen
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spillStrategies.localRangeHoleCutting.cost = INT_MAX;
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if (currentIndex >= 0)
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{
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for (sint32 f = 0; f < liveInfo.liveRangesCount; f++)
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for (auto candidate : livenessTimeline.activeRanges)
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{
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raLivenessSubrange_t* candidate = liveInfo.liveRangeList[f];
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if (candidate->end.index == RA_INTER_RANGE_END)
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continue;
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sint32 distance = PPCRecRA_countInstructionsUntilNextUse(candidate, currentIndex);
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@ -513,12 +577,11 @@ bool PPCRecRA_assignSegmentRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGen
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spillStrategies.explodeRange.cost = INT_MAX;
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spillStrategies.explodeRange.range = nullptr;
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spillStrategies.explodeRange.distance = -1;
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for (sint32 f = 0; f < liveInfo.liveRangesCount; f++)
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for (auto candidate : livenessTimeline.activeRanges)
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{
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raLivenessSubrange_t* candidate = liveInfo.liveRangeList[f];
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if (candidate->end.index != RA_INTER_RANGE_END)
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continue;
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sint32 distance = PPCRecRA_countInstructionsUntilNextUse(liveInfo.liveRangeList[f], currentIndex);
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sint32 distance = PPCRecRA_countInstructionsUntilNextUse(candidate, currentIndex);
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if( distance < 2)
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continue;
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sint32 cost;
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@ -580,9 +643,8 @@ bool PPCRecRA_assignSegmentRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGen
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spillStrategies.explodeRange.cost = INT_MAX;
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spillStrategies.explodeRange.range = nullptr;
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spillStrategies.explodeRange.distance = -1;
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for (sint32 f = 0; f < liveInfo.liveRangesCount; f++)
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for(auto candidate : livenessTimeline.activeRanges)
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{
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raLivenessSubrange_t* candidate = liveInfo.liveRangeList[f];
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if (candidate->end.index != RA_INTER_RANGE_END)
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continue;
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// only select candidates that clash with current subrange
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@ -616,16 +678,14 @@ bool PPCRecRA_assignSegmentRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGen
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}
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// assign register to range
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subrangeItr->range->physicalRegister = physRegSet.GetFirstAvailableReg();
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// add to live ranges
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liveInfo.liveRangeList[liveInfo.liveRangesCount] = subrangeItr;
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liveInfo.liveRangesCount++;
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livenessTimeline.AddActiveRange(subrangeItr);
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// next
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subrangeItr = subrangeItr->link_segmentSubrangesGPR.next;
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}
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return true;
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}
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void PPCRecRA_assignRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGenContext_t* ppcImlGenContext)
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void IMLRA_AssignRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGenContext_t* ppcImlGenContext)
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{
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// start with frequently executed segments first
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sint32 maxLoopDepth = 0;
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@ -633,6 +693,10 @@ void PPCRecRA_assignRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGenContext
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{
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maxLoopDepth = std::max(maxLoopDepth, segIt->loopDepth);
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}
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// assign fixed registers first
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for (IMLSegment* segIt : ppcImlGenContext->segmentList2)
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IMLRA_HandleFixedRegisters(ppcImlGenContext, segIt);
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while (true)
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{
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bool done = false;
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@ -642,7 +706,7 @@ void PPCRecRA_assignRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGenContext
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{
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if (segIt->loopDepth != d)
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continue;
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done = PPCRecRA_assignSegmentRegisters(ctx, ppcImlGenContext, segIt);
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done = IMLRA_AssignSegmentRegisters(ctx, ppcImlGenContext, segIt);
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if (done == false)
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break;
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}
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@ -654,12 +718,12 @@ void PPCRecRA_assignRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGenContext
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}
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}
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typedef struct
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struct subrangeEndingInfo_t
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{
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raLivenessSubrange_t* subrangeList[SUBRANGE_LIST_SIZE];
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sint32 subrangeCount;
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bool hasUndefinedEndings;
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}subrangeEndingInfo_t;
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};
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void _findSubrangeWriteEndings(raLivenessSubrange_t* subrange, uint32 iterationIndex, sint32 depth, subrangeEndingInfo_t* info)
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{
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@ -759,14 +823,13 @@ void _analyzeRangeDataFlow(raLivenessSubrange_t* subrange)
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}
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}
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void PPCRecRA_generateSegmentInstructions(ppcImlGenContext_t* ppcImlGenContext, IMLSegment* imlSegment)
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void IMLRA_GenerateSegmentInstructions(ppcImlGenContext_t* ppcImlGenContext, IMLSegment* imlSegment)
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{
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sint16 virtualReg2PhysReg[IML_RA_VIRT_REG_COUNT_MAX];
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for (sint32 i = 0; i < IML_RA_VIRT_REG_COUNT_MAX; i++)
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virtualReg2PhysReg[i] = -1;
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std::unordered_map<IMLReg, IMLReg> virt2PhysRegMap; // key = virtual register, value = physical register
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raLiveRangeInfo_t liveInfo;
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liveInfo.liveRangesCount = 0;
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IMLRALivenessTimeline livenessTimeline;
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sint32 index = 0;
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sint32 suffixInstructionCount = imlSegment->HasSuffixInstruction() ? 1 : 0;
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// load register ranges that are supplied from previous segments
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@ -775,8 +838,7 @@ void PPCRecRA_generateSegmentInstructions(ppcImlGenContext_t* ppcImlGenContext,
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{
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if (subrangeItr->start.index == RA_INTER_RANGE_START)
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{
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liveInfo.liveRangeList[liveInfo.liveRangesCount] = subrangeItr;
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liveInfo.liveRangesCount++;
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livenessTimeline.AddActiveRange(subrangeItr);
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#ifdef CEMU_DEBUG_ASSERT
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// load GPR
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if (subrangeItr->_noLoad == false)
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@ -797,41 +859,34 @@ void PPCRecRA_generateSegmentInstructions(ppcImlGenContext_t* ppcImlGenContext,
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while(index < imlSegment->imlList.size() + 1)
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{
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// expire ranges
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for (sint32 f = 0; f < liveInfo.liveRangesCount; f++)
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livenessTimeline.ExpireRanges(index);
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for (auto& expiredRange : livenessTimeline.GetExpiredRanges())
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{
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raLivenessSubrange_t* liverange = liveInfo.liveRangeList[f];
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if (liverange->end.index <= index)
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// update translation table
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if (virtualReg2PhysReg[expiredRange->range->virtualRegister] == -1)
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assert_dbg();
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virtualReg2PhysReg[expiredRange->range->virtualRegister] = -1;
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virt2PhysRegMap.erase(expiredRange->range->virtualRegister);
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// store GPR if required
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// special care has to be taken to execute any stores before the suffix instruction since trailing instructions may not get executed
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if (expiredRange->hasStore)
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{
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// update translation table
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if (virtualReg2PhysReg[liverange->range->virtualRegister] == -1)
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assert_dbg();
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virtualReg2PhysReg[liverange->range->virtualRegister] = -1;
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virt2PhysRegMap.erase(liverange->range->virtualRegister);
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// store GPR if required
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// special care has to be taken to execute any stores before the suffix instruction since trailing instructions may not get executed
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if (liverange->hasStore)
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{
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PPCRecRA_insertGPRStoreInstruction(imlSegment, std::min<sint32>(index, imlSegment->imlList.size() - suffixInstructionCount), liverange->range->physicalRegister, liverange->range->name);
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index++;
|
||||
}
|
||||
// remove entry
|
||||
liveInfo.liveRangesCount--;
|
||||
liveInfo.liveRangeList[f] = liveInfo.liveRangeList[liveInfo.liveRangesCount];
|
||||
f--;
|
||||
PPCRecRA_insertGPRStoreInstruction(imlSegment, std::min<sint32>(index, imlSegment->imlList.size() - suffixInstructionCount), expiredRange->range->physicalRegister, expiredRange->range->name);
|
||||
index++;
|
||||
}
|
||||
}
|
||||
|
||||
// load new ranges
|
||||
subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
|
||||
while(subrangeItr)
|
||||
{
|
||||
if (subrangeItr->start.index == index)
|
||||
{
|
||||
liveInfo.liveRangeList[liveInfo.liveRangesCount] = subrangeItr;
|
||||
liveInfo.liveRangesCount++;
|
||||
livenessTimeline.AddActiveRange(subrangeItr);
|
||||
// load GPR
|
||||
// similar to stores, any loads for the next segment need to happen before the suffix instruction
|
||||
// however, starting 17-12-2022 ranges that exit the segment at the end but do not cover the suffix instruction are illegal (e.g. RA_INTER_RANGE_END to RA_INTER_RANGE_END subrange)
|
||||
// the limitation that name loads (for the follow-up segments) need to happen before the suffix instruction require that the range also reflects this, otherwise the RA would erroneously assume registers to be available during the suffix instruction
|
||||
// however, ranges that exit the segment at the end but do not cover the suffix instruction are illegal (e.g. RA_INTER_RANGE_END to RA_INTER_RANGE_END subrange)
|
||||
// this is to prevent the RA from inserting store/load instructions after the suffix instruction
|
||||
if (imlSegment->HasSuffixInstruction())
|
||||
{
|
||||
cemu_assert_debug(subrangeItr->start.index <= imlSegment->GetSuffixInstructionIndex());
|
||||
|
|
@ -855,35 +910,25 @@ void PPCRecRA_generateSegmentInstructions(ppcImlGenContext_t* ppcImlGenContext,
|
|||
// next iml instruction
|
||||
index++;
|
||||
}
|
||||
// expire infinite subranges (subranges that cross the segment border)
|
||||
// expire infinite subranges (subranges which cross the segment border)
|
||||
sint32 storeLoadListLength = 0;
|
||||
raLoadStoreInfo_t loadStoreList[IML_RA_VIRT_REG_COUNT_MAX];
|
||||
for (sint32 f = 0; f < liveInfo.liveRangesCount; f++)
|
||||
livenessTimeline.ExpireRanges(RA_INTER_RANGE_END);
|
||||
for (auto liverange : livenessTimeline.GetExpiredRanges())
|
||||
{
|
||||
raLivenessSubrange_t* liverange = liveInfo.liveRangeList[f];
|
||||
if (liverange->end.index == RA_INTER_RANGE_END)
|
||||
// update translation table
|
||||
cemu_assert_debug(virtualReg2PhysReg[liverange->range->virtualRegister] != -1);
|
||||
virtualReg2PhysReg[liverange->range->virtualRegister] = -1;
|
||||
virt2PhysRegMap.erase(liverange->range->virtualRegister);
|
||||
// store GPR
|
||||
if (liverange->hasStore)
|
||||
{
|
||||
// update translation table
|
||||
cemu_assert_debug(virtualReg2PhysReg[liverange->range->virtualRegister] != -1);
|
||||
virtualReg2PhysReg[liverange->range->virtualRegister] = -1;
|
||||
virt2PhysRegMap.erase(liverange->range->virtualRegister);
|
||||
// store GPR
|
||||
if (liverange->hasStore)
|
||||
{
|
||||
loadStoreList[storeLoadListLength].registerIndex = liverange->range->physicalRegister;
|
||||
loadStoreList[storeLoadListLength].registerName = liverange->range->name;
|
||||
storeLoadListLength++;
|
||||
}
|
||||
// remove entry
|
||||
liveInfo.liveRangesCount--;
|
||||
liveInfo.liveRangeList[f] = liveInfo.liveRangeList[liveInfo.liveRangesCount];
|
||||
f--;
|
||||
}
|
||||
else
|
||||
{
|
||||
cemu_assert_suspicious();
|
||||
loadStoreList[storeLoadListLength].registerIndex = liverange->range->physicalRegister;
|
||||
loadStoreList[storeLoadListLength].registerName = liverange->range->name;
|
||||
storeLoadListLength++;
|
||||
}
|
||||
}
|
||||
cemu_assert_debug(livenessTimeline.activeRanges.empty());
|
||||
if (storeLoadListLength > 0)
|
||||
{
|
||||
PPCRecRA_insertGPRStoreInstructions(imlSegment, imlSegment->imlList.size() - suffixInstructionCount, loadStoreList, storeLoadListLength);
|
||||
|
|
@ -895,8 +940,7 @@ void PPCRecRA_generateSegmentInstructions(ppcImlGenContext_t* ppcImlGenContext,
|
|||
{
|
||||
if (subrangeItr->start.index == RA_INTER_RANGE_END)
|
||||
{
|
||||
liveInfo.liveRangeList[liveInfo.liveRangesCount] = subrangeItr;
|
||||
liveInfo.liveRangesCount++;
|
||||
livenessTimeline.AddActiveRange(subrangeItr);
|
||||
// load GPR
|
||||
if (subrangeItr->_noLoad == false)
|
||||
{
|
||||
|
|
@ -918,20 +962,20 @@ void PPCRecRA_generateSegmentInstructions(ppcImlGenContext_t* ppcImlGenContext,
|
|||
}
|
||||
}
|
||||
|
||||
void PPCRecRA_generateMoveInstructions(ppcImlGenContext_t* ppcImlGenContext)
|
||||
void IMLRA_GenerateMoveInstructions(ppcImlGenContext_t* ppcImlGenContext)
|
||||
{
|
||||
for (size_t s = 0; s < ppcImlGenContext->segmentList2.size(); s++)
|
||||
{
|
||||
IMLSegment* imlSegment = ppcImlGenContext->segmentList2[s];
|
||||
PPCRecRA_generateSegmentInstructions(ppcImlGenContext, imlSegment);
|
||||
IMLRA_GenerateSegmentInstructions(ppcImlGenContext, imlSegment);
|
||||
}
|
||||
}
|
||||
|
||||
void PPCRecRA_calculateLivenessRangesV2(ppcImlGenContext_t* ppcImlGenContext);
|
||||
void PPCRecRA_processFlowAndCalculateLivenessRangesV2(ppcImlGenContext_t* ppcImlGenContext);
|
||||
void PPCRecRA_analyzeRangeDataFlowV2(ppcImlGenContext_t* ppcImlGenContext);
|
||||
void IMLRA_CalculateLivenessRanges(ppcImlGenContext_t* ppcImlGenContext);
|
||||
void IMLRA_ProcessFlowAndCalculateLivenessRanges(ppcImlGenContext_t* ppcImlGenContext);
|
||||
void IMLRA_AnalyzeRangeDataFlow(ppcImlGenContext_t* ppcImlGenContext);
|
||||
|
||||
void PPCRecompilerImm_reshapeForRegisterAllocation(ppcImlGenContext_t* ppcImlGenContext)
|
||||
void IMLRA_ReshapeForRegisterAllocation(ppcImlGenContext_t* ppcImlGenContext)
|
||||
{
|
||||
// insert empty segments after every non-taken branch if the linked segment has more than one input
|
||||
// this gives the register allocator more room to create efficient spill code
|
||||
|
|
@ -986,16 +1030,16 @@ void IMLRegisterAllocator_AllocateRegisters(ppcImlGenContext_t* ppcImlGenContext
|
|||
IMLRegisterAllocatorContext ctx;
|
||||
ctx.raParam = &raParam;
|
||||
|
||||
PPCRecompilerImm_reshapeForRegisterAllocation(ppcImlGenContext);
|
||||
IMLRA_ReshapeForRegisterAllocation(ppcImlGenContext);
|
||||
|
||||
ppcImlGenContext->raInfo.list_ranges = std::vector<raLivenessRange_t*>();
|
||||
|
||||
PPCRecRA_calculateLivenessRangesV2(ppcImlGenContext);
|
||||
PPCRecRA_processFlowAndCalculateLivenessRangesV2(ppcImlGenContext);
|
||||
PPCRecRA_assignRegisters(ctx, ppcImlGenContext);
|
||||
IMLRA_CalculateLivenessRanges(ppcImlGenContext);
|
||||
IMLRA_ProcessFlowAndCalculateLivenessRanges(ppcImlGenContext);
|
||||
IMLRA_AssignRegisters(ctx, ppcImlGenContext);
|
||||
|
||||
PPCRecRA_analyzeRangeDataFlowV2(ppcImlGenContext);
|
||||
PPCRecRA_generateMoveInstructions(ppcImlGenContext);
|
||||
IMLRA_AnalyzeRangeDataFlow(ppcImlGenContext);
|
||||
IMLRA_GenerateMoveInstructions(ppcImlGenContext);
|
||||
|
||||
PPCRecRA_deleteAllRanges(ppcImlGenContext);
|
||||
}
|
||||
|
|
@ -1028,7 +1072,7 @@ void PPCRecRA_calculateSegmentMinMaxRanges(ppcImlGenContext_t* ppcImlGenContext,
|
|||
}
|
||||
}
|
||||
|
||||
void PPCRecRA_calculateLivenessRangesV2(ppcImlGenContext_t* ppcImlGenContext)
|
||||
void IMLRA_CalculateLivenessRanges(ppcImlGenContext_t* ppcImlGenContext)
|
||||
{
|
||||
// for each register calculate min/max index of usage range within each segment
|
||||
for (IMLSegment* segIt : ppcImlGenContext->segmentList2)
|
||||
|
|
@ -1338,7 +1382,7 @@ void PPCRecRA_extendRangesOutOfLoopsV2(ppcImlGenContext_t* ppcImlGenContext)
|
|||
}
|
||||
}
|
||||
|
||||
void PPCRecRA_processFlowAndCalculateLivenessRangesV2(ppcImlGenContext_t* ppcImlGenContext)
|
||||
void IMLRA_ProcessFlowAndCalculateLivenessRanges(ppcImlGenContext_t* ppcImlGenContext)
|
||||
{
|
||||
// merge close ranges
|
||||
PPCRecRA_mergeCloseRangesV2(ppcImlGenContext);
|
||||
|
|
@ -1377,7 +1421,7 @@ void PPCRecRA_analyzeSubrangeDataDependencyV2(raLivenessSubrange_t* subrange)
|
|||
subrange->_noLoad = true;
|
||||
}
|
||||
|
||||
void PPCRecRA_analyzeRangeDataFlowV2(ppcImlGenContext_t* ppcImlGenContext)
|
||||
void IMLRA_AnalyzeRangeDataFlow(ppcImlGenContext_t* ppcImlGenContext)
|
||||
{
|
||||
// this function is called after _assignRegisters(), which means that all ranges are already final and wont change anymore
|
||||
// first do a per-subrange pass
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue