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PPCRec: Simplify RA code and clean it up a bit
This commit is contained in:
Exzap
parent
f55b842773
commit
675c802cc1
7 changed files with 466 additions and 414 deletions
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@ -50,10 +50,9 @@ struct IMLRegisterAllocatorContext
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};
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uint32 recRACurrentIterationIndex = 0;
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uint32 PPCRecRA_getNextIterationIndex()
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{
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static uint32 recRACurrentIterationIndex = 0;
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recRACurrentIterationIndex++;
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return recRACurrentIterationIndex;
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}
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@ -120,7 +119,7 @@ void PPCRecRA_identifyLoop(ppcImlGenContext_t* ppcImlGenContext, IMLSegment* iml
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#define SUBRANGE_LIST_SIZE (128)
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sint32 PPCRecRA_countInstructionsUntilNextUse(raLivenessSubrange_t* subrange, sint32 startIndex)
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sint32 PPCRecRA_countInstructionsUntilNextUse(raLivenessRange* subrange, sint32 startIndex)
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{
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for (sint32 i = 0; i < subrange->list_locations.size(); i++)
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{
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@ -135,12 +134,12 @@ sint32 PPCRecRA_countInstructionsUntilNextLocalPhysRegisterUse(IMLSegment* imlSe
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{
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sint32 minDistance = INT_MAX;
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// next
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raLivenessSubrange_t* subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
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raLivenessRange* subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
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while(subrangeItr)
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{
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if (subrangeItr->range->physicalRegister != physRegister)
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if (subrangeItr->GetPhysicalRegister() != physRegister)
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{
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subrangeItr = subrangeItr->link_segmentSubrangesGPR.next;
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subrangeItr = subrangeItr->link_allSegmentRanges.next;
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continue;
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}
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if (startIndex >= subrangeItr->start.index && startIndex < subrangeItr->end.index)
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@ -149,7 +148,7 @@ sint32 PPCRecRA_countInstructionsUntilNextLocalPhysRegisterUse(IMLSegment* imlSe
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{
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minDistance = std::min(minDistance, (subrangeItr->start.index - startIndex));
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}
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subrangeItr = subrangeItr->link_segmentSubrangesGPR.next;
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subrangeItr = subrangeItr->link_allSegmentRanges.next;
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}
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return minDistance;
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}
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@ -175,7 +174,7 @@ struct IMLRALivenessTimeline
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}
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// manually add an active range
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void AddActiveRange(raLivenessSubrange_t* subrange)
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void AddActiveRange(raLivenessRange* subrange)
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{
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activeRanges.emplace_back(subrange);
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}
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@ -187,7 +186,7 @@ struct IMLRALivenessTimeline
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size_t count = activeRanges.size();
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for (size_t f = 0; f < count; f++)
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{
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raLivenessSubrange_t* liverange = activeRanges[f];
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raLivenessRange* liverange = activeRanges[f];
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if (liverange->end.index <= instructionIndex)
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{
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#ifdef CEMU_DEBUG_ASSERT
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@ -205,18 +204,18 @@ struct IMLRALivenessTimeline
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activeRanges.resize(count);
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}
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std::span<raLivenessSubrange_t*> GetExpiredRanges()
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std::span<raLivenessRange*> GetExpiredRanges()
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{
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return { expiredRanges.data(), expiredRanges.size() };
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}
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boost::container::small_vector<raLivenessSubrange_t*, 64> activeRanges;
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boost::container::small_vector<raLivenessRange*, 64> activeRanges;
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private:
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boost::container::small_vector<raLivenessSubrange_t*, 16> expiredRanges;
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boost::container::small_vector<raLivenessRange*, 16> expiredRanges;
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};
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bool IsRangeOverlapping(raLivenessSubrange_t* rangeA, raLivenessSubrange_t* rangeB)
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bool IsRangeOverlapping(raLivenessRange* rangeA, raLivenessRange* rangeB)
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{
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if (rangeA->start.index < rangeB->end.index && rangeA->end.index > rangeB->start.index)
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return true;
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@ -228,39 +227,40 @@ bool IsRangeOverlapping(raLivenessSubrange_t* rangeA, raLivenessSubrange_t* rang
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}
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// mark occupied registers by any overlapping range as unavailable in physRegSet
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void PPCRecRA_MaskOverlappingPhysRegForGlobalRange(raLivenessRange_t* range, IMLPhysRegisterSet& physRegSet)
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void PPCRecRA_MaskOverlappingPhysRegForGlobalRange(raLivenessRange* range2, IMLPhysRegisterSet& physRegSet)
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{
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for (auto& subrange : range->list_subranges)
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auto clusterRanges = range2->GetAllSubrangesInCluster();
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for (auto& subrange : clusterRanges)
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{
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IMLSegment* imlSegment = subrange->imlSegment;
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raLivenessSubrange_t* subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
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raLivenessRange* subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
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while(subrangeItr)
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{
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if (subrange == subrangeItr)
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{
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// next
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subrangeItr = subrangeItr->link_segmentSubrangesGPR.next;
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subrangeItr = subrangeItr->link_allSegmentRanges.next;
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continue;
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}
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if(IsRangeOverlapping(subrange, subrangeItr))
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{
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if (subrangeItr->range->physicalRegister >= 0)
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physRegSet.SetReserved(subrangeItr->range->physicalRegister);
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if (subrangeItr->GetPhysicalRegister() >= 0)
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physRegSet.SetReserved(subrangeItr->GetPhysicalRegister());
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}
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// next
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subrangeItr = subrangeItr->link_segmentSubrangesGPR.next;
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subrangeItr = subrangeItr->link_allSegmentRanges.next;
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}
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}
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}
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bool _livenessRangeStartCompare(raLivenessSubrange_t* lhs, raLivenessSubrange_t* rhs) { return lhs->start.index < rhs->start.index; }
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bool _livenessRangeStartCompare(raLivenessRange* lhs, raLivenessRange* rhs) { return lhs->start.index < rhs->start.index; }
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void _sortSegmentAllSubrangesLinkedList(IMLSegment* imlSegment)
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{
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raLivenessSubrange_t* subrangeList[4096+1];
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raLivenessRange* subrangeList[4096+1];
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sint32 count = 0;
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// disassemble linked list
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raLivenessSubrange_t* subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
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raLivenessRange* subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
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while (subrangeItr)
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{
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if (count >= 4096)
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@ -268,7 +268,7 @@ void _sortSegmentAllSubrangesLinkedList(IMLSegment* imlSegment)
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subrangeList[count] = subrangeItr;
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count++;
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// next
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subrangeItr = subrangeItr->link_segmentSubrangesGPR.next;
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subrangeItr = subrangeItr->link_allSegmentRanges.next;
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}
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if (count == 0)
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{
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@ -280,12 +280,12 @@ void _sortSegmentAllSubrangesLinkedList(IMLSegment* imlSegment)
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// reassemble linked list
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subrangeList[count] = nullptr;
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imlSegment->raInfo.linkedList_allSubranges = subrangeList[0];
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subrangeList[0]->link_segmentSubrangesGPR.prev = nullptr;
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subrangeList[0]->link_segmentSubrangesGPR.next = subrangeList[1];
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subrangeList[0]->link_allSegmentRanges.prev = nullptr;
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subrangeList[0]->link_allSegmentRanges.next = subrangeList[1];
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for (sint32 i = 1; i < count; i++)
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{
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subrangeList[i]->link_segmentSubrangesGPR.prev = subrangeList[i - 1];
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subrangeList[i]->link_segmentSubrangesGPR.next = subrangeList[i + 1];
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subrangeList[i]->link_allSegmentRanges.prev = subrangeList[i - 1];
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subrangeList[i]->link_allSegmentRanges.next = subrangeList[i + 1];
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}
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// validate list
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#ifdef CEMU_DEBUG_ASSERT
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@ -299,40 +299,40 @@ void _sortSegmentAllSubrangesLinkedList(IMLSegment* imlSegment)
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assert_dbg();
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currentStartIndex = subrangeItr->start.index;
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// next
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subrangeItr = subrangeItr->link_segmentSubrangesGPR.next;
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subrangeItr = subrangeItr->link_allSegmentRanges.next;
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}
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if (count != count2)
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assert_dbg();
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#endif
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}
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std::unordered_map<IMLRegID, raLivenessSubrange_t*>& IMLRA_GetSubrangeMap(IMLSegment* imlSegment)
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std::unordered_map<IMLRegID, raLivenessRange*>& IMLRA_GetSubrangeMap(IMLSegment* imlSegment)
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{
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return imlSegment->raInfo.linkedList_perVirtualGPR2;
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return imlSegment->raInfo.linkedList_perVirtualRegister;
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}
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raLivenessSubrange_t* IMLRA_GetSubrange(IMLSegment* imlSegment, IMLRegID regId)
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raLivenessRange* IMLRA_GetSubrange(IMLSegment* imlSegment, IMLRegID regId)
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{
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auto it = imlSegment->raInfo.linkedList_perVirtualGPR2.find(regId);
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if (it == imlSegment->raInfo.linkedList_perVirtualGPR2.end())
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auto it = imlSegment->raInfo.linkedList_perVirtualRegister.find(regId);
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if (it == imlSegment->raInfo.linkedList_perVirtualRegister.end())
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return nullptr;
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return it->second;
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}
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raLivenessSubrange_t* _GetSubrangeByInstructionIndexAndVirtualReg(IMLSegment* imlSegment, IMLReg regToSearch, sint32 instructionIndex)
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raLivenessRange* _GetSubrangeByInstructionIndexAndVirtualReg(IMLSegment* imlSegment, IMLReg regToSearch, sint32 instructionIndex)
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{
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uint32 regId = regToSearch.GetRegID();
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raLivenessSubrange_t* subrangeItr = IMLRA_GetSubrange(imlSegment, regId);
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raLivenessRange* subrangeItr = IMLRA_GetSubrange(imlSegment, regId);
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while (subrangeItr)
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{
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if (subrangeItr->start.index <= instructionIndex && subrangeItr->end.index > instructionIndex)
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return subrangeItr;
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subrangeItr = subrangeItr->link_sameVirtualRegisterGPR.next;
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subrangeItr = subrangeItr->link_sameVirtualRegister.next;
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}
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return nullptr;
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}
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void IMLRA_IsolateRangeOnInstruction(ppcImlGenContext_t* ppcImlGenContext, IMLSegment* imlSegment, raLivenessSubrange_t* subrange, sint32 instructionIndex)
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void IMLRA_IsolateRangeOnInstruction(ppcImlGenContext_t* ppcImlGenContext, IMLSegment* imlSegment, raLivenessRange* subrange, sint32 instructionIndex)
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{
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DEBUG_BREAK;
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}
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@ -381,42 +381,42 @@ bool IMLRA_AssignSegmentRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGenCon
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_sortSegmentAllSubrangesLinkedList(imlSegment);
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IMLRALivenessTimeline livenessTimeline;
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raLivenessSubrange_t* subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
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raLivenessRange* subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
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while(subrangeItr)
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{
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sint32 currentIndex = subrangeItr->start.index;
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PPCRecRA_debugValidateSubrange(subrangeItr);
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livenessTimeline.ExpireRanges(std::min<sint32>(currentIndex, RA_INTER_RANGE_END-1)); // expire up to currentIndex (inclusive), but exclude infinite ranges
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// if subrange already has register assigned then add it to the active list and continue
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if (subrangeItr->range->physicalRegister >= 0)
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if (subrangeItr->GetPhysicalRegister() >= 0)
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{
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// verify if register is actually available
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#ifdef CEMU_DEBUG_ASSERT
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for (auto& liverangeItr : livenessTimeline.activeRanges)
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{
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// check for register mismatch
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cemu_assert_debug(liverangeItr->range->physicalRegister != subrangeItr->range->physicalRegister);
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cemu_assert_debug(liverangeItr->GetPhysicalRegister() != subrangeItr->GetPhysicalRegister());
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}
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#endif
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livenessTimeline.AddActiveRange(subrangeItr);
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subrangeItr = subrangeItr->link_segmentSubrangesGPR.next;
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subrangeItr = subrangeItr->link_allSegmentRanges.next;
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continue;
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}
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// find free register for current subrangeItr and segment
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IMLRegFormat regBaseFormat = ctx.GetBaseFormatByRegId(subrangeItr->range->virtualRegister);
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IMLRegFormat regBaseFormat = ctx.GetBaseFormatByRegId(subrangeItr->GetVirtualRegister());
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IMLPhysRegisterSet physRegSet = ctx.raParam->GetPhysRegPool(regBaseFormat);
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cemu_assert_debug(physRegSet.HasAnyAvailable()); // register uses type with no valid pool
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for (auto& liverangeItr : livenessTimeline.activeRanges)
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{
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cemu_assert_debug(liverangeItr->range->physicalRegister >= 0);
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physRegSet.SetReserved(liverangeItr->range->physicalRegister);
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cemu_assert_debug(liverangeItr->GetPhysicalRegister() >= 0);
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physRegSet.SetReserved(liverangeItr->GetPhysicalRegister());
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}
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// check intersections with other ranges and determine allowed registers
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IMLPhysRegisterSet localAvailableRegsMask = physRegSet; // mask of registers that are currently not used (does not include range checks in other segments)
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if(physRegSet.HasAnyAvailable())
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{
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// check globally in all segments
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PPCRecRA_MaskOverlappingPhysRegForGlobalRange(subrangeItr->range, physRegSet);
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PPCRecRA_MaskOverlappingPhysRegForGlobalRange(subrangeItr, physRegSet);
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}
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if (!physRegSet.HasAnyAvailable())
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{
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@ -427,7 +427,7 @@ bool IMLRA_AssignSegmentRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGenCon
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struct
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{
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sint32 distance;
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raLivenessSubrange_t* largestHoleSubrange;
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raLivenessRange* largestHoleSubrange;
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sint32 cost; // additional cost of choosing this candidate
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}localRangeHoleCutting;
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// split current range (this is generally only a good choice when the current range is long but rarely used)
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@ -440,7 +440,7 @@ bool IMLRA_AssignSegmentRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGenCon
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// explode a inter-segment range (prefer ranges that are not read/written in this segment)
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struct
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{
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raLivenessRange_t* range;
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raLivenessRange* range;
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sint32 cost;
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sint32 distance; // size of hole
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// note: If we explode a range, we still have to check the size of the hole that becomes available, if too small then we need to add cost of splitting local subrange
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@ -540,7 +540,7 @@ bool IMLRA_AssignSegmentRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGenCon
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if( distance < 2)
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continue;
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sint32 cost;
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cost = PPCRecRARange_estimateAdditionalCostAfterRangeExplode(candidate->range);
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cost = PPCRecRARange_estimateCostAfterRangeExplode(candidate);
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// if the hole is not large enough, add cost of splitting current subrange
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if (distance < requiredSize)
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{
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@ -553,7 +553,7 @@ bool IMLRA_AssignSegmentRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGenCon
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{
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spillStrategies.explodeRange.cost = cost;
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spillStrategies.explodeRange.distance = distance;
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spillStrategies.explodeRange.range = candidate->range;
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spillStrategies.explodeRange.range = candidate;
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}
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}
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// choose strategy
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@ -581,7 +581,7 @@ bool IMLRA_AssignSegmentRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGenCon
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else if (subrangeItr->start.index == RA_INTER_RANGE_START)
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{
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// alternative strategy if we have no other choice: explode current range
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PPCRecRA_explodeRange(ppcImlGenContext, subrangeItr->range);
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PPCRecRA_explodeRange(ppcImlGenContext, subrangeItr);
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}
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else
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assert_dbg();
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@ -603,27 +603,27 @@ bool IMLRA_AssignSegmentRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGenCon
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if (candidate->end.index != RA_INTER_RANGE_END)
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continue;
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// only select candidates that clash with current subrange
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if (candidate->range->physicalRegister < 0 && candidate != subrangeItr)
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if (candidate->GetPhysicalRegister() < 0 && candidate != subrangeItr)
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continue;
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sint32 cost;
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cost = PPCRecRARange_estimateAdditionalCostAfterRangeExplode(candidate->range);
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cost = PPCRecRARange_estimateCostAfterRangeExplode(candidate);
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// compare with current best candidate for this strategy
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if (cost < spillStrategies.explodeRange.cost)
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{
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spillStrategies.explodeRange.cost = cost;
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spillStrategies.explodeRange.distance = INT_MAX;
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spillStrategies.explodeRange.range = candidate->range;
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spillStrategies.explodeRange.range = candidate;
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}
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}
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// add current range as a candidate too
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sint32 ownCost;
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ownCost = PPCRecRARange_estimateAdditionalCostAfterRangeExplode(subrangeItr->range);
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ownCost = PPCRecRARange_estimateCostAfterRangeExplode(subrangeItr);
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if (ownCost < spillStrategies.explodeRange.cost)
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{
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spillStrategies.explodeRange.cost = ownCost;
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spillStrategies.explodeRange.distance = INT_MAX;
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spillStrategies.explodeRange.range = subrangeItr->range;
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spillStrategies.explodeRange.range = subrangeItr;
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}
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if (spillStrategies.explodeRange.cost == INT_MAX)
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assert_dbg(); // should not happen
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@ -632,10 +632,11 @@ bool IMLRA_AssignSegmentRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGenCon
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return false;
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}
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// assign register to range
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subrangeItr->range->physicalRegister = physRegSet.GetFirstAvailableReg();
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//subrangeItr->SetPhysicalRegister(physRegSet.GetFirstAvailableReg());
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subrangeItr->SetPhysicalRegisterForCluster(physRegSet.GetFirstAvailableReg());
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livenessTimeline.AddActiveRange(subrangeItr);
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// next
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subrangeItr = subrangeItr->link_segmentSubrangesGPR.next;
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subrangeItr = subrangeItr->link_allSegmentRanges.next;
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}
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return true;
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}
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@ -673,137 +674,30 @@ void IMLRA_AssignRegisters(IMLRegisterAllocatorContext& ctx, ppcImlGenContext_t*
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}
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}
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struct subrangeEndingInfo_t
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{
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//boost::container::small_vector<raLivenessSubrange_t*, 32> subrangeList2;
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raLivenessSubrange_t* subrangeList[SUBRANGE_LIST_SIZE];
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sint32 subrangeCount;
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bool hasUndefinedEndings;
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};
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|
||||
void _findSubrangeWriteEndings(raLivenessSubrange_t* subrange, uint32 iterationIndex, sint32 depth, subrangeEndingInfo_t* info)
|
||||
{
|
||||
if (depth >= 30)
|
||||
{
|
||||
info->hasUndefinedEndings = true;
|
||||
return;
|
||||
}
|
||||
if (subrange->lastIterationIndex == iterationIndex)
|
||||
return; // already processed
|
||||
subrange->lastIterationIndex = iterationIndex;
|
||||
if (subrange->hasStoreDelayed)
|
||||
return; // no need to traverse this subrange
|
||||
IMLSegment* imlSegment = subrange->imlSegment;
|
||||
if (subrange->end.index != RA_INTER_RANGE_END)
|
||||
{
|
||||
// ending segment
|
||||
if (info->subrangeCount >= SUBRANGE_LIST_SIZE)
|
||||
{
|
||||
info->hasUndefinedEndings = true;
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
info->subrangeList[info->subrangeCount] = subrange;
|
||||
info->subrangeCount++;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
// traverse next subranges in flow
|
||||
if (imlSegment->nextSegmentBranchNotTaken)
|
||||
{
|
||||
if (subrange->subrangeBranchNotTaken == nullptr)
|
||||
{
|
||||
info->hasUndefinedEndings = true;
|
||||
}
|
||||
else
|
||||
{
|
||||
_findSubrangeWriteEndings(subrange->subrangeBranchNotTaken, iterationIndex, depth + 1, info);
|
||||
}
|
||||
}
|
||||
if (imlSegment->nextSegmentBranchTaken)
|
||||
{
|
||||
if (subrange->subrangeBranchTaken == nullptr)
|
||||
{
|
||||
info->hasUndefinedEndings = true;
|
||||
}
|
||||
else
|
||||
{
|
||||
_findSubrangeWriteEndings(subrange->subrangeBranchTaken, iterationIndex, depth + 1, info);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void _analyzeRangeDataFlow(raLivenessSubrange_t* subrange)
|
||||
{
|
||||
if (subrange->end.index != RA_INTER_RANGE_END)
|
||||
return;
|
||||
// analyze data flow across segments (if this segment has writes)
|
||||
if (subrange->hasStore)
|
||||
{
|
||||
subrangeEndingInfo_t writeEndingInfo;
|
||||
writeEndingInfo.subrangeCount = 0;
|
||||
writeEndingInfo.hasUndefinedEndings = false;
|
||||
_findSubrangeWriteEndings(subrange, PPCRecRA_getNextIterationIndex(), 0, &writeEndingInfo);
|
||||
if (writeEndingInfo.hasUndefinedEndings == false)
|
||||
{
|
||||
// get cost of delaying store into endings
|
||||
sint32 delayStoreCost = 0;
|
||||
bool alreadyStoredInAllEndings = true;
|
||||
for (sint32 i = 0; i < writeEndingInfo.subrangeCount; i++)
|
||||
{
|
||||
raLivenessSubrange_t* subrangeItr = writeEndingInfo.subrangeList[i];
|
||||
if( subrangeItr->hasStore )
|
||||
continue; // this ending already stores, no extra cost
|
||||
alreadyStoredInAllEndings = false;
|
||||
sint32 storeCost = PPCRecRARange_getReadWriteCost(subrangeItr->imlSegment);
|
||||
delayStoreCost = std::max(storeCost, delayStoreCost);
|
||||
}
|
||||
if (alreadyStoredInAllEndings)
|
||||
{
|
||||
subrange->hasStore = false;
|
||||
subrange->hasStoreDelayed = true;
|
||||
}
|
||||
else if (delayStoreCost <= PPCRecRARange_getReadWriteCost(subrange->imlSegment))
|
||||
{
|
||||
subrange->hasStore = false;
|
||||
subrange->hasStoreDelayed = true;
|
||||
for (sint32 i = 0; i < writeEndingInfo.subrangeCount; i++)
|
||||
{
|
||||
raLivenessSubrange_t* subrangeItr = writeEndingInfo.subrangeList[i];
|
||||
subrangeItr->hasStore = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
inline IMLReg _MakeNativeReg(IMLRegFormat baseFormat, IMLRegID regId)
|
||||
{
|
||||
return IMLReg(baseFormat, baseFormat, 0, regId);
|
||||
}
|
||||
|
||||
void PPCRecRA_insertGPRLoadInstructions(IMLRegisterAllocatorContext& ctx, IMLSegment* imlSegment, sint32 insertIndex, std::span<raLivenessSubrange_t*> loadList)
|
||||
void PPCRecRA_insertGPRLoadInstructions(IMLRegisterAllocatorContext& ctx, IMLSegment* imlSegment, sint32 insertIndex, std::span<raLivenessRange*> loadList)
|
||||
{
|
||||
PPCRecompiler_pushBackIMLInstructions(imlSegment, insertIndex, loadList.size());
|
||||
for (sint32 i = 0; i < loadList.size(); i++)
|
||||
{
|
||||
IMLRegFormat baseFormat = ctx.regIdToBaseFormat[loadList[i]->range->virtualRegister];
|
||||
IMLRegFormat baseFormat = ctx.regIdToBaseFormat[loadList[i]->GetVirtualRegister()];
|
||||
cemu_assert_debug(baseFormat != IMLRegFormat::INVALID_FORMAT);
|
||||
imlSegment->imlList[insertIndex + i].make_r_name(_MakeNativeReg(baseFormat, loadList[i]->range->physicalRegister), loadList[i]->range->name);
|
||||
imlSegment->imlList[insertIndex + i].make_r_name(_MakeNativeReg(baseFormat, loadList[i]->GetPhysicalRegister()), loadList[i]->GetName());
|
||||
}
|
||||
}
|
||||
|
||||
void PPCRecRA_insertGPRStoreInstructions(IMLRegisterAllocatorContext& ctx, IMLSegment* imlSegment, sint32 insertIndex, std::span<raLivenessSubrange_t*> storeList)
|
||||
void PPCRecRA_insertGPRStoreInstructions(IMLRegisterAllocatorContext& ctx, IMLSegment* imlSegment, sint32 insertIndex, std::span<raLivenessRange*> storeList)
|
||||
{
|
||||
PPCRecompiler_pushBackIMLInstructions(imlSegment, insertIndex, storeList.size());
|
||||
for (size_t i = 0; i < storeList.size(); i++)
|
||||
{
|
||||
IMLRegFormat baseFormat = ctx.regIdToBaseFormat[storeList[i]->range->virtualRegister];
|
||||
IMLRegFormat baseFormat = ctx.regIdToBaseFormat[storeList[i]->GetVirtualRegister()];
|
||||
cemu_assert_debug(baseFormat != IMLRegFormat::INVALID_FORMAT);
|
||||
imlSegment->imlList[insertIndex + i].make_name_r(storeList[i]->range->name, _MakeNativeReg(baseFormat, storeList[i]->range->physicalRegister));
|
||||
imlSegment->imlList[insertIndex + i].make_name_r(storeList[i]->GetName(), _MakeNativeReg(baseFormat, storeList[i]->GetPhysicalRegister()));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -814,7 +708,7 @@ void IMLRA_GenerateSegmentMoveInstructions(IMLRegisterAllocatorContext& ctx, IML
|
|||
sint32 index = 0;
|
||||
sint32 suffixInstructionCount = imlSegment->HasSuffixInstruction() ? 1 : 0;
|
||||
// load register ranges that are supplied from previous segments
|
||||
raLivenessSubrange_t* subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
|
||||
raLivenessRange* subrangeItr = imlSegment->raInfo.linkedList_allSubranges;
|
||||
while(subrangeItr)
|
||||
{
|
||||
if (subrangeItr->start.index == RA_INTER_RANGE_START)
|
||||
|
|
@ -827,12 +721,12 @@ void IMLRA_GenerateSegmentMoveInstructions(IMLRegisterAllocatorContext& ctx, IML
|
|||
assert_dbg();
|
||||
}
|
||||
// update translation table
|
||||
cemu_assert_debug(!virtId2PhysRegIdMap.contains(subrangeItr->range->virtualRegister));
|
||||
cemu_assert_debug(!virtId2PhysRegIdMap.contains(subrangeItr->GetVirtualRegister()));
|
||||
#endif
|
||||
virtId2PhysRegIdMap.try_emplace(subrangeItr->range->virtualRegister, subrangeItr->range->physicalRegister);
|
||||
virtId2PhysRegIdMap.try_emplace(subrangeItr->GetVirtualRegister(), subrangeItr->GetPhysicalRegister());
|
||||
}
|
||||
// next
|
||||
subrangeItr = subrangeItr->link_segmentSubrangesGPR.next;
|
||||
subrangeItr = subrangeItr->link_allSegmentRanges.next;
|
||||
}
|
||||
// process instructions
|
||||
while(index < imlSegment->imlList.size() + 1)
|
||||
|
|
@ -842,7 +736,7 @@ void IMLRA_GenerateSegmentMoveInstructions(IMLRegisterAllocatorContext& ctx, IML
|
|||
for (auto& expiredRange : livenessTimeline.GetExpiredRanges())
|
||||
{
|
||||
// update translation table
|
||||
virtId2PhysRegIdMap.erase(expiredRange->range->virtualRegister);
|
||||
virtId2PhysRegIdMap.erase(expiredRange->GetVirtualRegister());
|
||||
// store GPR if required
|
||||
// special care has to be taken to execute any stores before the suffix instruction since trailing instructions may not get executed
|
||||
if (expiredRange->hasStore)
|
||||
|
|
@ -874,9 +768,9 @@ void IMLRA_GenerateSegmentMoveInstructions(IMLRegisterAllocatorContext& ctx, IML
|
|||
subrangeItr->start.index--;
|
||||
}
|
||||
// update translation table
|
||||
virtId2PhysRegIdMap.insert_or_assign(subrangeItr->range->virtualRegister, subrangeItr->range->physicalRegister);
|
||||
virtId2PhysRegIdMap.insert_or_assign(subrangeItr->GetVirtualRegister(), subrangeItr->GetPhysicalRegister());
|
||||
}
|
||||
subrangeItr = subrangeItr->link_segmentSubrangesGPR.next;
|
||||
subrangeItr = subrangeItr->link_allSegmentRanges.next;
|
||||
}
|
||||
// rewrite registers
|
||||
if (index < imlSegment->imlList.size())
|
||||
|
|
@ -885,12 +779,12 @@ void IMLRA_GenerateSegmentMoveInstructions(IMLRegisterAllocatorContext& ctx, IML
|
|||
index++;
|
||||
}
|
||||
// expire infinite subranges (subranges which cross the segment border)
|
||||
std::vector<raLivenessSubrange_t*> loadStoreList;
|
||||
std::vector<raLivenessRange*> loadStoreList;
|
||||
livenessTimeline.ExpireRanges(RA_INTER_RANGE_END);
|
||||
for (auto liverange : livenessTimeline.GetExpiredRanges())
|
||||
{
|
||||
// update translation table
|
||||
virtId2PhysRegIdMap.erase(liverange->range->virtualRegister);
|
||||
virtId2PhysRegIdMap.erase(liverange->GetVirtualRegister());
|
||||
// store GPR
|
||||
if (liverange->hasStore)
|
||||
loadStoreList.emplace_back(liverange);
|
||||
|
|
@ -910,10 +804,10 @@ void IMLRA_GenerateSegmentMoveInstructions(IMLRegisterAllocatorContext& ctx, IML
|
|||
if (subrangeItr->_noLoad == false)
|
||||
loadStoreList.emplace_back(subrangeItr);
|
||||
// update translation table
|
||||
virtId2PhysRegIdMap.try_emplace(subrangeItr->range->virtualRegister, subrangeItr->range->physicalRegister);
|
||||
virtId2PhysRegIdMap.try_emplace(subrangeItr->GetVirtualRegister(), subrangeItr->GetPhysicalRegister());
|
||||
}
|
||||
// next
|
||||
subrangeItr = subrangeItr->link_segmentSubrangesGPR.next;
|
||||
subrangeItr = subrangeItr->link_allSegmentRanges.next;
|
||||
}
|
||||
if (!loadStoreList.empty())
|
||||
PPCRecRA_insertGPRLoadInstructions(ctx, imlSegment, imlSegment->imlList.size() - suffixInstructionCount, loadStoreList);
|
||||
|
|
@ -1026,7 +920,7 @@ void IMLRA_CalculateLivenessRanges(IMLRegisterAllocatorContext& ctx)
|
|||
}
|
||||
}
|
||||
|
||||
raLivenessSubrange_t* PPCRecRA_convertToMappedRanges(IMLRegisterAllocatorContext& ctx, IMLSegment* imlSegment, sint32 vGPR, raLivenessRange_t* range)
|
||||
raLivenessRange* PPCRecRA_convertToMappedRanges(IMLRegisterAllocatorContext& ctx, IMLSegment* imlSegment, IMLRegID vGPR, IMLName name)
|
||||
{
|
||||
IMLRARegAbstractLiveness* abstractRange = _GetAbstractRange(ctx, imlSegment, vGPR);
|
||||
if (!abstractRange)
|
||||
|
|
@ -1034,7 +928,7 @@ raLivenessSubrange_t* PPCRecRA_convertToMappedRanges(IMLRegisterAllocatorContext
|
|||
if (abstractRange->isProcessed)
|
||||
{
|
||||
// return already existing segment
|
||||
raLivenessSubrange_t* existingRange = IMLRA_GetSubrange(imlSegment, vGPR);
|
||||
raLivenessRange* existingRange = IMLRA_GetSubrange(imlSegment, vGPR);
|
||||
cemu_assert_debug(existingRange);
|
||||
return existingRange;
|
||||
}
|
||||
|
|
@ -1043,7 +937,7 @@ raLivenessSubrange_t* PPCRecRA_convertToMappedRanges(IMLRegisterAllocatorContext
|
|||
#ifdef CEMU_DEBUG_ASSERT
|
||||
cemu_assert_debug(IMLRA_GetSubrange(imlSegment, vGPR) == nullptr);
|
||||
#endif
|
||||
raLivenessSubrange_t* subrange = PPCRecRA_createSubrange(ctx.deprGenContext, range, imlSegment, abstractRange->usageStart, abstractRange->usageEnd);
|
||||
raLivenessRange* subrange = PPCRecRA_createSubrange(ctx.deprGenContext, imlSegment, vGPR, name, abstractRange->usageStart, abstractRange->usageEnd);
|
||||
// traverse forward
|
||||
if (abstractRange->usageEnd == RA_INTER_RANGE_END)
|
||||
{
|
||||
|
|
@ -1052,7 +946,8 @@ raLivenessSubrange_t* PPCRecRA_convertToMappedRanges(IMLRegisterAllocatorContext
|
|||
IMLRARegAbstractLiveness* branchTakenRange = _GetAbstractRange(ctx, imlSegment->nextSegmentBranchTaken, vGPR);
|
||||
if (branchTakenRange && branchTakenRange->usageStart == RA_INTER_RANGE_START)
|
||||
{
|
||||
subrange->subrangeBranchTaken = PPCRecRA_convertToMappedRanges(ctx, imlSegment->nextSegmentBranchTaken, vGPR, range);
|
||||
subrange->subrangeBranchTaken = PPCRecRA_convertToMappedRanges(ctx, imlSegment->nextSegmentBranchTaken, vGPR, name);
|
||||
subrange->subrangeBranchTaken->previousRanges.push_back(subrange);
|
||||
cemu_assert_debug(subrange->subrangeBranchTaken->start.index == RA_INTER_RANGE_START);
|
||||
}
|
||||
}
|
||||
|
|
@ -1061,7 +956,8 @@ raLivenessSubrange_t* PPCRecRA_convertToMappedRanges(IMLRegisterAllocatorContext
|
|||
IMLRARegAbstractLiveness* branchNotTakenRange = _GetAbstractRange(ctx, imlSegment->nextSegmentBranchNotTaken, vGPR);
|
||||
if (branchNotTakenRange && branchNotTakenRange->usageStart == RA_INTER_RANGE_START)
|
||||
{
|
||||
subrange->subrangeBranchNotTaken = PPCRecRA_convertToMappedRanges(ctx, imlSegment->nextSegmentBranchNotTaken, vGPR, range);
|
||||
subrange->subrangeBranchNotTaken = PPCRecRA_convertToMappedRanges(ctx, imlSegment->nextSegmentBranchNotTaken, vGPR, name);
|
||||
subrange->subrangeBranchNotTaken->previousRanges.push_back(subrange);
|
||||
cemu_assert_debug(subrange->subrangeBranchNotTaken->start.index == RA_INTER_RANGE_START);
|
||||
}
|
||||
}
|
||||
|
|
@ -1075,7 +971,7 @@ raLivenessSubrange_t* PPCRecRA_convertToMappedRanges(IMLRegisterAllocatorContext
|
|||
if(!prevRange)
|
||||
continue;
|
||||
if (prevRange->usageEnd == RA_INTER_RANGE_END)
|
||||
PPCRecRA_convertToMappedRanges(ctx, it, vGPR, range);
|
||||
PPCRecRA_convertToMappedRanges(ctx, it, vGPR, name);
|
||||
}
|
||||
}
|
||||
// for subranges which exit the segment at the end there is a hard requirement that they cover the suffix instruction
|
||||
|
|
@ -1100,13 +996,12 @@ void IMLRA_ConvertAbstractToLivenessRanges(IMLRegisterAllocatorContext& ctx, IML
|
|||
if(it.second.isProcessed)
|
||||
continue;
|
||||
IMLRegID regId = it.first;
|
||||
raLivenessRange_t* range = PPCRecRA_createRangeBase(ctx.deprGenContext, regId, ctx.raParam->regIdToName.find(regId)->second);
|
||||
PPCRecRA_convertToMappedRanges(ctx, imlSegment, regId, range);
|
||||
PPCRecRA_convertToMappedRanges(ctx, imlSegment, regId, ctx.raParam->regIdToName.find(regId)->second);
|
||||
}
|
||||
// fill created ranges with read/write location indices
|
||||
// note that at this point there is only one range per register per segment
|
||||
// and the algorithm below relies on this
|
||||
const std::unordered_map<IMLRegID, raLivenessSubrange_t*>& regToSubrange = IMLRA_GetSubrangeMap(imlSegment);
|
||||
const std::unordered_map<IMLRegID, raLivenessRange*>& regToSubrange = IMLRA_GetSubrangeMap(imlSegment);
|
||||
size_t index = 0;
|
||||
IMLUsedRegisters gprTracking;
|
||||
while (index < imlSegment->imlList.size())
|
||||
|
|
@ -1114,7 +1009,7 @@ void IMLRA_ConvertAbstractToLivenessRanges(IMLRegisterAllocatorContext& ctx, IML
|
|||
imlSegment->imlList[index].CheckRegisterUsage(&gprTracking);
|
||||
gprTracking.ForEachAccessedGPR([&](IMLReg gprReg, bool isWritten) {
|
||||
IMLRegID gprId = gprReg.GetRegID();
|
||||
raLivenessSubrange_t* subrange = regToSubrange.find(gprId)->second;
|
||||
raLivenessRange* subrange = regToSubrange.find(gprId)->second;
|
||||
PPCRecRA_updateOrAddSubrangeLocation(subrange, index, !isWritten, isWritten);
|
||||
#ifdef CEMU_DEBUG_ASSERT
|
||||
if ((sint32)index < subrange->start.index)
|
||||
|
|
@ -1351,7 +1246,7 @@ void IMLRA_ProcessFlowAndCalculateLivenessRanges(IMLRegisterAllocatorContext& ct
|
|||
IMLRA_ConvertAbstractToLivenessRanges(ctx, segIt);
|
||||
}
|
||||
|
||||
void PPCRecRA_analyzeSubrangeDataDependencyV2(raLivenessSubrange_t* subrange)
|
||||
void PPCRecRA_analyzeSubrangeDataDependencyV2(raLivenessRange* subrange)
|
||||
{
|
||||
bool isRead = false;
|
||||
bool isWritten = false;
|
||||
|
|
@ -1376,23 +1271,135 @@ void PPCRecRA_analyzeSubrangeDataDependencyV2(raLivenessSubrange_t* subrange)
|
|||
subrange->_noLoad = true;
|
||||
}
|
||||
|
||||
void IMLRA_AnalyzeRangeDataFlow(ppcImlGenContext_t* ppcImlGenContext)
|
||||
|
||||
struct subrangeEndingInfo_t
|
||||
{
|
||||
// this function is called after _assignRegisters(), which means that all ranges are already final and wont change anymore
|
||||
// first do a per-subrange pass
|
||||
for (auto& range : ppcImlGenContext->raInfo.list_ranges)
|
||||
//boost::container::small_vector<raLivenessSubrange_t*, 32> subrangeList2;
|
||||
raLivenessRange* subrangeList[SUBRANGE_LIST_SIZE];
|
||||
sint32 subrangeCount;
|
||||
|
||||
bool hasUndefinedEndings;
|
||||
};
|
||||
|
||||
void _findSubrangeWriteEndings(raLivenessRange* subrange, uint32 iterationIndex, sint32 depth, subrangeEndingInfo_t* info)
|
||||
{
|
||||
if (depth >= 30)
|
||||
{
|
||||
for (auto& subrange : range->list_subranges)
|
||||
info->hasUndefinedEndings = true;
|
||||
return;
|
||||
}
|
||||
if (subrange->lastIterationIndex == iterationIndex)
|
||||
return; // already processed
|
||||
subrange->lastIterationIndex = iterationIndex;
|
||||
if (subrange->hasStoreDelayed)
|
||||
return; // no need to traverse this subrange
|
||||
IMLSegment* imlSegment = subrange->imlSegment;
|
||||
if (subrange->end.index != RA_INTER_RANGE_END)
|
||||
{
|
||||
// ending segment
|
||||
if (info->subrangeCount >= SUBRANGE_LIST_SIZE)
|
||||
{
|
||||
PPCRecRA_analyzeSubrangeDataDependencyV2(subrange);
|
||||
info->hasUndefinedEndings = true;
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
info->subrangeList[info->subrangeCount] = subrange;
|
||||
info->subrangeCount++;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
// traverse next subranges in flow
|
||||
if (imlSegment->nextSegmentBranchNotTaken)
|
||||
{
|
||||
if (subrange->subrangeBranchNotTaken == nullptr)
|
||||
{
|
||||
info->hasUndefinedEndings = true;
|
||||
}
|
||||
else
|
||||
{
|
||||
_findSubrangeWriteEndings(subrange->subrangeBranchNotTaken, iterationIndex, depth + 1, info);
|
||||
}
|
||||
}
|
||||
// then do a second pass where we scan along subrange flow
|
||||
for (auto& range : ppcImlGenContext->raInfo.list_ranges)
|
||||
if (imlSegment->nextSegmentBranchTaken)
|
||||
{
|
||||
for (auto& subrange : range->list_subranges) // todo - traversing this backwards should be faster and yield better results due to the nature of the algorithm
|
||||
if (subrange->subrangeBranchTaken == nullptr)
|
||||
{
|
||||
info->hasUndefinedEndings = true;
|
||||
}
|
||||
else
|
||||
{
|
||||
_findSubrangeWriteEndings(subrange->subrangeBranchTaken, iterationIndex, depth + 1, info);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void _analyzeRangeDataFlow(raLivenessRange* subrange)
|
||||
{
|
||||
if (subrange->end.index != RA_INTER_RANGE_END)
|
||||
return;
|
||||
// analyze data flow across segments (if this segment has writes)
|
||||
if (subrange->hasStore)
|
||||
{
|
||||
subrangeEndingInfo_t writeEndingInfo;
|
||||
writeEndingInfo.subrangeCount = 0;
|
||||
writeEndingInfo.hasUndefinedEndings = false;
|
||||
_findSubrangeWriteEndings(subrange, PPCRecRA_getNextIterationIndex(), 0, &writeEndingInfo);
|
||||
if (writeEndingInfo.hasUndefinedEndings == false)
|
||||
{
|
||||
// get cost of delaying store into endings
|
||||
sint32 delayStoreCost = 0;
|
||||
bool alreadyStoredInAllEndings = true;
|
||||
for (sint32 i = 0; i < writeEndingInfo.subrangeCount; i++)
|
||||
{
|
||||
raLivenessRange* subrangeItr = writeEndingInfo.subrangeList[i];
|
||||
if( subrangeItr->hasStore )
|
||||
continue; // this ending already stores, no extra cost
|
||||
alreadyStoredInAllEndings = false;
|
||||
sint32 storeCost = PPCRecRARange_getReadWriteCost(subrangeItr->imlSegment);
|
||||
delayStoreCost = std::max(storeCost, delayStoreCost);
|
||||
}
|
||||
if (alreadyStoredInAllEndings)
|
||||
{
|
||||
subrange->hasStore = false;
|
||||
subrange->hasStoreDelayed = true;
|
||||
}
|
||||
else if (delayStoreCost <= PPCRecRARange_getReadWriteCost(subrange->imlSegment))
|
||||
{
|
||||
subrange->hasStore = false;
|
||||
subrange->hasStoreDelayed = true;
|
||||
for (sint32 i = 0; i < writeEndingInfo.subrangeCount; i++)
|
||||
{
|
||||
raLivenessRange* subrangeItr = writeEndingInfo.subrangeList[i];
|
||||
subrangeItr->hasStore = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void IMLRA_AnalyzeRangeDataFlow(ppcImlGenContext_t* ppcImlGenContext)
|
||||
{
|
||||
// this function is called after _assignRegisters(), which means that all liveness ranges are already final and must not be changed anymore
|
||||
// in the first pass we track read/write dependencies
|
||||
for(auto& seg : ppcImlGenContext->segmentList2)
|
||||
{
|
||||
raLivenessRange* subrange = seg->raInfo.linkedList_allSubranges;
|
||||
while(subrange)
|
||||
{
|
||||
PPCRecRA_analyzeSubrangeDataDependencyV2(subrange);
|
||||
subrange = subrange->link_allSegmentRanges.next;
|
||||
}
|
||||
}
|
||||
// then we do a second pass where we scan along subrange flow
|
||||
for(auto& seg : ppcImlGenContext->segmentList2)
|
||||
{
|
||||
raLivenessRange* subrange = seg->raInfo.linkedList_allSubranges;
|
||||
while(subrange)
|
||||
{
|
||||
_analyzeRangeDataFlow(subrange);
|
||||
subrange = subrange->link_allSegmentRanges.next;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1407,8 +1414,6 @@ void IMLRegisterAllocator_AllocateRegisters(ppcImlGenContext_t* ppcImlGenContext
|
|||
|
||||
ppcImlGenContext->UpdateSegmentIndices(); // update momentaryIndex of each segment
|
||||
|
||||
ppcImlGenContext->raInfo.list_ranges = std::vector<raLivenessRange_t*>();
|
||||
|
||||
ctx.perSegmentAbstractRanges.resize(ppcImlGenContext->segmentList2.size());
|
||||
|
||||
IMLRA_CalculateLivenessRanges(ctx);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue